/drivers/gpu/drm/bridge/synopsys/ |
D | dw-hdmi.c | 220 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) in hdmi_writeb() function 269 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, in dw_hdmi_i2c_init() 272 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | in dw_hdmi_i2c_init() 277 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); in dw_hdmi_i2c_init() 280 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); in dw_hdmi_i2c_init() 283 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); in dw_hdmi_i2c_init() 284 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, in dw_hdmi_i2c_init() 288 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, in dw_hdmi_i2c_init() 292 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, in dw_hdmi_i2c_init() 382 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); in dw_hdmi_i2c_read() [all …]
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/drivers/gpu/drm/zte/ |
D | zx_hdmi.c | 60 static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val) in hdmi_writeb() function 72 hdmi_writeb(hdmi, offset, tmp); in hdmi_writeb_mask() 82 hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel); in zx_hdmi_infoframe_trans() 91 hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]); in zx_hdmi_infoframe_trans() 155 hdmi_writeb(hdmi, 0x222, 0x0); in zx_hdmi_phy_start() 156 hdmi_writeb(hdmi, 0x224, 0x4); in zx_hdmi_phy_start() 157 hdmi_writeb(hdmi, 0x909, 0x0); in zx_hdmi_phy_start() 158 hdmi_writeb(hdmi, 0x7b0, 0x90); in zx_hdmi_phy_start() 159 hdmi_writeb(hdmi, 0x7b1, 0x00); in zx_hdmi_phy_start() 160 hdmi_writeb(hdmi, 0x7b2, 0xa7); in zx_hdmi_phy_start() [all …]
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/drivers/gpu/drm/rockchip/ |
D | inno_hdmi.c | 154 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() function 165 hdmi_writeb(hdmi, offset, temp); in hdmi_modb() 174 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); in inno_hdmi_i2c_init() 175 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); in inno_hdmi_i2c_init() 178 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); in inno_hdmi_i2c_init() 179 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); in inno_hdmi_i2c_init() 196 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x6f); in inno_hdmi_set_pwr_mode() 197 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0xbb); in inno_hdmi_set_pwr_mode() 199 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); in inno_hdmi_set_pwr_mode() 200 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); in inno_hdmi_set_pwr_mode() [all …]
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D | rk3066_hdmi.c | 68 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() function 79 hdmi_writeb(hdmi, offset, temp); in hdmi_modb() 88 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); in rk3066_hdmi_i2c_init() 89 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); in rk3066_hdmi_i2c_init() 93 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); in rk3066_hdmi_i2c_init() 130 hdmi_writeb(hdmi, HDMI_SYS_CTRL, in rk3066_hdmi_set_power_mode() 134 hdmi_writeb(hdmi, HDMI_SYS_CTRL, in rk3066_hdmi_set_power_mode() 138 hdmi_writeb(hdmi, HDMI_SYS_CTRL, in rk3066_hdmi_set_power_mode() 163 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index); in rk3066_hdmi_upload_frame() 175 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, in rk3066_hdmi_upload_frame() [all …]
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/drivers/gpu/drm/bridge/ |
D | sii9234.c | 296 #define hdmi_writeb(sii9234, offset, value) \ macro 414 hdmi_writeb(ctx, HDMI_RX_TMDS_CLK_EN_REG, 0x01); in sii9234_power_init() 416 hdmi_writeb(ctx, HDMI_RX_TMDS_CH_EN_REG, 0x15); in sii9234_power_init() 424 hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1); in sii9234_hdmi_init() 425 hdmi_writeb(ctx, HDMI_RX_PLL_CALREFSEL_REG, 0x03); in sii9234_hdmi_init() 426 hdmi_writeb(ctx, HDMI_RX_PLL_VCOCAL_REG, 0x20); in sii9234_hdmi_init() 427 hdmi_writeb(ctx, HDMI_RX_EQ_DATA0_REG, 0x8A); in sii9234_hdmi_init() 428 hdmi_writeb(ctx, HDMI_RX_EQ_DATA1_REG, 0x6A); in sii9234_hdmi_init() 429 hdmi_writeb(ctx, HDMI_RX_EQ_DATA2_REG, 0xAA); in sii9234_hdmi_init() 430 hdmi_writeb(ctx, HDMI_RX_EQ_DATA3_REG, 0xCA); in sii9234_hdmi_init() [all …]
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