1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
21
22 #include <media/cec-notifier.h>
23
24 #include <uapi/linux/media-bus-format.h>
25 #include <uapi/linux/videodev2.h>
26
27 #include <drm/bridge/dw_hdmi.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_of.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/drm_scdc_helper.h>
36
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39 #include "dw-hdmi.h"
40
41 #define DDC_CI_ADDR 0x37
42 #define DDC_SEGMENT_ADDR 0x30
43
44 #define HDMI_EDID_LEN 512
45
46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
47 #define SCDC_MIN_SOURCE_VERSION 0x1
48
49 #define HDMI14_MAX_TMDSCLK 340000000
50
51 enum hdmi_datamap {
52 RGB444_8B = 0x01,
53 RGB444_10B = 0x03,
54 RGB444_12B = 0x05,
55 RGB444_16B = 0x07,
56 YCbCr444_8B = 0x09,
57 YCbCr444_10B = 0x0B,
58 YCbCr444_12B = 0x0D,
59 YCbCr444_16B = 0x0F,
60 YCbCr422_8B = 0x16,
61 YCbCr422_10B = 0x14,
62 YCbCr422_12B = 0x12,
63 };
64
65 static const u16 csc_coeff_default[3][4] = {
66 { 0x2000, 0x0000, 0x0000, 0x0000 },
67 { 0x0000, 0x2000, 0x0000, 0x0000 },
68 { 0x0000, 0x0000, 0x2000, 0x0000 }
69 };
70
71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
72 { 0x2000, 0x6926, 0x74fd, 0x010e },
73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
74 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
75 };
76
77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
78 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
79 { 0x2000, 0x3264, 0x0000, 0x7e6d },
80 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
81 };
82
83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
84 { 0x2591, 0x1322, 0x074b, 0x0000 },
85 { 0x6535, 0x2000, 0x7acc, 0x0200 },
86 { 0x6acd, 0x7534, 0x2000, 0x0200 }
87 };
88
89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
91 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
92 { 0x6756, 0x78ab, 0x2000, 0x0200 }
93 };
94
95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
96 { 0x1b7c, 0x0000, 0x0000, 0x0020 },
97 { 0x0000, 0x1b7c, 0x0000, 0x0020 },
98 { 0x0000, 0x0000, 0x1b7c, 0x0020 }
99 };
100
101 struct hdmi_vmode {
102 bool mdataenablepolarity;
103
104 unsigned int mpixelclock;
105 unsigned int mpixelrepetitioninput;
106 unsigned int mpixelrepetitionoutput;
107 unsigned int mtmdsclock;
108 };
109
110 struct hdmi_data_info {
111 unsigned int enc_in_bus_format;
112 unsigned int enc_out_bus_format;
113 unsigned int enc_in_encoding;
114 unsigned int enc_out_encoding;
115 unsigned int pix_repet_factor;
116 unsigned int hdcp_enable;
117 struct hdmi_vmode video_mode;
118 bool rgb_limited_range;
119 };
120
121 struct dw_hdmi_i2c {
122 struct i2c_adapter adap;
123
124 struct mutex lock; /* used to serialize data transfers */
125 struct completion cmp;
126 u8 stat;
127
128 u8 slave_reg;
129 bool is_regaddr;
130 bool is_segment;
131 };
132
133 struct dw_hdmi_phy_data {
134 enum dw_hdmi_phy_type type;
135 const char *name;
136 unsigned int gen;
137 bool has_svsret;
138 int (*configure)(struct dw_hdmi *hdmi,
139 const struct dw_hdmi_plat_data *pdata,
140 unsigned long mpixelclock);
141 };
142
143 struct dw_hdmi {
144 struct drm_connector connector;
145 struct drm_bridge bridge;
146 struct drm_bridge *next_bridge;
147
148 unsigned int version;
149
150 struct platform_device *audio;
151 struct platform_device *cec;
152 struct device *dev;
153 struct clk *isfr_clk;
154 struct clk *iahb_clk;
155 struct clk *cec_clk;
156 struct dw_hdmi_i2c *i2c;
157
158 struct hdmi_data_info hdmi_data;
159 const struct dw_hdmi_plat_data *plat_data;
160
161 int vic;
162
163 u8 edid[HDMI_EDID_LEN];
164
165 struct {
166 const struct dw_hdmi_phy_ops *ops;
167 const char *name;
168 void *data;
169 bool enabled;
170 } phy;
171
172 struct drm_display_mode previous_mode;
173
174 struct i2c_adapter *ddc;
175 void __iomem *regs;
176 bool sink_is_hdmi;
177 bool sink_has_audio;
178
179 struct pinctrl *pinctrl;
180 struct pinctrl_state *default_state;
181 struct pinctrl_state *unwedge_state;
182
183 struct mutex mutex; /* for state below and previous_mode */
184 enum drm_connector_force force; /* mutex-protected force state */
185 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
186 bool disabled; /* DRM has disabled our bridge */
187 bool bridge_is_on; /* indicates the bridge is on */
188 bool rxsense; /* rxsense state */
189 u8 phy_mask; /* desired phy int mask settings */
190 u8 mc_clkdis; /* clock disable register */
191
192 spinlock_t audio_lock;
193 struct mutex audio_mutex;
194 unsigned int sample_rate;
195 unsigned int audio_cts;
196 unsigned int audio_n;
197 bool audio_enable;
198
199 unsigned int reg_shift;
200 struct regmap *regm;
201 void (*enable_audio)(struct dw_hdmi *hdmi);
202 void (*disable_audio)(struct dw_hdmi *hdmi);
203
204 struct mutex cec_notifier_mutex;
205 struct cec_notifier *cec_notifier;
206
207 hdmi_codec_plugged_cb plugged_cb;
208 struct device *codec_dev;
209 enum drm_connector_status last_connector_result;
210 };
211
212 #define HDMI_IH_PHY_STAT0_RX_SENSE \
213 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
214 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
215
216 #define HDMI_PHY_RX_SENSE \
217 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
218 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
219
hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)220 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
221 {
222 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
223 }
224
hdmi_readb(struct dw_hdmi * hdmi,int offset)225 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
226 {
227 unsigned int val = 0;
228
229 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
230
231 return val;
232 }
233
handle_plugged_change(struct dw_hdmi * hdmi,bool plugged)234 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
235 {
236 if (hdmi->plugged_cb && hdmi->codec_dev)
237 hdmi->plugged_cb(hdmi->codec_dev, plugged);
238 }
239
dw_hdmi_set_plugged_cb(struct dw_hdmi * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)240 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
241 struct device *codec_dev)
242 {
243 bool plugged;
244
245 mutex_lock(&hdmi->mutex);
246 hdmi->plugged_cb = fn;
247 hdmi->codec_dev = codec_dev;
248 plugged = hdmi->last_connector_result == connector_status_connected;
249 handle_plugged_change(hdmi, plugged);
250 mutex_unlock(&hdmi->mutex);
251
252 return 0;
253 }
254 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
255
hdmi_modb(struct dw_hdmi * hdmi,u8 data,u8 mask,unsigned reg)256 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
257 {
258 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
259 }
260
hdmi_mask_writeb(struct dw_hdmi * hdmi,u8 data,unsigned int reg,u8 shift,u8 mask)261 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
262 u8 shift, u8 mask)
263 {
264 hdmi_modb(hdmi, data << shift, mask, reg);
265 }
266
dw_hdmi_i2c_init(struct dw_hdmi * hdmi)267 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
268 {
269 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
270 HDMI_PHY_I2CM_INT_ADDR);
271
272 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
273 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
274 HDMI_PHY_I2CM_CTLINT_ADDR);
275
276 /* Software reset */
277 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
278
279 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
280 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
281
282 /* Set done, not acknowledged and arbitration interrupt polarities */
283 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
284 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
285 HDMI_I2CM_CTLINT);
286
287 /* Clear DONE and ERROR interrupts */
288 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
289 HDMI_IH_I2CM_STAT0);
290
291 /* Mute DONE and ERROR interrupts */
292 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
293 HDMI_IH_MUTE_I2CM_STAT0);
294 }
295
dw_hdmi_i2c_unwedge(struct dw_hdmi * hdmi)296 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
297 {
298 /* If no unwedge state then give up */
299 if (!hdmi->unwedge_state)
300 return false;
301
302 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
303
304 /*
305 * This is a huge hack to workaround a problem where the dw_hdmi i2c
306 * bus could sometimes get wedged. Once wedged there doesn't appear
307 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
308 * other than pulsing the SDA line.
309 *
310 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
311 * by:
312 * 1. Remux the pin as a GPIO output, driven low.
313 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
314 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
315 *
316 * At the moment of remuxing, the line will still be low due to its
317 * recent stint as an output, but then it will be pulled high by the
318 * (presumed) external pullup. dw_hdmi seems to see this as a rising
319 * edge and that seems to get it out of its jam.
320 *
321 * This wedging was only ever seen on one TV, and only on one of
322 * its HDMI ports. It happened when the TV was powered on while the
323 * device was plugged in. A scope trace shows the TV bringing both SDA
324 * and SCL low, then bringing them both back up at roughly the same
325 * time. Presumably this confuses dw_hdmi because it saw activity but
326 * no real STOP (maybe it thinks there's another master on the bus?).
327 * Giving it a clean rising edge of SDA while SCL is already high
328 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
329 * of its stupor.
330 *
331 * Note that after coming back alive, transfers seem to immediately
332 * resume, so if we unwedge due to a timeout we should wait a little
333 * longer for our transfer to finish, since it might have just started
334 * now.
335 */
336 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
337 msleep(10);
338 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
339
340 return true;
341 }
342
dw_hdmi_i2c_wait(struct dw_hdmi * hdmi)343 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
344 {
345 struct dw_hdmi_i2c *i2c = hdmi->i2c;
346 int stat;
347
348 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
349 if (!stat) {
350 /* If we can't unwedge, return timeout */
351 if (!dw_hdmi_i2c_unwedge(hdmi))
352 return -EAGAIN;
353
354 /* We tried to unwedge; give it another chance */
355 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
356 if (!stat)
357 return -EAGAIN;
358 }
359
360 /* Check for error condition on the bus */
361 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
362 return -EIO;
363
364 return 0;
365 }
366
dw_hdmi_i2c_read(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)367 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
368 unsigned char *buf, unsigned int length)
369 {
370 struct dw_hdmi_i2c *i2c = hdmi->i2c;
371 int ret;
372
373 if (!i2c->is_regaddr) {
374 dev_dbg(hdmi->dev, "set read register address to 0\n");
375 i2c->slave_reg = 0x00;
376 i2c->is_regaddr = true;
377 }
378
379 while (length--) {
380 reinit_completion(&i2c->cmp);
381
382 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
383 if (i2c->is_segment)
384 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
385 HDMI_I2CM_OPERATION);
386 else
387 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
388 HDMI_I2CM_OPERATION);
389
390 ret = dw_hdmi_i2c_wait(hdmi);
391 if (ret)
392 return ret;
393
394 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
395 }
396 i2c->is_segment = false;
397
398 return 0;
399 }
400
dw_hdmi_i2c_write(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)401 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
402 unsigned char *buf, unsigned int length)
403 {
404 struct dw_hdmi_i2c *i2c = hdmi->i2c;
405 int ret;
406
407 if (!i2c->is_regaddr) {
408 /* Use the first write byte as register address */
409 i2c->slave_reg = buf[0];
410 length--;
411 buf++;
412 i2c->is_regaddr = true;
413 }
414
415 while (length--) {
416 reinit_completion(&i2c->cmp);
417
418 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
419 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
420 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
421 HDMI_I2CM_OPERATION);
422
423 ret = dw_hdmi_i2c_wait(hdmi);
424 if (ret)
425 return ret;
426 }
427
428 return 0;
429 }
430
dw_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)431 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
432 struct i2c_msg *msgs, int num)
433 {
434 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
435 struct dw_hdmi_i2c *i2c = hdmi->i2c;
436 u8 addr = msgs[0].addr;
437 int i, ret = 0;
438
439 if (addr == DDC_CI_ADDR)
440 /*
441 * The internal I2C controller does not support the multi-byte
442 * read and write operations needed for DDC/CI.
443 * TOFIX: Blacklist the DDC/CI address until we filter out
444 * unsupported I2C operations.
445 */
446 return -EOPNOTSUPP;
447
448 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
449
450 for (i = 0; i < num; i++) {
451 if (msgs[i].len == 0) {
452 dev_dbg(hdmi->dev,
453 "unsupported transfer %d/%d, no data\n",
454 i + 1, num);
455 return -EOPNOTSUPP;
456 }
457 }
458
459 mutex_lock(&i2c->lock);
460
461 /* Unmute DONE and ERROR interrupts */
462 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
463
464 /* Set slave device address taken from the first I2C message */
465 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
466
467 /* Set slave device register address on transfer */
468 i2c->is_regaddr = false;
469
470 /* Set segment pointer for I2C extended read mode operation */
471 i2c->is_segment = false;
472
473 for (i = 0; i < num; i++) {
474 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
475 i + 1, num, msgs[i].len, msgs[i].flags);
476 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
477 i2c->is_segment = true;
478 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
479 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
480 } else {
481 if (msgs[i].flags & I2C_M_RD)
482 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
483 msgs[i].len);
484 else
485 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
486 msgs[i].len);
487 }
488 if (ret < 0)
489 break;
490 }
491
492 if (!ret)
493 ret = num;
494
495 /* Mute DONE and ERROR interrupts */
496 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
497 HDMI_IH_MUTE_I2CM_STAT0);
498
499 mutex_unlock(&i2c->lock);
500
501 return ret;
502 }
503
dw_hdmi_i2c_func(struct i2c_adapter * adapter)504 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
505 {
506 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
507 }
508
509 static const struct i2c_algorithm dw_hdmi_algorithm = {
510 .master_xfer = dw_hdmi_i2c_xfer,
511 .functionality = dw_hdmi_i2c_func,
512 };
513
dw_hdmi_i2c_adapter(struct dw_hdmi * hdmi)514 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
515 {
516 struct i2c_adapter *adap;
517 struct dw_hdmi_i2c *i2c;
518 int ret;
519
520 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
521 if (!i2c)
522 return ERR_PTR(-ENOMEM);
523
524 mutex_init(&i2c->lock);
525 init_completion(&i2c->cmp);
526
527 adap = &i2c->adap;
528 adap->class = I2C_CLASS_DDC;
529 adap->owner = THIS_MODULE;
530 adap->dev.parent = hdmi->dev;
531 adap->algo = &dw_hdmi_algorithm;
532 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
533 i2c_set_adapdata(adap, hdmi);
534
535 ret = i2c_add_adapter(adap);
536 if (ret) {
537 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
538 devm_kfree(hdmi->dev, i2c);
539 return ERR_PTR(ret);
540 }
541
542 hdmi->i2c = i2c;
543
544 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
545
546 return adap;
547 }
548
hdmi_set_cts_n(struct dw_hdmi * hdmi,unsigned int cts,unsigned int n)549 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
550 unsigned int n)
551 {
552 /* Must be set/cleared first */
553 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
554
555 /* nshift factor = 0 */
556 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
557
558 /* Use automatic CTS generation mode when CTS is not set */
559 if (cts)
560 hdmi_writeb(hdmi, ((cts >> 16) &
561 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
562 HDMI_AUD_CTS3_CTS_MANUAL,
563 HDMI_AUD_CTS3);
564 else
565 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
566 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
567 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
568
569 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
570 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
571 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
572 }
573
hdmi_compute_n(unsigned int freq,unsigned long pixel_clk)574 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
575 {
576 unsigned int n = (128 * freq) / 1000;
577 unsigned int mult = 1;
578
579 while (freq > 48000) {
580 mult *= 2;
581 freq /= 2;
582 }
583
584 switch (freq) {
585 case 32000:
586 if (pixel_clk == 25175000)
587 n = 4576;
588 else if (pixel_clk == 27027000)
589 n = 4096;
590 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
591 n = 11648;
592 else
593 n = 4096;
594 n *= mult;
595 break;
596
597 case 44100:
598 if (pixel_clk == 25175000)
599 n = 7007;
600 else if (pixel_clk == 74176000)
601 n = 17836;
602 else if (pixel_clk == 148352000)
603 n = 8918;
604 else
605 n = 6272;
606 n *= mult;
607 break;
608
609 case 48000:
610 if (pixel_clk == 25175000)
611 n = 6864;
612 else if (pixel_clk == 27027000)
613 n = 6144;
614 else if (pixel_clk == 74176000)
615 n = 11648;
616 else if (pixel_clk == 148352000)
617 n = 5824;
618 else
619 n = 6144;
620 n *= mult;
621 break;
622
623 default:
624 break;
625 }
626
627 return n;
628 }
629
630 /*
631 * When transmitting IEC60958 linear PCM audio, these registers allow to
632 * configure the channel status information of all the channel status
633 * bits in the IEC60958 frame. For the moment this configuration is only
634 * used when the I2S audio interface, General Purpose Audio (GPA),
635 * or AHB audio DMA (AHBAUDDMA) interface is active
636 * (for S/PDIF interface this information comes from the stream).
637 */
dw_hdmi_set_channel_status(struct dw_hdmi * hdmi,u8 * channel_status)638 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
639 u8 *channel_status)
640 {
641 /*
642 * Set channel status register for frequency and word length.
643 * Use default values for other registers.
644 */
645 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
646 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
647 }
648 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
649
hdmi_set_clk_regenerator(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned int sample_rate)650 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
651 unsigned long pixel_clk, unsigned int sample_rate)
652 {
653 unsigned long ftdms = pixel_clk;
654 unsigned int n, cts;
655 u8 config3;
656 u64 tmp;
657
658 n = hdmi_compute_n(sample_rate, pixel_clk);
659
660 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
661
662 /* Only compute CTS when using internal AHB audio */
663 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
664 /*
665 * Compute the CTS value from the N value. Note that CTS and N
666 * can be up to 20 bits in total, so we need 64-bit math. Also
667 * note that our TDMS clock is not fully accurate; it is
668 * accurate to kHz. This can introduce an unnecessary remainder
669 * in the calculation below, so we don't try to warn about that.
670 */
671 tmp = (u64)ftdms * n;
672 do_div(tmp, 128 * sample_rate);
673 cts = tmp;
674
675 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
676 __func__, sample_rate,
677 ftdms / 1000000, (ftdms / 1000) % 1000,
678 n, cts);
679 } else {
680 cts = 0;
681 }
682
683 spin_lock_irq(&hdmi->audio_lock);
684 hdmi->audio_n = n;
685 hdmi->audio_cts = cts;
686 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
687 spin_unlock_irq(&hdmi->audio_lock);
688 }
689
hdmi_init_clk_regenerator(struct dw_hdmi * hdmi)690 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
691 {
692 mutex_lock(&hdmi->audio_mutex);
693 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
694 mutex_unlock(&hdmi->audio_mutex);
695 }
696
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi * hdmi)697 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
698 {
699 mutex_lock(&hdmi->audio_mutex);
700 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
701 hdmi->sample_rate);
702 mutex_unlock(&hdmi->audio_mutex);
703 }
704
dw_hdmi_set_sample_rate(struct dw_hdmi * hdmi,unsigned int rate)705 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
706 {
707 mutex_lock(&hdmi->audio_mutex);
708 hdmi->sample_rate = rate;
709 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
710 hdmi->sample_rate);
711 mutex_unlock(&hdmi->audio_mutex);
712 }
713 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
714
dw_hdmi_set_channel_count(struct dw_hdmi * hdmi,unsigned int cnt)715 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
716 {
717 u8 layout;
718
719 mutex_lock(&hdmi->audio_mutex);
720
721 /*
722 * For >2 channel PCM audio, we need to select layout 1
723 * and set an appropriate channel map.
724 */
725 if (cnt > 2)
726 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
727 else
728 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
729
730 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
731 HDMI_FC_AUDSCONF);
732
733 /* Set the audio infoframes channel count */
734 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
735 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
736
737 mutex_unlock(&hdmi->audio_mutex);
738 }
739 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
740
dw_hdmi_set_channel_allocation(struct dw_hdmi * hdmi,unsigned int ca)741 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
742 {
743 mutex_lock(&hdmi->audio_mutex);
744
745 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
746
747 mutex_unlock(&hdmi->audio_mutex);
748 }
749 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
750
hdmi_enable_audio_clk(struct dw_hdmi * hdmi,bool enable)751 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
752 {
753 if (enable)
754 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
755 else
756 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
757 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
758 }
759
hdmi_audio_get_eld(struct dw_hdmi * hdmi)760 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
761 {
762 if (!hdmi->curr_conn)
763 return NULL;
764
765 return hdmi->curr_conn->eld;
766 }
767
dw_hdmi_ahb_audio_enable(struct dw_hdmi * hdmi)768 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
769 {
770 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
771 }
772
dw_hdmi_ahb_audio_disable(struct dw_hdmi * hdmi)773 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
774 {
775 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
776 }
777
dw_hdmi_i2s_audio_enable(struct dw_hdmi * hdmi)778 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
779 {
780 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
781 hdmi_enable_audio_clk(hdmi, true);
782 }
783
dw_hdmi_i2s_audio_disable(struct dw_hdmi * hdmi)784 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
785 {
786 hdmi_enable_audio_clk(hdmi, false);
787 }
788
dw_hdmi_audio_enable(struct dw_hdmi * hdmi)789 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
790 {
791 unsigned long flags;
792
793 spin_lock_irqsave(&hdmi->audio_lock, flags);
794 hdmi->audio_enable = true;
795 if (hdmi->enable_audio)
796 hdmi->enable_audio(hdmi);
797 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
798 }
799 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
800
dw_hdmi_audio_disable(struct dw_hdmi * hdmi)801 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
802 {
803 unsigned long flags;
804
805 spin_lock_irqsave(&hdmi->audio_lock, flags);
806 hdmi->audio_enable = false;
807 if (hdmi->disable_audio)
808 hdmi->disable_audio(hdmi);
809 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
810 }
811 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
812
hdmi_bus_fmt_is_rgb(unsigned int bus_format)813 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
814 {
815 switch (bus_format) {
816 case MEDIA_BUS_FMT_RGB888_1X24:
817 case MEDIA_BUS_FMT_RGB101010_1X30:
818 case MEDIA_BUS_FMT_RGB121212_1X36:
819 case MEDIA_BUS_FMT_RGB161616_1X48:
820 return true;
821
822 default:
823 return false;
824 }
825 }
826
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)827 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
828 {
829 switch (bus_format) {
830 case MEDIA_BUS_FMT_YUV8_1X24:
831 case MEDIA_BUS_FMT_YUV10_1X30:
832 case MEDIA_BUS_FMT_YUV12_1X36:
833 case MEDIA_BUS_FMT_YUV16_1X48:
834 return true;
835
836 default:
837 return false;
838 }
839 }
840
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)841 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
842 {
843 switch (bus_format) {
844 case MEDIA_BUS_FMT_UYVY8_1X16:
845 case MEDIA_BUS_FMT_UYVY10_1X20:
846 case MEDIA_BUS_FMT_UYVY12_1X24:
847 return true;
848
849 default:
850 return false;
851 }
852 }
853
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)854 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
855 {
856 switch (bus_format) {
857 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
858 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
859 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
860 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
861 return true;
862
863 default:
864 return false;
865 }
866 }
867
hdmi_bus_fmt_color_depth(unsigned int bus_format)868 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
869 {
870 switch (bus_format) {
871 case MEDIA_BUS_FMT_RGB888_1X24:
872 case MEDIA_BUS_FMT_YUV8_1X24:
873 case MEDIA_BUS_FMT_UYVY8_1X16:
874 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
875 return 8;
876
877 case MEDIA_BUS_FMT_RGB101010_1X30:
878 case MEDIA_BUS_FMT_YUV10_1X30:
879 case MEDIA_BUS_FMT_UYVY10_1X20:
880 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
881 return 10;
882
883 case MEDIA_BUS_FMT_RGB121212_1X36:
884 case MEDIA_BUS_FMT_YUV12_1X36:
885 case MEDIA_BUS_FMT_UYVY12_1X24:
886 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
887 return 12;
888
889 case MEDIA_BUS_FMT_RGB161616_1X48:
890 case MEDIA_BUS_FMT_YUV16_1X48:
891 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
892 return 16;
893
894 default:
895 return 0;
896 }
897 }
898
899 /*
900 * this submodule is responsible for the video data synchronization.
901 * for example, for RGB 4:4:4 input, the data map is defined as
902 * pin{47~40} <==> R[7:0]
903 * pin{31~24} <==> G[7:0]
904 * pin{15~8} <==> B[7:0]
905 */
hdmi_video_sample(struct dw_hdmi * hdmi)906 static void hdmi_video_sample(struct dw_hdmi *hdmi)
907 {
908 int color_format = 0;
909 u8 val;
910
911 switch (hdmi->hdmi_data.enc_in_bus_format) {
912 case MEDIA_BUS_FMT_RGB888_1X24:
913 color_format = 0x01;
914 break;
915 case MEDIA_BUS_FMT_RGB101010_1X30:
916 color_format = 0x03;
917 break;
918 case MEDIA_BUS_FMT_RGB121212_1X36:
919 color_format = 0x05;
920 break;
921 case MEDIA_BUS_FMT_RGB161616_1X48:
922 color_format = 0x07;
923 break;
924
925 case MEDIA_BUS_FMT_YUV8_1X24:
926 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
927 color_format = 0x09;
928 break;
929 case MEDIA_BUS_FMT_YUV10_1X30:
930 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
931 color_format = 0x0B;
932 break;
933 case MEDIA_BUS_FMT_YUV12_1X36:
934 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
935 color_format = 0x0D;
936 break;
937 case MEDIA_BUS_FMT_YUV16_1X48:
938 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
939 color_format = 0x0F;
940 break;
941
942 case MEDIA_BUS_FMT_UYVY8_1X16:
943 color_format = 0x16;
944 break;
945 case MEDIA_BUS_FMT_UYVY10_1X20:
946 color_format = 0x14;
947 break;
948 case MEDIA_BUS_FMT_UYVY12_1X24:
949 color_format = 0x12;
950 break;
951
952 default:
953 return;
954 }
955
956 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
957 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
958 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
959 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
960
961 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
962 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
963 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
964 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
965 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
966 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
967 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
968 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
969 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
970 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
971 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
972 }
973
is_color_space_conversion(struct dw_hdmi * hdmi)974 static int is_color_space_conversion(struct dw_hdmi *hdmi)
975 {
976 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
977 bool is_input_rgb, is_output_rgb;
978
979 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
980 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
981
982 return (is_input_rgb != is_output_rgb) ||
983 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
984 }
985
is_color_space_decimation(struct dw_hdmi * hdmi)986 static int is_color_space_decimation(struct dw_hdmi *hdmi)
987 {
988 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
989 return 0;
990
991 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
992 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
993 return 1;
994
995 return 0;
996 }
997
is_color_space_interpolation(struct dw_hdmi * hdmi)998 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
999 {
1000 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1001 return 0;
1002
1003 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1004 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1005 return 1;
1006
1007 return 0;
1008 }
1009
is_csc_needed(struct dw_hdmi * hdmi)1010 static bool is_csc_needed(struct dw_hdmi *hdmi)
1011 {
1012 return is_color_space_conversion(hdmi) ||
1013 is_color_space_decimation(hdmi) ||
1014 is_color_space_interpolation(hdmi);
1015 }
1016
dw_hdmi_update_csc_coeffs(struct dw_hdmi * hdmi)1017 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1018 {
1019 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1020 bool is_input_rgb, is_output_rgb;
1021 unsigned i;
1022 u32 csc_scale = 1;
1023
1024 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1025 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1026
1027 if (!is_input_rgb && is_output_rgb) {
1028 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1029 csc_coeff = &csc_coeff_rgb_out_eitu601;
1030 else
1031 csc_coeff = &csc_coeff_rgb_out_eitu709;
1032 } else if (is_input_rgb && !is_output_rgb) {
1033 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1034 csc_coeff = &csc_coeff_rgb_in_eitu601;
1035 else
1036 csc_coeff = &csc_coeff_rgb_in_eitu709;
1037 csc_scale = 0;
1038 } else if (is_input_rgb && is_output_rgb &&
1039 hdmi->hdmi_data.rgb_limited_range) {
1040 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1041 }
1042
1043 /* The CSC registers are sequential, alternating MSB then LSB */
1044 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1045 u16 coeff_a = (*csc_coeff)[0][i];
1046 u16 coeff_b = (*csc_coeff)[1][i];
1047 u16 coeff_c = (*csc_coeff)[2][i];
1048
1049 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1050 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1051 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1052 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1053 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1054 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1055 }
1056
1057 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1058 HDMI_CSC_SCALE);
1059 }
1060
hdmi_video_csc(struct dw_hdmi * hdmi)1061 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1062 {
1063 int color_depth = 0;
1064 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1065 int decimation = 0;
1066
1067 /* YCC422 interpolation to 444 mode */
1068 if (is_color_space_interpolation(hdmi))
1069 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1070 else if (is_color_space_decimation(hdmi))
1071 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1072
1073 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1074 case 8:
1075 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1076 break;
1077 case 10:
1078 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1079 break;
1080 case 12:
1081 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1082 break;
1083 case 16:
1084 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1085 break;
1086
1087 default:
1088 return;
1089 }
1090
1091 /* Configure the CSC registers */
1092 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1093 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1094 HDMI_CSC_SCALE);
1095
1096 dw_hdmi_update_csc_coeffs(hdmi);
1097 }
1098
1099 /*
1100 * HDMI video packetizer is used to packetize the data.
1101 * for example, if input is YCC422 mode or repeater is used,
1102 * data should be repacked this module can be bypassed.
1103 */
hdmi_video_packetize(struct dw_hdmi * hdmi)1104 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1105 {
1106 unsigned int color_depth = 0;
1107 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1108 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1109 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1110 u8 val, vp_conf;
1111
1112 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1113 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1114 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1115 switch (hdmi_bus_fmt_color_depth(
1116 hdmi->hdmi_data.enc_out_bus_format)) {
1117 case 8:
1118 color_depth = 4;
1119 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1120 break;
1121 case 10:
1122 color_depth = 5;
1123 break;
1124 case 12:
1125 color_depth = 6;
1126 break;
1127 case 16:
1128 color_depth = 7;
1129 break;
1130 default:
1131 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1132 }
1133 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1134 switch (hdmi_bus_fmt_color_depth(
1135 hdmi->hdmi_data.enc_out_bus_format)) {
1136 case 0:
1137 case 8:
1138 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1139 break;
1140 case 10:
1141 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1142 break;
1143 case 12:
1144 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1145 break;
1146
1147 default:
1148 return;
1149 }
1150 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1151 } else {
1152 return;
1153 }
1154
1155 /* set the packetizer registers */
1156 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1157 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1158 ((hdmi_data->pix_repet_factor <<
1159 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1160 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1161 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1162
1163 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1164 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1165
1166 /* Data from pixel repeater block */
1167 if (hdmi_data->pix_repet_factor > 1) {
1168 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1169 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1170 } else { /* data from packetizer block */
1171 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1172 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1173 }
1174
1175 hdmi_modb(hdmi, vp_conf,
1176 HDMI_VP_CONF_PR_EN_MASK |
1177 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1178
1179 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1180 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1181
1182 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1183
1184 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1185 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1186 HDMI_VP_CONF_PP_EN_ENABLE |
1187 HDMI_VP_CONF_YCC422_EN_DISABLE;
1188 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1189 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1190 HDMI_VP_CONF_PP_EN_DISABLE |
1191 HDMI_VP_CONF_YCC422_EN_ENABLE;
1192 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1193 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1194 HDMI_VP_CONF_PP_EN_DISABLE |
1195 HDMI_VP_CONF_YCC422_EN_DISABLE;
1196 } else {
1197 return;
1198 }
1199
1200 hdmi_modb(hdmi, vp_conf,
1201 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1202 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1203
1204 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1205 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1206 HDMI_VP_STUFF_PP_STUFFING_MASK |
1207 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1208
1209 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1210 HDMI_VP_CONF);
1211 }
1212
1213 /* -----------------------------------------------------------------------------
1214 * Synopsys PHY Handling
1215 */
1216
hdmi_phy_test_clear(struct dw_hdmi * hdmi,unsigned char bit)1217 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1218 unsigned char bit)
1219 {
1220 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1221 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1222 }
1223
hdmi_phy_wait_i2c_done(struct dw_hdmi * hdmi,int msec)1224 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1225 {
1226 u32 val;
1227
1228 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1229 if (msec-- == 0)
1230 return false;
1231 udelay(1000);
1232 }
1233 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1234
1235 return true;
1236 }
1237
dw_hdmi_phy_i2c_write(struct dw_hdmi * hdmi,unsigned short data,unsigned char addr)1238 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1239 unsigned char addr)
1240 {
1241 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1242 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1243 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1244 HDMI_PHY_I2CM_DATAO_1_ADDR);
1245 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1246 HDMI_PHY_I2CM_DATAO_0_ADDR);
1247 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1248 HDMI_PHY_I2CM_OPERATION_ADDR);
1249 hdmi_phy_wait_i2c_done(hdmi, 1000);
1250 }
1251 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1252
1253 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi * hdmi,const struct drm_display_info * display)1254 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1255 const struct drm_display_info *display)
1256 {
1257 /* Completely disable SCDC support for older controllers */
1258 if (hdmi->version < 0x200a)
1259 return false;
1260
1261 /* Disable if no DDC bus */
1262 if (!hdmi->ddc)
1263 return false;
1264
1265 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1266 if (!display->hdmi.scdc.supported ||
1267 !display->hdmi.scdc.scrambling.supported)
1268 return false;
1269
1270 /*
1271 * Disable if display only support low TMDS rates and scrambling
1272 * for low rates is not supported either
1273 */
1274 if (!display->hdmi.scdc.scrambling.low_rates &&
1275 display->max_tmds_clock <= 340000)
1276 return false;
1277
1278 return true;
1279 }
1280
1281 /*
1282 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1283 * - The Source shall suspend transmission of the TMDS clock and data
1284 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1285 * from a 0 to a 1 or from a 1 to a 0
1286 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1287 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1288 * transmission of TMDS clock and data
1289 *
1290 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1291 * helper should called right before enabling the TMDS Clock and Data in
1292 * the PHY configuration callback.
1293 */
dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi * hdmi,const struct drm_display_info * display)1294 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1295 const struct drm_display_info *display)
1296 {
1297 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1298
1299 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1300 if (dw_hdmi_support_scdc(hdmi, display)) {
1301 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1302 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1303 else
1304 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1305 }
1306 }
1307 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1308
dw_hdmi_phy_enable_powerdown(struct dw_hdmi * hdmi,bool enable)1309 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1310 {
1311 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1312 HDMI_PHY_CONF0_PDZ_OFFSET,
1313 HDMI_PHY_CONF0_PDZ_MASK);
1314 }
1315
dw_hdmi_phy_enable_tmds(struct dw_hdmi * hdmi,u8 enable)1316 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1317 {
1318 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1319 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1320 HDMI_PHY_CONF0_ENTMDS_MASK);
1321 }
1322
dw_hdmi_phy_enable_svsret(struct dw_hdmi * hdmi,u8 enable)1323 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1324 {
1325 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1326 HDMI_PHY_CONF0_SVSRET_OFFSET,
1327 HDMI_PHY_CONF0_SVSRET_MASK);
1328 }
1329
dw_hdmi_phy_gen2_pddq(struct dw_hdmi * hdmi,u8 enable)1330 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1331 {
1332 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1333 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1334 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1335 }
1336 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1337
dw_hdmi_phy_gen2_txpwron(struct dw_hdmi * hdmi,u8 enable)1338 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1339 {
1340 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1341 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1342 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1343 }
1344 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1345
dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi * hdmi,u8 enable)1346 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1347 {
1348 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1349 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1350 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1351 }
1352
dw_hdmi_phy_sel_interface_control(struct dw_hdmi * hdmi,u8 enable)1353 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1354 {
1355 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1356 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1357 HDMI_PHY_CONF0_SELDIPIF_MASK);
1358 }
1359
dw_hdmi_phy_reset(struct dw_hdmi * hdmi)1360 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1361 {
1362 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1363 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1364 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1365 }
1366 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1367
dw_hdmi_phy_i2c_set_addr(struct dw_hdmi * hdmi,u8 address)1368 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1369 {
1370 hdmi_phy_test_clear(hdmi, 1);
1371 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1372 hdmi_phy_test_clear(hdmi, 0);
1373 }
1374 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1375
dw_hdmi_phy_power_off(struct dw_hdmi * hdmi)1376 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1377 {
1378 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1379 unsigned int i;
1380 u16 val;
1381
1382 if (phy->gen == 1) {
1383 dw_hdmi_phy_enable_tmds(hdmi, 0);
1384 dw_hdmi_phy_enable_powerdown(hdmi, true);
1385 return;
1386 }
1387
1388 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1389
1390 /*
1391 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1392 * to low power mode.
1393 */
1394 for (i = 0; i < 5; ++i) {
1395 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1396 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1397 break;
1398
1399 usleep_range(1000, 2000);
1400 }
1401
1402 if (val & HDMI_PHY_TX_PHY_LOCK)
1403 dev_warn(hdmi->dev, "PHY failed to power down\n");
1404 else
1405 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1406
1407 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1408 }
1409
dw_hdmi_phy_power_on(struct dw_hdmi * hdmi)1410 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1411 {
1412 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1413 unsigned int i;
1414 u8 val;
1415
1416 if (phy->gen == 1) {
1417 dw_hdmi_phy_enable_powerdown(hdmi, false);
1418
1419 /* Toggle TMDS enable. */
1420 dw_hdmi_phy_enable_tmds(hdmi, 0);
1421 dw_hdmi_phy_enable_tmds(hdmi, 1);
1422 return 0;
1423 }
1424
1425 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1426 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1427
1428 /* Wait for PHY PLL lock */
1429 for (i = 0; i < 5; ++i) {
1430 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1431 if (val)
1432 break;
1433
1434 usleep_range(1000, 2000);
1435 }
1436
1437 if (!val) {
1438 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1439 return -ETIMEDOUT;
1440 }
1441
1442 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1443 return 0;
1444 }
1445
1446 /*
1447 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1448 * information the DWC MHL PHY has the same register layout and is thus also
1449 * supported by this function.
1450 */
hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi * hdmi,const struct dw_hdmi_plat_data * pdata,unsigned long mpixelclock)1451 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1452 const struct dw_hdmi_plat_data *pdata,
1453 unsigned long mpixelclock)
1454 {
1455 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1456 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1457 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1458
1459 /* TOFIX Will need 420 specific PHY configuration tables */
1460
1461 /* PLL/MPLL Cfg - always match on final entry */
1462 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1463 if (mpixelclock <= mpll_config->mpixelclock)
1464 break;
1465
1466 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1467 if (mpixelclock <= curr_ctrl->mpixelclock)
1468 break;
1469
1470 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1471 if (mpixelclock <= phy_config->mpixelclock)
1472 break;
1473
1474 if (mpll_config->mpixelclock == ~0UL ||
1475 curr_ctrl->mpixelclock == ~0UL ||
1476 phy_config->mpixelclock == ~0UL)
1477 return -EINVAL;
1478
1479 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1480 HDMI_3D_TX_PHY_CPCE_CTRL);
1481 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1482 HDMI_3D_TX_PHY_GMPCTRL);
1483 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1484 HDMI_3D_TX_PHY_CURRCTRL);
1485
1486 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1487 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1488 HDMI_3D_TX_PHY_MSM_CTRL);
1489
1490 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1491 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1492 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1493 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1494 HDMI_3D_TX_PHY_VLEVCTRL);
1495
1496 /* Override and disable clock termination. */
1497 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1498 HDMI_3D_TX_PHY_CKCALCTRL);
1499
1500 return 0;
1501 }
1502
hdmi_phy_configure(struct dw_hdmi * hdmi,const struct drm_display_info * display)1503 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1504 const struct drm_display_info *display)
1505 {
1506 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1507 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1508 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1509 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1510 int ret;
1511
1512 dw_hdmi_phy_power_off(hdmi);
1513
1514 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1515
1516 /* Leave low power consumption mode by asserting SVSRET. */
1517 if (phy->has_svsret)
1518 dw_hdmi_phy_enable_svsret(hdmi, 1);
1519
1520 dw_hdmi_phy_reset(hdmi);
1521
1522 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1523
1524 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1525
1526 /* Write to the PHY as configured by the platform */
1527 if (pdata->configure_phy)
1528 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1529 else
1530 ret = phy->configure(hdmi, pdata, mpixelclock);
1531 if (ret) {
1532 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1533 mpixelclock);
1534 return ret;
1535 }
1536
1537 /* Wait for resuming transmission of TMDS clock and data */
1538 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1539 msleep(100);
1540
1541 return dw_hdmi_phy_power_on(hdmi);
1542 }
1543
dw_hdmi_phy_init(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * display,const struct drm_display_mode * mode)1544 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1545 const struct drm_display_info *display,
1546 const struct drm_display_mode *mode)
1547 {
1548 int i, ret;
1549
1550 /* HDMI Phy spec says to do the phy initialization sequence twice */
1551 for (i = 0; i < 2; i++) {
1552 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1553 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1554
1555 ret = hdmi_phy_configure(hdmi, display);
1556 if (ret)
1557 return ret;
1558 }
1559
1560 return 0;
1561 }
1562
dw_hdmi_phy_disable(struct dw_hdmi * hdmi,void * data)1563 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1564 {
1565 dw_hdmi_phy_power_off(hdmi);
1566 }
1567
dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)1568 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1569 void *data)
1570 {
1571 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1572 connector_status_connected : connector_status_disconnected;
1573 }
1574 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1575
dw_hdmi_phy_update_hpd(struct dw_hdmi * hdmi,void * data,bool force,bool disabled,bool rxsense)1576 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1577 bool force, bool disabled, bool rxsense)
1578 {
1579 u8 old_mask = hdmi->phy_mask;
1580
1581 if (force || disabled || !rxsense)
1582 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1583 else
1584 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1585
1586 if (old_mask != hdmi->phy_mask)
1587 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1588 }
1589 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1590
dw_hdmi_phy_setup_hpd(struct dw_hdmi * hdmi,void * data)1591 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1592 {
1593 /*
1594 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1595 * any pending interrupt.
1596 */
1597 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1598 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1599 HDMI_IH_PHY_STAT0);
1600
1601 /* Enable cable hot plug irq. */
1602 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1603
1604 /* Clear and unmute interrupts. */
1605 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1606 HDMI_IH_PHY_STAT0);
1607 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1608 HDMI_IH_MUTE_PHY_STAT0);
1609 }
1610 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1611
1612 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1613 .init = dw_hdmi_phy_init,
1614 .disable = dw_hdmi_phy_disable,
1615 .read_hpd = dw_hdmi_phy_read_hpd,
1616 .update_hpd = dw_hdmi_phy_update_hpd,
1617 .setup_hpd = dw_hdmi_phy_setup_hpd,
1618 };
1619
1620 /* -----------------------------------------------------------------------------
1621 * HDMI TX Setup
1622 */
1623
hdmi_tx_hdcp_config(struct dw_hdmi * hdmi)1624 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1625 {
1626 u8 de;
1627
1628 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1629 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1630 else
1631 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1632
1633 /* disable rx detect */
1634 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1635 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1636
1637 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1638
1639 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1640 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1641 }
1642
hdmi_config_AVI(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1643 static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1644 const struct drm_connector *connector,
1645 const struct drm_display_mode *mode)
1646 {
1647 struct hdmi_avi_infoframe frame;
1648 u8 val;
1649
1650 /* Initialise info frame from DRM mode */
1651 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1652
1653 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1654 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
1655 hdmi->hdmi_data.rgb_limited_range ?
1656 HDMI_QUANTIZATION_RANGE_LIMITED :
1657 HDMI_QUANTIZATION_RANGE_FULL);
1658 } else {
1659 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1660 frame.ycc_quantization_range =
1661 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1662 }
1663
1664 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1665 frame.colorspace = HDMI_COLORSPACE_YUV444;
1666 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1667 frame.colorspace = HDMI_COLORSPACE_YUV422;
1668 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1669 frame.colorspace = HDMI_COLORSPACE_YUV420;
1670 else
1671 frame.colorspace = HDMI_COLORSPACE_RGB;
1672
1673 /* Set up colorimetry */
1674 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1675 switch (hdmi->hdmi_data.enc_out_encoding) {
1676 case V4L2_YCBCR_ENC_601:
1677 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1678 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1679 else
1680 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1681 frame.extended_colorimetry =
1682 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1683 break;
1684 case V4L2_YCBCR_ENC_709:
1685 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1686 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1687 else
1688 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1689 frame.extended_colorimetry =
1690 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1691 break;
1692 default: /* Carries no data */
1693 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1694 frame.extended_colorimetry =
1695 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1696 break;
1697 }
1698 } else {
1699 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1700 frame.extended_colorimetry =
1701 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1702 }
1703
1704 /*
1705 * The Designware IP uses a different byte format from standard
1706 * AVI info frames, though generally the bits are in the correct
1707 * bytes.
1708 */
1709
1710 /*
1711 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1712 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1713 * bit 6 rather than 4.
1714 */
1715 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1716 if (frame.active_aspect & 15)
1717 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1718 if (frame.top_bar || frame.bottom_bar)
1719 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1720 if (frame.left_bar || frame.right_bar)
1721 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1722 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1723
1724 /* AVI data byte 2 differences: none */
1725 val = ((frame.colorimetry & 0x3) << 6) |
1726 ((frame.picture_aspect & 0x3) << 4) |
1727 (frame.active_aspect & 0xf);
1728 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1729
1730 /* AVI data byte 3 differences: none */
1731 val = ((frame.extended_colorimetry & 0x7) << 4) |
1732 ((frame.quantization_range & 0x3) << 2) |
1733 (frame.nups & 0x3);
1734 if (frame.itc)
1735 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1736 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1737
1738 /* AVI data byte 4 differences: none */
1739 val = frame.video_code & 0x7f;
1740 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1741
1742 /* AVI Data Byte 5- set up input and output pixel repetition */
1743 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1744 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1745 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1746 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1747 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1748 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1749 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1750
1751 /*
1752 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1753 * ycc range in bits 2,3 rather than 6,7
1754 */
1755 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1756 (frame.content_type & 0x3);
1757 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1758
1759 /* AVI Data Bytes 6-13 */
1760 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1761 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1762 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1763 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1764 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1765 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1766 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1767 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1768 }
1769
hdmi_config_vendor_specific_infoframe(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1770 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1771 const struct drm_connector *connector,
1772 const struct drm_display_mode *mode)
1773 {
1774 struct hdmi_vendor_infoframe frame;
1775 u8 buffer[10];
1776 ssize_t err;
1777
1778 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,
1779 mode);
1780 if (err < 0)
1781 /*
1782 * Going into that statement does not means vendor infoframe
1783 * fails. It just informed us that vendor infoframe is not
1784 * needed for the selected mode. Only 4k or stereoscopic 3D
1785 * mode requires vendor infoframe. So just simply return.
1786 */
1787 return;
1788
1789 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1790 if (err < 0) {
1791 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1792 err);
1793 return;
1794 }
1795 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1796 HDMI_FC_DATAUTO0_VSD_MASK);
1797
1798 /* Set the length of HDMI vendor specific InfoFrame payload */
1799 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1800
1801 /* Set 24bit IEEE Registration Identifier */
1802 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1803 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1804 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1805
1806 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1807 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1808 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1809
1810 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1811 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1812
1813 /* Packet frame interpolation */
1814 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1815
1816 /* Auto packets per frame and line spacing */
1817 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1818
1819 /* Configures the Frame Composer On RDRB mode */
1820 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1821 HDMI_FC_DATAUTO0_VSD_MASK);
1822 }
1823
hdmi_config_drm_infoframe(struct dw_hdmi * hdmi,const struct drm_connector * connector)1824 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1825 const struct drm_connector *connector)
1826 {
1827 const struct drm_connector_state *conn_state = connector->state;
1828 struct hdmi_drm_infoframe frame;
1829 u8 buffer[30];
1830 ssize_t err;
1831 int i;
1832
1833 if (!hdmi->plat_data->use_drm_infoframe)
1834 return;
1835
1836 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1837 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1838
1839 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1840 if (err < 0)
1841 return;
1842
1843 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1844 if (err < 0) {
1845 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1846 return;
1847 }
1848
1849 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1850 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1851
1852 for (i = 0; i < frame.length; i++)
1853 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1854
1855 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1856 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1857 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1858 }
1859
hdmi_av_composer(struct dw_hdmi * hdmi,const struct drm_display_info * display,const struct drm_display_mode * mode)1860 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1861 const struct drm_display_info *display,
1862 const struct drm_display_mode *mode)
1863 {
1864 u8 inv_val, bytes;
1865 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1866 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1867 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1868 unsigned int vdisplay, hdisplay;
1869
1870 vmode->mpixelclock = mode->clock * 1000;
1871
1872 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1873
1874 vmode->mtmdsclock = vmode->mpixelclock;
1875
1876 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1877 switch (hdmi_bus_fmt_color_depth(
1878 hdmi->hdmi_data.enc_out_bus_format)) {
1879 case 16:
1880 vmode->mtmdsclock = vmode->mpixelclock * 2;
1881 break;
1882 case 12:
1883 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
1884 break;
1885 case 10:
1886 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
1887 break;
1888 }
1889 }
1890
1891 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1892 vmode->mtmdsclock /= 2;
1893
1894 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
1895
1896 /* Set up HDMI_FC_INVIDCONF */
1897 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1898 (dw_hdmi_support_scdc(hdmi, display) &&
1899 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1900 hdmi_info->scdc.scrambling.low_rates)) ?
1901 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1902 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1903
1904 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1905 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1906 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1907
1908 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1909 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1910 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1911
1912 inv_val |= (vmode->mdataenablepolarity ?
1913 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1914 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1915
1916 if (hdmi->vic == 39)
1917 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1918 else
1919 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1920 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1921 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1922
1923 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1924 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1925 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1926
1927 inv_val |= hdmi->sink_is_hdmi ?
1928 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1929 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1930
1931 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1932
1933 hdisplay = mode->hdisplay;
1934 hblank = mode->htotal - mode->hdisplay;
1935 h_de_hs = mode->hsync_start - mode->hdisplay;
1936 hsync_len = mode->hsync_end - mode->hsync_start;
1937
1938 /*
1939 * When we're setting a YCbCr420 mode, we need
1940 * to adjust the horizontal timing to suit.
1941 */
1942 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1943 hdisplay /= 2;
1944 hblank /= 2;
1945 h_de_hs /= 2;
1946 hsync_len /= 2;
1947 }
1948
1949 vdisplay = mode->vdisplay;
1950 vblank = mode->vtotal - mode->vdisplay;
1951 v_de_vs = mode->vsync_start - mode->vdisplay;
1952 vsync_len = mode->vsync_end - mode->vsync_start;
1953
1954 /*
1955 * When we're setting an interlaced mode, we need
1956 * to adjust the vertical timing to suit.
1957 */
1958 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1959 vdisplay /= 2;
1960 vblank /= 2;
1961 v_de_vs /= 2;
1962 vsync_len /= 2;
1963 }
1964
1965 /* Scrambling Control */
1966 if (dw_hdmi_support_scdc(hdmi, display)) {
1967 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1968 hdmi_info->scdc.scrambling.low_rates) {
1969 /*
1970 * HDMI2.0 Specifies the following procedure:
1971 * After the Source Device has determined that
1972 * SCDC_Present is set (=1), the Source Device should
1973 * write the accurate Version of the Source Device
1974 * to the Source Version field in the SCDCS.
1975 * Source Devices compliant shall set the
1976 * Source Version = 1.
1977 */
1978 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1979 &bytes);
1980 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1981 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1982
1983 /* Enabled Scrambling in the Sink */
1984 drm_scdc_set_scrambling(hdmi->ddc, 1);
1985
1986 /*
1987 * To activate the scrambler feature, you must ensure
1988 * that the quasi-static configuration bit
1989 * fc_invidconf.HDCP_keepout is set at configuration
1990 * time, before the required mc_swrstzreq.tmdsswrst_req
1991 * reset request is issued.
1992 */
1993 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1994 HDMI_MC_SWRSTZ);
1995 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1996 } else {
1997 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1998 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1999 HDMI_MC_SWRSTZ);
2000 drm_scdc_set_scrambling(hdmi->ddc, 0);
2001 }
2002 }
2003
2004 /* Set up horizontal active pixel width */
2005 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
2006 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2007
2008 /* Set up vertical active lines */
2009 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2010 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2011
2012 /* Set up horizontal blanking pixel region width */
2013 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2014 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2015
2016 /* Set up vertical blanking pixel region width */
2017 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2018
2019 /* Set up HSYNC active edge delay width (in pixel clks) */
2020 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2021 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2022
2023 /* Set up VSYNC active edge delay (in lines) */
2024 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2025
2026 /* Set up HSYNC active pulse width (in pixel clks) */
2027 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2028 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2029
2030 /* Set up VSYNC active edge delay (in lines) */
2031 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2032 }
2033
2034 /* HDMI Initialization Step B.4 */
dw_hdmi_enable_video_path(struct dw_hdmi * hdmi)2035 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2036 {
2037 /* control period minimum duration */
2038 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2039 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2040 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2041
2042 /* Set to fill TMDS data channels */
2043 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2044 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2045 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2046
2047 /* Enable pixel clock and tmds data path */
2048 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2049 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2050 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2051 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2052 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2053 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2054 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2055
2056 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2057 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2058
2059 /* Enable csc path */
2060 if (is_csc_needed(hdmi)) {
2061 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2062 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2063
2064 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2065 HDMI_MC_FLOWCTRL);
2066 } else {
2067 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2068 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2069
2070 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2071 HDMI_MC_FLOWCTRL);
2072 }
2073 }
2074
2075 /* Workaround to clear the overflow condition */
dw_hdmi_clear_overflow(struct dw_hdmi * hdmi)2076 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2077 {
2078 unsigned int count;
2079 unsigned int i;
2080 u8 val;
2081
2082 /*
2083 * Under some circumstances the Frame Composer arithmetic unit can miss
2084 * an FC register write due to being busy processing the previous one.
2085 * The issue can be worked around by issuing a TMDS software reset and
2086 * then write one of the FC registers several times.
2087 *
2088 * The number of iterations matters and depends on the HDMI TX revision
2089 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2090 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2091 * as needing the workaround, with 4 iterations for v1.30a and 1
2092 * iteration for others.
2093 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2094 * the workaround with a single iteration.
2095 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2096 * been identified as needing the workaround with a single iteration.
2097 */
2098
2099 switch (hdmi->version) {
2100 case 0x130a:
2101 count = 4;
2102 break;
2103 case 0x131a:
2104 case 0x132a:
2105 case 0x200a:
2106 case 0x201a:
2107 case 0x211a:
2108 case 0x212a:
2109 count = 1;
2110 break;
2111 default:
2112 return;
2113 }
2114
2115 /* TMDS software reset */
2116 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2117
2118 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2119 for (i = 0; i < count; i++)
2120 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2121 }
2122
hdmi_disable_overflow_interrupts(struct dw_hdmi * hdmi)2123 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2124 {
2125 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2126 HDMI_IH_MUTE_FC_STAT2);
2127 }
2128
dw_hdmi_setup(struct dw_hdmi * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)2129 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2130 const struct drm_connector *connector,
2131 const struct drm_display_mode *mode)
2132 {
2133 int ret;
2134
2135 hdmi_disable_overflow_interrupts(hdmi);
2136
2137 hdmi->vic = drm_match_cea_mode(mode);
2138
2139 if (!hdmi->vic) {
2140 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2141 } else {
2142 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2143 }
2144
2145 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2146 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2147 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2148 (hdmi->vic == 17) || (hdmi->vic == 18))
2149 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2150 else
2151 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2152
2153 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2154 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2155
2156 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2157 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2158
2159 /* TOFIX: Get input encoding from plat data or fallback to none */
2160 if (hdmi->plat_data->input_bus_encoding)
2161 hdmi->hdmi_data.enc_in_encoding =
2162 hdmi->plat_data->input_bus_encoding;
2163 else
2164 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2165
2166 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2167 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2168
2169 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2170 drm_default_rgb_quant_range(mode) ==
2171 HDMI_QUANTIZATION_RANGE_LIMITED;
2172
2173 hdmi->hdmi_data.pix_repet_factor = 0;
2174 hdmi->hdmi_data.hdcp_enable = 0;
2175 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2176
2177 /* HDMI Initialization Step B.1 */
2178 hdmi_av_composer(hdmi, &connector->display_info, mode);
2179
2180 /* HDMI Initializateion Step B.2 */
2181 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2182 &connector->display_info,
2183 &hdmi->previous_mode);
2184 if (ret)
2185 return ret;
2186 hdmi->phy.enabled = true;
2187
2188 /* HDMI Initialization Step B.3 */
2189 dw_hdmi_enable_video_path(hdmi);
2190
2191 if (hdmi->sink_has_audio) {
2192 dev_dbg(hdmi->dev, "sink has audio support\n");
2193
2194 /* HDMI Initialization Step E - Configure audio */
2195 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2196 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2197 }
2198
2199 /* not for DVI mode */
2200 if (hdmi->sink_is_hdmi) {
2201 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2202
2203 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2204 hdmi_config_AVI(hdmi, connector, mode);
2205 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2206 hdmi_config_drm_infoframe(hdmi, connector);
2207 } else {
2208 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2209 }
2210
2211 hdmi_video_packetize(hdmi);
2212 hdmi_video_csc(hdmi);
2213 hdmi_video_sample(hdmi);
2214 hdmi_tx_hdcp_config(hdmi);
2215
2216 dw_hdmi_clear_overflow(hdmi);
2217
2218 return 0;
2219 }
2220
initialize_hdmi_ih_mutes(struct dw_hdmi * hdmi)2221 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2222 {
2223 u8 ih_mute;
2224
2225 /*
2226 * Boot up defaults are:
2227 * HDMI_IH_MUTE = 0x03 (disabled)
2228 * HDMI_IH_MUTE_* = 0x00 (enabled)
2229 *
2230 * Disable top level interrupt bits in HDMI block
2231 */
2232 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2233 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2234 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2235
2236 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2237
2238 /* by default mask all interrupts */
2239 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2240 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2241 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2242 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2243 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2244 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2245 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2246 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2247 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2248 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2249 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2250 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2251 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2252 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2253
2254 /* Disable interrupts in the IH_MUTE_* registers */
2255 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2256 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2257 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2258 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2259 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2260 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2261 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2262 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2263 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2264 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2265
2266 /* Enable top level interrupt bits in HDMI block */
2267 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2268 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2269 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2270 }
2271
dw_hdmi_poweron(struct dw_hdmi * hdmi)2272 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2273 {
2274 hdmi->bridge_is_on = true;
2275
2276 /*
2277 * The curr_conn field is guaranteed to be valid here, as this function
2278 * is only be called when !hdmi->disabled.
2279 */
2280 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2281 }
2282
dw_hdmi_poweroff(struct dw_hdmi * hdmi)2283 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2284 {
2285 if (hdmi->phy.enabled) {
2286 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2287 hdmi->phy.enabled = false;
2288 }
2289
2290 hdmi->bridge_is_on = false;
2291 }
2292
dw_hdmi_update_power(struct dw_hdmi * hdmi)2293 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2294 {
2295 int force = hdmi->force;
2296
2297 if (hdmi->disabled) {
2298 force = DRM_FORCE_OFF;
2299 } else if (force == DRM_FORCE_UNSPECIFIED) {
2300 if (hdmi->rxsense)
2301 force = DRM_FORCE_ON;
2302 else
2303 force = DRM_FORCE_OFF;
2304 }
2305
2306 if (force == DRM_FORCE_OFF) {
2307 if (hdmi->bridge_is_on)
2308 dw_hdmi_poweroff(hdmi);
2309 } else {
2310 if (!hdmi->bridge_is_on)
2311 dw_hdmi_poweron(hdmi);
2312 }
2313 }
2314
2315 /*
2316 * Adjust the detection of RXSENSE according to whether we have a forced
2317 * connection mode enabled, or whether we have been disabled. There is
2318 * no point processing RXSENSE interrupts if we have a forced connection
2319 * state, or DRM has us disabled.
2320 *
2321 * We also disable rxsense interrupts when we think we're disconnected
2322 * to avoid floating TDMS signals giving false rxsense interrupts.
2323 *
2324 * Note: we still need to listen for HPD interrupts even when DRM has us
2325 * disabled so that we can detect a connect event.
2326 */
dw_hdmi_update_phy_mask(struct dw_hdmi * hdmi)2327 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2328 {
2329 if (hdmi->phy.ops->update_hpd)
2330 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2331 hdmi->force, hdmi->disabled,
2332 hdmi->rxsense);
2333 }
2334
dw_hdmi_detect(struct dw_hdmi * hdmi)2335 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2336 {
2337 enum drm_connector_status result;
2338
2339 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2340
2341 mutex_lock(&hdmi->mutex);
2342 if (result != hdmi->last_connector_result) {
2343 dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2344 handle_plugged_change(hdmi,
2345 result == connector_status_connected);
2346 hdmi->last_connector_result = result;
2347 }
2348 mutex_unlock(&hdmi->mutex);
2349
2350 return result;
2351 }
2352
dw_hdmi_get_edid(struct dw_hdmi * hdmi,struct drm_connector * connector)2353 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
2354 struct drm_connector *connector)
2355 {
2356 struct edid *edid;
2357
2358 if (!hdmi->ddc)
2359 return NULL;
2360
2361 edid = drm_get_edid(connector, hdmi->ddc);
2362 if (!edid) {
2363 dev_dbg(hdmi->dev, "failed to get edid\n");
2364 return NULL;
2365 }
2366
2367 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2368 edid->width_cm, edid->height_cm);
2369
2370 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2371 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2372
2373 return edid;
2374 }
2375
2376 /* -----------------------------------------------------------------------------
2377 * DRM Connector Operations
2378 */
2379
2380 static enum drm_connector_status
dw_hdmi_connector_detect(struct drm_connector * connector,bool force)2381 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2382 {
2383 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2384 connector);
2385 return dw_hdmi_detect(hdmi);
2386 }
2387
dw_hdmi_connector_get_modes(struct drm_connector * connector)2388 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2389 {
2390 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2391 connector);
2392 struct edid *edid;
2393 int ret;
2394
2395 edid = dw_hdmi_get_edid(hdmi, connector);
2396 if (!edid)
2397 return 0;
2398
2399 drm_connector_update_edid_property(connector, edid);
2400 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2401 ret = drm_add_edid_modes(connector, edid);
2402 kfree(edid);
2403
2404 return ret;
2405 }
2406
dw_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)2407 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2408 struct drm_atomic_state *state)
2409 {
2410 struct drm_connector_state *old_state =
2411 drm_atomic_get_old_connector_state(state, connector);
2412 struct drm_connector_state *new_state =
2413 drm_atomic_get_new_connector_state(state, connector);
2414 struct drm_crtc *crtc = new_state->crtc;
2415 struct drm_crtc_state *crtc_state;
2416
2417 if (!crtc)
2418 return 0;
2419
2420 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
2421 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2422 if (IS_ERR(crtc_state))
2423 return PTR_ERR(crtc_state);
2424
2425 crtc_state->mode_changed = true;
2426 }
2427
2428 return 0;
2429 }
2430
dw_hdmi_connector_force(struct drm_connector * connector)2431 static void dw_hdmi_connector_force(struct drm_connector *connector)
2432 {
2433 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2434 connector);
2435
2436 mutex_lock(&hdmi->mutex);
2437 hdmi->force = connector->force;
2438 dw_hdmi_update_power(hdmi);
2439 dw_hdmi_update_phy_mask(hdmi);
2440 mutex_unlock(&hdmi->mutex);
2441 }
2442
2443 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2444 .fill_modes = drm_helper_probe_single_connector_modes,
2445 .detect = dw_hdmi_connector_detect,
2446 .destroy = drm_connector_cleanup,
2447 .force = dw_hdmi_connector_force,
2448 .reset = drm_atomic_helper_connector_reset,
2449 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2450 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2451 };
2452
2453 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2454 .get_modes = dw_hdmi_connector_get_modes,
2455 .atomic_check = dw_hdmi_connector_atomic_check,
2456 };
2457
dw_hdmi_connector_create(struct dw_hdmi * hdmi)2458 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2459 {
2460 struct drm_connector *connector = &hdmi->connector;
2461 struct cec_connector_info conn_info;
2462 struct cec_notifier *notifier;
2463
2464 if (hdmi->version >= 0x200a)
2465 connector->ycbcr_420_allowed =
2466 hdmi->plat_data->ycbcr_420_allowed;
2467 else
2468 connector->ycbcr_420_allowed = false;
2469
2470 connector->interlace_allowed = 1;
2471 connector->polled = DRM_CONNECTOR_POLL_HPD;
2472
2473 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2474
2475 drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2476 &dw_hdmi_connector_funcs,
2477 DRM_MODE_CONNECTOR_HDMIA,
2478 hdmi->ddc);
2479
2480 /*
2481 * drm_connector_attach_max_bpc_property() requires the
2482 * connector to have a state.
2483 */
2484 drm_atomic_helper_connector_reset(connector);
2485
2486 drm_connector_attach_max_bpc_property(connector, 8, 16);
2487
2488 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2489 drm_connector_attach_hdr_output_metadata_property(connector);
2490
2491 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2492
2493 cec_fill_conn_info_from_drm(&conn_info, connector);
2494
2495 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2496 if (!notifier)
2497 return -ENOMEM;
2498
2499 mutex_lock(&hdmi->cec_notifier_mutex);
2500 hdmi->cec_notifier = notifier;
2501 mutex_unlock(&hdmi->cec_notifier_mutex);
2502
2503 return 0;
2504 }
2505
2506 /* -----------------------------------------------------------------------------
2507 * DRM Bridge Operations
2508 */
2509
2510 /*
2511 * Possible output formats :
2512 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2513 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2514 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2515 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2516 * - MEDIA_BUS_FMT_YUV16_1X48,
2517 * - MEDIA_BUS_FMT_RGB161616_1X48,
2518 * - MEDIA_BUS_FMT_UYVY12_1X24,
2519 * - MEDIA_BUS_FMT_YUV12_1X36,
2520 * - MEDIA_BUS_FMT_RGB121212_1X36,
2521 * - MEDIA_BUS_FMT_UYVY10_1X20,
2522 * - MEDIA_BUS_FMT_YUV10_1X30,
2523 * - MEDIA_BUS_FMT_RGB101010_1X30,
2524 * - MEDIA_BUS_FMT_UYVY8_1X16,
2525 * - MEDIA_BUS_FMT_YUV8_1X24,
2526 * - MEDIA_BUS_FMT_RGB888_1X24,
2527 */
2528
2529 /* Can return a maximum of 11 possible output formats for a mode/connector */
2530 #define MAX_OUTPUT_SEL_FORMATS 11
2531
dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)2532 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2533 struct drm_bridge_state *bridge_state,
2534 struct drm_crtc_state *crtc_state,
2535 struct drm_connector_state *conn_state,
2536 unsigned int *num_output_fmts)
2537 {
2538 struct drm_connector *conn = conn_state->connector;
2539 struct drm_display_info *info = &conn->display_info;
2540 struct drm_display_mode *mode = &crtc_state->mode;
2541 u8 max_bpc = conn_state->max_requested_bpc;
2542 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2543 (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
2544 u32 *output_fmts;
2545 unsigned int i = 0;
2546
2547 *num_output_fmts = 0;
2548
2549 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
2550 GFP_KERNEL);
2551 if (!output_fmts)
2552 return NULL;
2553
2554 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2555 if (list_is_singular(&bridge->encoder->bridge_chain) ||
2556 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2557 *num_output_fmts = 1;
2558 output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2559
2560 return output_fmts;
2561 }
2562
2563 /*
2564 * If the current mode enforces 4:2:0, force the output but format
2565 * to 4:2:0 and do not add the YUV422/444/RGB formats
2566 */
2567 if (conn->ycbcr_420_allowed &&
2568 (drm_mode_is_420_only(info, mode) ||
2569 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
2570
2571 /* Order bus formats from 16bit to 8bit if supported */
2572 if (max_bpc >= 16 && info->bpc == 16 &&
2573 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2574 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
2575
2576 if (max_bpc >= 12 && info->bpc >= 12 &&
2577 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2578 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
2579
2580 if (max_bpc >= 10 && info->bpc >= 10 &&
2581 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2582 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
2583
2584 /* Default 8bit fallback */
2585 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2586
2587 *num_output_fmts = i;
2588
2589 return output_fmts;
2590 }
2591
2592 /*
2593 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2594 * if supported. In any case the default RGB888 format is added
2595 */
2596
2597 /* Default 8bit RGB fallback */
2598 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2599
2600 if (max_bpc >= 16 && info->bpc == 16) {
2601 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2602 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2603
2604 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2605 }
2606
2607 if (max_bpc >= 12 && info->bpc >= 12) {
2608 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2609 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2610
2611 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2612 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2613
2614 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2615 }
2616
2617 if (max_bpc >= 10 && info->bpc >= 10) {
2618 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2619 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2620
2621 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2622 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2623
2624 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2625 }
2626
2627 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2628 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2629
2630 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2631 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2632
2633 *num_output_fmts = i;
2634
2635 return output_fmts;
2636 }
2637
2638 /*
2639 * Possible input formats :
2640 * - MEDIA_BUS_FMT_RGB888_1X24
2641 * - MEDIA_BUS_FMT_YUV8_1X24
2642 * - MEDIA_BUS_FMT_UYVY8_1X16
2643 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2644 * - MEDIA_BUS_FMT_RGB101010_1X30
2645 * - MEDIA_BUS_FMT_YUV10_1X30
2646 * - MEDIA_BUS_FMT_UYVY10_1X20
2647 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2648 * - MEDIA_BUS_FMT_RGB121212_1X36
2649 * - MEDIA_BUS_FMT_YUV12_1X36
2650 * - MEDIA_BUS_FMT_UYVY12_1X24
2651 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2652 * - MEDIA_BUS_FMT_RGB161616_1X48
2653 * - MEDIA_BUS_FMT_YUV16_1X48
2654 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2655 */
2656
2657 /* Can return a maximum of 3 possible input formats for an output format */
2658 #define MAX_INPUT_SEL_FORMATS 3
2659
dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)2660 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2661 struct drm_bridge_state *bridge_state,
2662 struct drm_crtc_state *crtc_state,
2663 struct drm_connector_state *conn_state,
2664 u32 output_fmt,
2665 unsigned int *num_input_fmts)
2666 {
2667 u32 *input_fmts;
2668 unsigned int i = 0;
2669
2670 *num_input_fmts = 0;
2671
2672 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
2673 GFP_KERNEL);
2674 if (!input_fmts)
2675 return NULL;
2676
2677 switch (output_fmt) {
2678 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2679 case MEDIA_BUS_FMT_FIXED:
2680 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2681 break;
2682 /* 8bit */
2683 case MEDIA_BUS_FMT_RGB888_1X24:
2684 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2685 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2686 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2687 break;
2688 case MEDIA_BUS_FMT_YUV8_1X24:
2689 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2690 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2691 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2692 break;
2693 case MEDIA_BUS_FMT_UYVY8_1X16:
2694 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2695 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2696 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2697 break;
2698
2699 /* 10bit */
2700 case MEDIA_BUS_FMT_RGB101010_1X30:
2701 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2702 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2703 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2704 break;
2705 case MEDIA_BUS_FMT_YUV10_1X30:
2706 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2707 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2708 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2709 break;
2710 case MEDIA_BUS_FMT_UYVY10_1X20:
2711 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2712 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2713 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2714 break;
2715
2716 /* 12bit */
2717 case MEDIA_BUS_FMT_RGB121212_1X36:
2718 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2719 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2720 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2721 break;
2722 case MEDIA_BUS_FMT_YUV12_1X36:
2723 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2724 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2725 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2726 break;
2727 case MEDIA_BUS_FMT_UYVY12_1X24:
2728 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2729 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2730 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2731 break;
2732
2733 /* 16bit */
2734 case MEDIA_BUS_FMT_RGB161616_1X48:
2735 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2736 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2737 break;
2738 case MEDIA_BUS_FMT_YUV16_1X48:
2739 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2740 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2741 break;
2742
2743 /*YUV 4:2:0 */
2744 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2745 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2746 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
2747 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
2748 input_fmts[i++] = output_fmt;
2749 break;
2750 }
2751
2752 *num_input_fmts = i;
2753
2754 if (*num_input_fmts == 0) {
2755 kfree(input_fmts);
2756 input_fmts = NULL;
2757 }
2758
2759 return input_fmts;
2760 }
2761
dw_hdmi_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)2762 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2763 struct drm_bridge_state *bridge_state,
2764 struct drm_crtc_state *crtc_state,
2765 struct drm_connector_state *conn_state)
2766 {
2767 struct dw_hdmi *hdmi = bridge->driver_private;
2768
2769 hdmi->hdmi_data.enc_out_bus_format =
2770 bridge_state->output_bus_cfg.format;
2771
2772 hdmi->hdmi_data.enc_in_bus_format =
2773 bridge_state->input_bus_cfg.format;
2774
2775 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2776 bridge_state->input_bus_cfg.format,
2777 bridge_state->output_bus_cfg.format);
2778
2779 return 0;
2780 }
2781
dw_hdmi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)2782 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2783 enum drm_bridge_attach_flags flags)
2784 {
2785 struct dw_hdmi *hdmi = bridge->driver_private;
2786
2787 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
2788 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
2789 bridge, flags);
2790
2791 return dw_hdmi_connector_create(hdmi);
2792 }
2793
dw_hdmi_bridge_detach(struct drm_bridge * bridge)2794 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2795 {
2796 struct dw_hdmi *hdmi = bridge->driver_private;
2797
2798 mutex_lock(&hdmi->cec_notifier_mutex);
2799 cec_notifier_conn_unregister(hdmi->cec_notifier);
2800 hdmi->cec_notifier = NULL;
2801 mutex_unlock(&hdmi->cec_notifier_mutex);
2802 }
2803
2804 static enum drm_mode_status
dw_hdmi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)2805 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2806 const struct drm_display_info *info,
2807 const struct drm_display_mode *mode)
2808 {
2809 struct dw_hdmi *hdmi = bridge->driver_private;
2810 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2811 enum drm_mode_status mode_status = MODE_OK;
2812
2813 /* We don't support double-clocked modes */
2814 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2815 return MODE_BAD;
2816
2817 if (pdata->mode_valid)
2818 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2819 mode);
2820
2821 return mode_status;
2822 }
2823
dw_hdmi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)2824 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2825 const struct drm_display_mode *orig_mode,
2826 const struct drm_display_mode *mode)
2827 {
2828 struct dw_hdmi *hdmi = bridge->driver_private;
2829
2830 mutex_lock(&hdmi->mutex);
2831
2832 /* Store the display mode for plugin/DKMS poweron events */
2833 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2834
2835 mutex_unlock(&hdmi->mutex);
2836 }
2837
dw_hdmi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2838 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
2839 struct drm_bridge_state *old_state)
2840 {
2841 struct dw_hdmi *hdmi = bridge->driver_private;
2842
2843 mutex_lock(&hdmi->mutex);
2844 hdmi->disabled = true;
2845 hdmi->curr_conn = NULL;
2846 dw_hdmi_update_power(hdmi);
2847 dw_hdmi_update_phy_mask(hdmi);
2848 mutex_unlock(&hdmi->mutex);
2849 }
2850
dw_hdmi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2851 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
2852 struct drm_bridge_state *old_state)
2853 {
2854 struct dw_hdmi *hdmi = bridge->driver_private;
2855 struct drm_atomic_state *state = old_state->base.state;
2856 struct drm_connector *connector;
2857
2858 connector = drm_atomic_get_new_connector_for_encoder(state,
2859 bridge->encoder);
2860
2861 mutex_lock(&hdmi->mutex);
2862 hdmi->disabled = false;
2863 hdmi->curr_conn = connector;
2864 dw_hdmi_update_power(hdmi);
2865 dw_hdmi_update_phy_mask(hdmi);
2866 mutex_unlock(&hdmi->mutex);
2867 }
2868
dw_hdmi_bridge_detect(struct drm_bridge * bridge)2869 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
2870 {
2871 struct dw_hdmi *hdmi = bridge->driver_private;
2872
2873 return dw_hdmi_detect(hdmi);
2874 }
2875
dw_hdmi_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)2876 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
2877 struct drm_connector *connector)
2878 {
2879 struct dw_hdmi *hdmi = bridge->driver_private;
2880
2881 return dw_hdmi_get_edid(hdmi, connector);
2882 }
2883
2884 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2885 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2886 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2887 .atomic_reset = drm_atomic_helper_bridge_reset,
2888 .attach = dw_hdmi_bridge_attach,
2889 .detach = dw_hdmi_bridge_detach,
2890 .atomic_check = dw_hdmi_bridge_atomic_check,
2891 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
2892 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
2893 .atomic_enable = dw_hdmi_bridge_atomic_enable,
2894 .atomic_disable = dw_hdmi_bridge_atomic_disable,
2895 .mode_set = dw_hdmi_bridge_mode_set,
2896 .mode_valid = dw_hdmi_bridge_mode_valid,
2897 .detect = dw_hdmi_bridge_detect,
2898 .get_edid = dw_hdmi_bridge_get_edid,
2899 };
2900
2901 /* -----------------------------------------------------------------------------
2902 * IRQ Handling
2903 */
2904
dw_hdmi_i2c_irq(struct dw_hdmi * hdmi)2905 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2906 {
2907 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2908 unsigned int stat;
2909
2910 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2911 if (!stat)
2912 return IRQ_NONE;
2913
2914 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2915
2916 i2c->stat = stat;
2917
2918 complete(&i2c->cmp);
2919
2920 return IRQ_HANDLED;
2921 }
2922
dw_hdmi_hardirq(int irq,void * dev_id)2923 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2924 {
2925 struct dw_hdmi *hdmi = dev_id;
2926 u8 intr_stat;
2927 irqreturn_t ret = IRQ_NONE;
2928
2929 if (hdmi->i2c)
2930 ret = dw_hdmi_i2c_irq(hdmi);
2931
2932 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2933 if (intr_stat) {
2934 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2935 return IRQ_WAKE_THREAD;
2936 }
2937
2938 return ret;
2939 }
2940
dw_hdmi_setup_rx_sense(struct dw_hdmi * hdmi,bool hpd,bool rx_sense)2941 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2942 {
2943 mutex_lock(&hdmi->mutex);
2944
2945 if (!hdmi->force) {
2946 /*
2947 * If the RX sense status indicates we're disconnected,
2948 * clear the software rxsense status.
2949 */
2950 if (!rx_sense)
2951 hdmi->rxsense = false;
2952
2953 /*
2954 * Only set the software rxsense status when both
2955 * rxsense and hpd indicates we're connected.
2956 * This avoids what seems to be bad behaviour in
2957 * at least iMX6S versions of the phy.
2958 */
2959 if (hpd)
2960 hdmi->rxsense = true;
2961
2962 dw_hdmi_update_power(hdmi);
2963 dw_hdmi_update_phy_mask(hdmi);
2964 }
2965 mutex_unlock(&hdmi->mutex);
2966 }
2967 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2968
dw_hdmi_irq(int irq,void * dev_id)2969 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2970 {
2971 struct dw_hdmi *hdmi = dev_id;
2972 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2973 enum drm_connector_status status = connector_status_unknown;
2974
2975 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2976 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2977 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2978
2979 phy_pol_mask = 0;
2980 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2981 phy_pol_mask |= HDMI_PHY_HPD;
2982 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2983 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2984 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2985 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2986 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2987 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2988 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2989 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2990
2991 if (phy_pol_mask)
2992 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2993
2994 /*
2995 * RX sense tells us whether the TDMS transmitters are detecting
2996 * load - in other words, there's something listening on the
2997 * other end of the link. Use this to decide whether we should
2998 * power on the phy as HPD may be toggled by the sink to merely
2999 * ask the source to re-read the EDID.
3000 */
3001 if (intr_stat &
3002 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
3003 dw_hdmi_setup_rx_sense(hdmi,
3004 phy_stat & HDMI_PHY_HPD,
3005 phy_stat & HDMI_PHY_RX_SENSE);
3006
3007 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
3008 mutex_lock(&hdmi->cec_notifier_mutex);
3009 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3010 mutex_unlock(&hdmi->cec_notifier_mutex);
3011 }
3012
3013 if (phy_stat & HDMI_PHY_HPD)
3014 status = connector_status_connected;
3015
3016 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE)))
3017 status = connector_status_disconnected;
3018 }
3019
3020 if (status != connector_status_unknown) {
3021 dev_dbg(hdmi->dev, "EVENT=%s\n",
3022 status == connector_status_connected ?
3023 "plugin" : "plugout");
3024
3025 if (hdmi->bridge.dev) {
3026 drm_helper_hpd_irq_event(hdmi->bridge.dev);
3027 drm_bridge_hpd_notify(&hdmi->bridge, status);
3028 }
3029 }
3030
3031 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3032 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3033 HDMI_IH_MUTE_PHY_STAT0);
3034
3035 return IRQ_HANDLED;
3036 }
3037
3038 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
3039 {
3040 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
3041 .name = "DWC HDMI TX PHY",
3042 .gen = 1,
3043 }, {
3044 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
3045 .name = "DWC MHL PHY + HEAC PHY",
3046 .gen = 2,
3047 .has_svsret = true,
3048 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3049 }, {
3050 .type = DW_HDMI_PHY_DWC_MHL_PHY,
3051 .name = "DWC MHL PHY",
3052 .gen = 2,
3053 .has_svsret = true,
3054 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3055 }, {
3056 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
3057 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3058 .gen = 2,
3059 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3060 }, {
3061 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
3062 .name = "DWC HDMI 3D TX PHY",
3063 .gen = 2,
3064 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3065 }, {
3066 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
3067 .name = "DWC HDMI 2.0 TX PHY",
3068 .gen = 2,
3069 .has_svsret = true,
3070 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3071 }, {
3072 .type = DW_HDMI_PHY_VENDOR_PHY,
3073 .name = "Vendor PHY",
3074 }
3075 };
3076
dw_hdmi_detect_phy(struct dw_hdmi * hdmi)3077 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3078 {
3079 unsigned int i;
3080 u8 phy_type;
3081
3082 phy_type = hdmi->plat_data->phy_force_vendor ?
3083 DW_HDMI_PHY_VENDOR_PHY :
3084 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3085
3086 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3087 /* Vendor PHYs require support from the glue layer. */
3088 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3089 dev_err(hdmi->dev,
3090 "Vendor HDMI PHY not supported by glue layer\n");
3091 return -ENODEV;
3092 }
3093
3094 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3095 hdmi->phy.data = hdmi->plat_data->phy_data;
3096 hdmi->phy.name = hdmi->plat_data->phy_name;
3097 return 0;
3098 }
3099
3100 /* Synopsys PHYs are handled internally. */
3101 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3102 if (dw_hdmi_phys[i].type == phy_type) {
3103 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3104 hdmi->phy.name = dw_hdmi_phys[i].name;
3105 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3106
3107 if (!dw_hdmi_phys[i].configure &&
3108 !hdmi->plat_data->configure_phy) {
3109 dev_err(hdmi->dev, "%s requires platform support\n",
3110 hdmi->phy.name);
3111 return -ENODEV;
3112 }
3113
3114 return 0;
3115 }
3116 }
3117
3118 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3119 return -ENODEV;
3120 }
3121
dw_hdmi_cec_enable(struct dw_hdmi * hdmi)3122 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3123 {
3124 mutex_lock(&hdmi->mutex);
3125 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3126 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3127 mutex_unlock(&hdmi->mutex);
3128 }
3129
dw_hdmi_cec_disable(struct dw_hdmi * hdmi)3130 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3131 {
3132 mutex_lock(&hdmi->mutex);
3133 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3134 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3135 mutex_unlock(&hdmi->mutex);
3136 }
3137
3138 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3139 .write = hdmi_writeb,
3140 .read = hdmi_readb,
3141 .enable = dw_hdmi_cec_enable,
3142 .disable = dw_hdmi_cec_disable,
3143 };
3144
3145 static const struct regmap_config hdmi_regmap_8bit_config = {
3146 .reg_bits = 32,
3147 .val_bits = 8,
3148 .reg_stride = 1,
3149 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
3150 };
3151
3152 static const struct regmap_config hdmi_regmap_32bit_config = {
3153 .reg_bits = 32,
3154 .val_bits = 32,
3155 .reg_stride = 4,
3156 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
3157 };
3158
dw_hdmi_init_hw(struct dw_hdmi * hdmi)3159 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3160 {
3161 initialize_hdmi_ih_mutes(hdmi);
3162
3163 /*
3164 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3165 * Even if we are using a separate i2c adapter doing this doesn't
3166 * hurt.
3167 */
3168 dw_hdmi_i2c_init(hdmi);
3169
3170 if (hdmi->phy.ops->setup_hpd)
3171 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3172 }
3173
3174 /* -----------------------------------------------------------------------------
3175 * Probe/remove API, used from platforms based on the DRM bridge API.
3176 */
3177
dw_hdmi_parse_dt(struct dw_hdmi * hdmi)3178 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi)
3179 {
3180 struct device_node *endpoint;
3181 struct device_node *remote;
3182
3183 if (!hdmi->plat_data->output_port)
3184 return 0;
3185
3186 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node,
3187 hdmi->plat_data->output_port,
3188 -1);
3189 if (!endpoint) {
3190 /*
3191 * On platforms whose bindings don't make the output port
3192 * mandatory (such as Rockchip) the plat_data->output_port
3193 * field isn't set, so it's safe to make this a fatal error.
3194 */
3195 dev_err(hdmi->dev, "Missing endpoint in port@%u\n",
3196 hdmi->plat_data->output_port);
3197 return -ENODEV;
3198 }
3199
3200 remote = of_graph_get_remote_port_parent(endpoint);
3201 of_node_put(endpoint);
3202 if (!remote) {
3203 dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n",
3204 hdmi->plat_data->output_port);
3205 return -ENODEV;
3206 }
3207
3208 if (!of_device_is_available(remote)) {
3209 dev_err(hdmi->dev, "port@%u remote device is disabled\n",
3210 hdmi->plat_data->output_port);
3211 of_node_put(remote);
3212 return -ENODEV;
3213 }
3214
3215 hdmi->next_bridge = of_drm_find_bridge(remote);
3216 of_node_put(remote);
3217 if (!hdmi->next_bridge)
3218 return -EPROBE_DEFER;
3219
3220 return 0;
3221 }
3222
dw_hdmi_probe(struct platform_device * pdev,const struct dw_hdmi_plat_data * plat_data)3223 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3224 const struct dw_hdmi_plat_data *plat_data)
3225 {
3226 struct device *dev = &pdev->dev;
3227 struct device_node *np = dev->of_node;
3228 struct platform_device_info pdevinfo;
3229 struct device_node *ddc_node;
3230 struct dw_hdmi_cec_data cec;
3231 struct dw_hdmi *hdmi;
3232 struct resource *iores = NULL;
3233 int irq;
3234 int ret;
3235 u32 val = 1;
3236 u8 prod_id0;
3237 u8 prod_id1;
3238 u8 config0;
3239 u8 config3;
3240
3241 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3242 if (!hdmi)
3243 return ERR_PTR(-ENOMEM);
3244
3245 hdmi->plat_data = plat_data;
3246 hdmi->dev = dev;
3247 hdmi->sample_rate = 48000;
3248 hdmi->disabled = true;
3249 hdmi->rxsense = true;
3250 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3251 hdmi->mc_clkdis = 0x7f;
3252 hdmi->last_connector_result = connector_status_disconnected;
3253
3254 mutex_init(&hdmi->mutex);
3255 mutex_init(&hdmi->audio_mutex);
3256 mutex_init(&hdmi->cec_notifier_mutex);
3257 spin_lock_init(&hdmi->audio_lock);
3258
3259 ret = dw_hdmi_parse_dt(hdmi);
3260 if (ret < 0)
3261 return ERR_PTR(ret);
3262
3263 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3264 if (ddc_node) {
3265 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3266 of_node_put(ddc_node);
3267 if (!hdmi->ddc) {
3268 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3269 return ERR_PTR(-EPROBE_DEFER);
3270 }
3271
3272 } else {
3273 dev_dbg(hdmi->dev, "no ddc property found\n");
3274 }
3275
3276 if (!plat_data->regm) {
3277 const struct regmap_config *reg_config;
3278
3279 of_property_read_u32(np, "reg-io-width", &val);
3280 switch (val) {
3281 case 4:
3282 reg_config = &hdmi_regmap_32bit_config;
3283 hdmi->reg_shift = 2;
3284 break;
3285 case 1:
3286 reg_config = &hdmi_regmap_8bit_config;
3287 break;
3288 default:
3289 dev_err(dev, "reg-io-width must be 1 or 4\n");
3290 return ERR_PTR(-EINVAL);
3291 }
3292
3293 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3294 hdmi->regs = devm_ioremap_resource(dev, iores);
3295 if (IS_ERR(hdmi->regs)) {
3296 ret = PTR_ERR(hdmi->regs);
3297 goto err_res;
3298 }
3299
3300 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3301 if (IS_ERR(hdmi->regm)) {
3302 dev_err(dev, "Failed to configure regmap\n");
3303 ret = PTR_ERR(hdmi->regm);
3304 goto err_res;
3305 }
3306 } else {
3307 hdmi->regm = plat_data->regm;
3308 }
3309
3310 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3311 if (IS_ERR(hdmi->isfr_clk)) {
3312 ret = PTR_ERR(hdmi->isfr_clk);
3313 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3314 goto err_res;
3315 }
3316
3317 ret = clk_prepare_enable(hdmi->isfr_clk);
3318 if (ret) {
3319 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3320 goto err_res;
3321 }
3322
3323 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3324 if (IS_ERR(hdmi->iahb_clk)) {
3325 ret = PTR_ERR(hdmi->iahb_clk);
3326 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3327 goto err_isfr;
3328 }
3329
3330 ret = clk_prepare_enable(hdmi->iahb_clk);
3331 if (ret) {
3332 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3333 goto err_isfr;
3334 }
3335
3336 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3337 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3338 hdmi->cec_clk = NULL;
3339 } else if (IS_ERR(hdmi->cec_clk)) {
3340 ret = PTR_ERR(hdmi->cec_clk);
3341 if (ret != -EPROBE_DEFER)
3342 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3343 ret);
3344
3345 hdmi->cec_clk = NULL;
3346 goto err_iahb;
3347 } else {
3348 ret = clk_prepare_enable(hdmi->cec_clk);
3349 if (ret) {
3350 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3351 ret);
3352 goto err_iahb;
3353 }
3354 }
3355
3356 /* Product and revision IDs */
3357 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3358 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3359 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3360 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3361
3362 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
3363 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
3364 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3365 hdmi->version, prod_id0, prod_id1);
3366 ret = -ENODEV;
3367 goto err_iahb;
3368 }
3369
3370 ret = dw_hdmi_detect_phy(hdmi);
3371 if (ret < 0)
3372 goto err_iahb;
3373
3374 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3375 hdmi->version >> 12, hdmi->version & 0xfff,
3376 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
3377 hdmi->phy.name);
3378
3379 dw_hdmi_init_hw(hdmi);
3380
3381 irq = platform_get_irq(pdev, 0);
3382 if (irq < 0) {
3383 ret = irq;
3384 goto err_iahb;
3385 }
3386
3387 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3388 dw_hdmi_irq, IRQF_SHARED,
3389 dev_name(dev), hdmi);
3390 if (ret)
3391 goto err_iahb;
3392
3393 /*
3394 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3395 * N and cts values before enabling phy
3396 */
3397 hdmi_init_clk_regenerator(hdmi);
3398
3399 /* If DDC bus is not specified, try to register HDMI I2C bus */
3400 if (!hdmi->ddc) {
3401 /* Look for (optional) stuff related to unwedging */
3402 hdmi->pinctrl = devm_pinctrl_get(dev);
3403 if (!IS_ERR(hdmi->pinctrl)) {
3404 hdmi->unwedge_state =
3405 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3406 hdmi->default_state =
3407 pinctrl_lookup_state(hdmi->pinctrl, "default");
3408
3409 if (IS_ERR(hdmi->default_state) ||
3410 IS_ERR(hdmi->unwedge_state)) {
3411 if (!IS_ERR(hdmi->unwedge_state))
3412 dev_warn(dev,
3413 "Unwedge requires default pinctrl\n");
3414 hdmi->default_state = NULL;
3415 hdmi->unwedge_state = NULL;
3416 }
3417 }
3418
3419 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3420 if (IS_ERR(hdmi->ddc))
3421 hdmi->ddc = NULL;
3422 }
3423
3424 hdmi->bridge.driver_private = hdmi;
3425 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3426 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3427 | DRM_BRIDGE_OP_HPD;
3428 #ifdef CONFIG_OF
3429 hdmi->bridge.of_node = pdev->dev.of_node;
3430 #endif
3431
3432 memset(&pdevinfo, 0, sizeof(pdevinfo));
3433 pdevinfo.parent = dev;
3434 pdevinfo.id = PLATFORM_DEVID_AUTO;
3435
3436 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3437 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3438
3439 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
3440 struct dw_hdmi_audio_data audio;
3441
3442 audio.phys = iores->start;
3443 audio.base = hdmi->regs;
3444 audio.irq = irq;
3445 audio.hdmi = hdmi;
3446 audio.get_eld = hdmi_audio_get_eld;
3447 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3448 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3449
3450 pdevinfo.name = "dw-hdmi-ahb-audio";
3451 pdevinfo.data = &audio;
3452 pdevinfo.size_data = sizeof(audio);
3453 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3454 hdmi->audio = platform_device_register_full(&pdevinfo);
3455 } else if (config0 & HDMI_CONFIG0_I2S) {
3456 struct dw_hdmi_i2s_audio_data audio;
3457
3458 audio.hdmi = hdmi;
3459 audio.get_eld = hdmi_audio_get_eld;
3460 audio.write = hdmi_writeb;
3461 audio.read = hdmi_readb;
3462 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3463 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3464
3465 pdevinfo.name = "dw-hdmi-i2s-audio";
3466 pdevinfo.data = &audio;
3467 pdevinfo.size_data = sizeof(audio);
3468 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3469 hdmi->audio = platform_device_register_full(&pdevinfo);
3470 }
3471
3472 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
3473 cec.hdmi = hdmi;
3474 cec.ops = &dw_hdmi_cec_ops;
3475 cec.irq = irq;
3476
3477 pdevinfo.name = "dw-hdmi-cec";
3478 pdevinfo.data = &cec;
3479 pdevinfo.size_data = sizeof(cec);
3480 pdevinfo.dma_mask = 0;
3481
3482 hdmi->cec = platform_device_register_full(&pdevinfo);
3483 }
3484
3485 drm_bridge_add(&hdmi->bridge);
3486
3487 return hdmi;
3488
3489 err_iahb:
3490 clk_disable_unprepare(hdmi->iahb_clk);
3491 clk_disable_unprepare(hdmi->cec_clk);
3492 err_isfr:
3493 clk_disable_unprepare(hdmi->isfr_clk);
3494 err_res:
3495 i2c_put_adapter(hdmi->ddc);
3496
3497 return ERR_PTR(ret);
3498 }
3499 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3500
dw_hdmi_remove(struct dw_hdmi * hdmi)3501 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3502 {
3503 drm_bridge_remove(&hdmi->bridge);
3504
3505 if (hdmi->audio && !IS_ERR(hdmi->audio))
3506 platform_device_unregister(hdmi->audio);
3507 if (!IS_ERR(hdmi->cec))
3508 platform_device_unregister(hdmi->cec);
3509
3510 /* Disable all interrupts */
3511 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3512
3513 clk_disable_unprepare(hdmi->iahb_clk);
3514 clk_disable_unprepare(hdmi->isfr_clk);
3515 clk_disable_unprepare(hdmi->cec_clk);
3516
3517 if (hdmi->i2c)
3518 i2c_del_adapter(&hdmi->i2c->adap);
3519 else
3520 i2c_put_adapter(hdmi->ddc);
3521 }
3522 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3523
3524 /* -----------------------------------------------------------------------------
3525 * Bind/unbind API, used from platforms based on the component framework.
3526 */
dw_hdmi_bind(struct platform_device * pdev,struct drm_encoder * encoder,const struct dw_hdmi_plat_data * plat_data)3527 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3528 struct drm_encoder *encoder,
3529 const struct dw_hdmi_plat_data *plat_data)
3530 {
3531 struct dw_hdmi *hdmi;
3532 int ret;
3533
3534 hdmi = dw_hdmi_probe(pdev, plat_data);
3535 if (IS_ERR(hdmi))
3536 return hdmi;
3537
3538 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3539 if (ret) {
3540 dw_hdmi_remove(hdmi);
3541 return ERR_PTR(ret);
3542 }
3543
3544 return hdmi;
3545 }
3546 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3547
dw_hdmi_unbind(struct dw_hdmi * hdmi)3548 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3549 {
3550 dw_hdmi_remove(hdmi);
3551 }
3552 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3553
dw_hdmi_resume(struct dw_hdmi * hdmi)3554 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3555 {
3556 dw_hdmi_init_hw(hdmi);
3557 }
3558 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3559
3560 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3561 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3562 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3563 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3564 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3565 MODULE_LICENSE("GPL");
3566 MODULE_ALIAS("platform:dw-hdmi");
3567