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Searched refs:hw_mode (Results 1 – 25 of 27) sorted by relevance

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/drivers/spi/
Dspi-fsl-spi.c97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
243 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 in fsl_spi_setup_transfer()
246 cs->hw_mode |= SPMODE_LEN(bits_per_word); in fsl_spi_setup_transfer()
249 cs->hw_mode |= SPMODE_DIV16; in fsl_spi_setup_transfer()
262 cs->hw_mode |= SPMODE_PM(pm); in fsl_spi_setup_transfer()
440 u32 hw_mode; in fsl_spi_setup() local
457 hw_mode = cs->hw_mode; /* Save original settings */ in fsl_spi_setup()
458 cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode); in fsl_spi_setup()
[all …]
Dspi-fsl-espi.c113 u32 hw_mode; member
330 u32 hw_mode_old = cs->hw_mode; in fsl_espi_setup_transfer()
333 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); in fsl_espi_setup_transfer()
335 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); in fsl_espi_setup_transfer()
340 cs->hw_mode |= CSMODE_DIV16; in fsl_espi_setup_transfer()
344 cs->hw_mode |= CSMODE_PM(pm); in fsl_espi_setup_transfer()
347 if (cs->hw_mode != hw_mode_old) in fsl_espi_setup_transfer()
349 cs->hw_mode); in fsl_espi_setup_transfer()
495 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select)); in fsl_espi_setup()
497 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH in fsl_espi_setup()
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Dspi-sprd.c158 u32 hw_mode; member
419 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) in sprd_spi_txrx_bufs()
430 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) in sprd_spi_txrx_bufs()
596 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) in sprd_spi_dma_txrx_bufs()
605 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) in sprd_spi_dma_txrx_bufs()
677 val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX; in sprd_spi_init_hw()
678 val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0; in sprd_spi_init_hw()
700 if (ss->hw_mode & SPI_3WIRE) in sprd_spi_init_hw()
705 if (ss->hw_mode & SPI_TX_DUAL) in sprd_spi_init_hw()
727 ss->hw_mode = sdev->mode; in sprd_spi_setup_transfer()
Dspi-fsl-lib.h79 u32 hw_mode; /* Holds HW mode register settings */ member
/drivers/crypto/ccree/
Dcc_hash.c70 int hw_mode; member
96 int hw_mode; member
143 if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC && in cc_init_req()
144 ctx->hw_mode != DRV_CIPHER_CMAC) { in cc_init_req()
195 if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { in cc_map_req()
351 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_fin_result()
374 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
384 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
393 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
468 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_hash_digest()
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/drivers/usb/dwc3/
Dcore.c51 unsigned int hw_mode; in dwc3_get_dr_mode() local
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_get_dr_mode()
59 switch (hw_mode) { in dwc3_get_dr_mode()
597 unsigned int hw_mode; in dwc3_phy_setup() local
600 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_phy_setup()
624 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) in dwc3_phy_setup()
714 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) in dwc3_phy_setup()
987 unsigned int hw_mode; in dwc3_core_init() local
991 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_core_init()
1038 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && in dwc3_core_init()
/drivers/net/ethernet/qlogic/qed/
Dqed_dev.c2104 p_hwfn->hw_info.hw_mode); in qed_qm_reconf()
2476 int hw_mode = 0; in qed_calc_hw_mode() local
2479 hw_mode |= 1 << MODE_BB; in qed_calc_hw_mode()
2481 hw_mode |= 1 << MODE_K2; in qed_calc_hw_mode()
2490 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; in qed_calc_hw_mode()
2493 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; in qed_calc_hw_mode()
2496 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; in qed_calc_hw_mode()
2505 hw_mode |= 1 << MODE_MF_SD; in qed_calc_hw_mode()
2507 hw_mode |= 1 << MODE_MF_SI; in qed_calc_hw_mode()
2509 hw_mode |= 1 << MODE_ASIC; in qed_calc_hw_mode()
[all …]
Dqed.h323 u32 hw_mode; member
Dqed_mcp.c1767 p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); in qed_mcp_update_stag()
/drivers/crypto/stm32/
Dstm32-cryp.c531 u32 cfg, hw_mode; in stm32_cryp_hw_init() local
559 hw_mode = stm32_cryp_get_hw_mode(cryp); in stm32_cryp_hw_init()
560 if (hw_mode == CR_AES_UNKNOWN) in stm32_cryp_hw_init()
565 ((hw_mode == CR_AES_ECB) || (hw_mode == CR_AES_CBC))) { in stm32_cryp_hw_init()
576 cfg |= hw_mode; in stm32_cryp_hw_init()
584 switch (hw_mode) { in stm32_cryp_hw_init()
588 if (hw_mode == CR_AES_CCM) in stm32_cryp_hw_init()
/drivers/regulator/
Dmt6360-regulator.c308 static unsigned int mt6360_regulator_of_map_mode(unsigned int hw_mode) in mt6360_regulator_of_map_mode() argument
310 switch (hw_mode) { in mt6360_regulator_of_map_mode()
/drivers/gpu/drm/radeon/
Dr600_dpm.c167 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vblank_time()
169 radeon_crtc->hw_mode.crtc_htotal * in r600_dpm_get_vblank_time()
170 (radeon_crtc->hw_mode.crtc_vblank_end - in r600_dpm_get_vblank_time()
171 radeon_crtc->hw_mode.crtc_vdisplay + in r600_dpm_get_vblank_time()
174 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; in r600_dpm_get_vblank_time()
193 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vrefresh()
194 vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode); in r600_dpm_get_vrefresh()
Dradeon_mode.h371 struct drm_display_mode hw_mode; member
Datombios_crtc.c2088 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
Dsi.c5193 bool hw_mode = true; in si_init_uvd_internal_cg() local
5195 if (hw_mode) { in si_init_uvd_internal_cg()
/drivers/gpu/drm/amd/pm/
Damdgpu_dpm.c155 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { in amdgpu_dpm_get_vblank_time()
157 amdgpu_crtc->hw_mode.crtc_htotal * in amdgpu_dpm_get_vblank_time()
158 (amdgpu_crtc->hw_mode.crtc_vblank_end - in amdgpu_dpm_get_vblank_time()
159 amdgpu_crtc->hw_mode.crtc_vdisplay + in amdgpu_dpm_get_vblank_time()
162 vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; in amdgpu_dpm_get_vblank_time()
181 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { in amdgpu_dpm_get_vrefresh()
182 vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); in amdgpu_dpm_get_vrefresh()
/drivers/net/ethernet/ti/
Ddavinci_cpdma.c72 u32 hw_mode; member
1007 mode = desc_read(prev, hw_mode); in __cpdma_chan_submit()
1010 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ); in __cpdma_chan_submit()
1063 writel_relaxed(mode | len, &desc->hw_mode); in cpdma_chan_submit_si()
1239 status = desc_read(desc, hw_mode); in __cpdma_chan_process()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_mode.h428 struct drm_display_mode hw_mode; member
Ddce_v8_0.c2538 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v8_0_crtc_mode_set()
Ddce_v6_0.c2518 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
Ddce_v10_0.c2626 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v10_0_crtc_mode_set()
Ddce_v11_0.c2731 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v11_0_crtc_mode_set()
/drivers/net/wireless/ath/ath11k/
Dwmi.c3514 struct wmi_pdev_set_hw_mode_cmd_param *hw_mode; in ath11k_init_cmd_send() local
3524 hw_mode_len = sizeof(*hw_mode) + TLV_HDR_SIZE + in ath11k_init_cmd_send()
3577 hw_mode = (struct wmi_pdev_set_hw_mode_cmd_param *)ptr; in ath11k_init_cmd_send()
3578 hw_mode->tlv_header = FIELD_PREP(WMI_TLV_TAG, in ath11k_init_cmd_send()
3581 sizeof(*hw_mode) - TLV_HDR_SIZE); in ath11k_init_cmd_send()
3583 hw_mode->hw_mode_index = param->hw_mode_id; in ath11k_init_cmd_send()
3584 hw_mode->num_band_to_mac = param->num_band_to_mac; in ath11k_init_cmd_send()
3586 ptr += sizeof(*hw_mode); in ath11k_init_cmd_send()
/drivers/staging/rtl8723bs/include/
Drtw_mlme_ext.h393 enum hw_mode {IEEE80211G, IEEE80211A} mode; enum
/drivers/staging/r8188eu/include/
Drtw_mlme_ext.h373 enum hw_mode {IEEE80211G} mode; enum

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