1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
__dwc3_set_mode(struct work_struct * work)117 static void __dwc3_set_mode(struct work_struct *work)
118 {
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122 u32 reg;
123 u32 desired_dr_role;
124
125 mutex_lock(&dwc->mutex);
126 spin_lock_irqsave(&dwc->lock, flags);
127 desired_dr_role = dwc->desired_dr_role;
128 spin_unlock_irqrestore(&dwc->lock, flags);
129
130 pm_runtime_get_sync(dwc->dev);
131
132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
133 dwc3_otg_update(dwc, 0);
134
135 if (!desired_dr_role)
136 goto out;
137
138 if (desired_dr_role == dwc->current_dr_role)
139 goto out;
140
141 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
142 goto out;
143
144 switch (dwc->current_dr_role) {
145 case DWC3_GCTL_PRTCAP_HOST:
146 dwc3_host_exit(dwc);
147 break;
148 case DWC3_GCTL_PRTCAP_DEVICE:
149 dwc3_gadget_exit(dwc);
150 dwc3_event_buffers_cleanup(dwc);
151 break;
152 case DWC3_GCTL_PRTCAP_OTG:
153 dwc3_otg_exit(dwc);
154 spin_lock_irqsave(&dwc->lock, flags);
155 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
156 spin_unlock_irqrestore(&dwc->lock, flags);
157 dwc3_otg_update(dwc, 1);
158 break;
159 default:
160 break;
161 }
162
163 /*
164 * When current_dr_role is not set, there's no role switching.
165 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
166 */
167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
168 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
169 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
170 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
171 reg |= DWC3_GCTL_CORESOFTRESET;
172 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
173
174 /*
175 * Wait for internal clocks to synchronized. DWC_usb31 and
176 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
177 * keep it consistent across different IPs, let's wait up to
178 * 100ms before clearing GCTL.CORESOFTRESET.
179 */
180 msleep(100);
181
182 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
183 reg &= ~DWC3_GCTL_CORESOFTRESET;
184 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
185 }
186
187 spin_lock_irqsave(&dwc->lock, flags);
188
189 dwc3_set_prtcap(dwc, desired_dr_role);
190
191 spin_unlock_irqrestore(&dwc->lock, flags);
192
193 switch (desired_dr_role) {
194 case DWC3_GCTL_PRTCAP_HOST:
195 ret = dwc3_host_init(dwc);
196 if (ret) {
197 dev_err(dwc->dev, "failed to initialize host\n");
198 } else {
199 if (dwc->usb2_phy)
200 otg_set_vbus(dwc->usb2_phy->otg, true);
201 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
202 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
203 if (dwc->dis_split_quirk) {
204 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
205 reg |= DWC3_GUCTL3_SPLITDISABLE;
206 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
207 }
208 }
209 break;
210 case DWC3_GCTL_PRTCAP_DEVICE:
211 dwc3_core_soft_reset(dwc);
212
213 dwc3_event_buffers_setup(dwc);
214
215 if (dwc->usb2_phy)
216 otg_set_vbus(dwc->usb2_phy->otg, false);
217 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
218 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
219
220 ret = dwc3_gadget_init(dwc);
221 if (ret)
222 dev_err(dwc->dev, "failed to initialize peripheral\n");
223 break;
224 case DWC3_GCTL_PRTCAP_OTG:
225 dwc3_otg_init(dwc);
226 dwc3_otg_update(dwc, 0);
227 break;
228 default:
229 break;
230 }
231
232 out:
233 pm_runtime_mark_last_busy(dwc->dev);
234 pm_runtime_put_autosuspend(dwc->dev);
235 mutex_unlock(&dwc->mutex);
236 }
237
dwc3_set_mode(struct dwc3 * dwc,u32 mode)238 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
239 {
240 unsigned long flags;
241
242 if (dwc->dr_mode != USB_DR_MODE_OTG)
243 return;
244
245 spin_lock_irqsave(&dwc->lock, flags);
246 dwc->desired_dr_role = mode;
247 spin_unlock_irqrestore(&dwc->lock, flags);
248
249 queue_work(system_freezable_wq, &dwc->drd_work);
250 }
251
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)252 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
253 {
254 struct dwc3 *dwc = dep->dwc;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
258 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
259 DWC3_GDBGFIFOSPACE_TYPE(type));
260
261 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
262
263 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
264 }
265
266 /**
267 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
268 * @dwc: pointer to our context structure
269 */
dwc3_core_soft_reset(struct dwc3 * dwc)270 int dwc3_core_soft_reset(struct dwc3 *dwc)
271 {
272 u32 reg;
273 int retries = 1000;
274
275 /*
276 * We're resetting only the device side because, if we're in host mode,
277 * XHCI driver will reset the host block. If dwc3 was configured for
278 * host-only mode, then we can return early.
279 */
280 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
281 return 0;
282
283 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
284 reg |= DWC3_DCTL_CSFTRST;
285 reg &= ~DWC3_DCTL_RUN_STOP;
286 dwc3_gadget_dctl_write_safe(dwc, reg);
287
288 /*
289 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
290 * is cleared only after all the clocks are synchronized. This can
291 * take a little more than 50ms. Set the polling rate at 20ms
292 * for 10 times instead.
293 */
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 retries = 10;
296
297 do {
298 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
299 if (!(reg & DWC3_DCTL_CSFTRST))
300 goto done;
301
302 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
303 msleep(20);
304 else
305 udelay(1);
306 } while (--retries);
307
308 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
309 return -ETIMEDOUT;
310
311 done:
312 /*
313 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
314 * is cleared, we must wait at least 50ms before accessing the PHY
315 * domain (synchronization delay).
316 */
317 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
318 msleep(50);
319
320 return 0;
321 }
322
323 /*
324 * dwc3_frame_length_adjustment - Adjusts frame length if required
325 * @dwc3: Pointer to our controller context structure
326 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)327 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
328 {
329 u32 reg;
330 u32 dft;
331
332 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
333 return;
334
335 if (dwc->fladj == 0)
336 return;
337
338 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
339 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
340 if (dft != dwc->fladj) {
341 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
342 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
343 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
344 }
345 }
346
347 /**
348 * dwc3_free_one_event_buffer - Frees one event buffer
349 * @dwc: Pointer to our controller context structure
350 * @evt: Pointer to event buffer to be freed
351 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)352 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
353 struct dwc3_event_buffer *evt)
354 {
355 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
356 }
357
358 /**
359 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
360 * @dwc: Pointer to our controller context structure
361 * @length: size of the event buffer
362 *
363 * Returns a pointer to the allocated event buffer structure on success
364 * otherwise ERR_PTR(errno).
365 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)366 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
367 unsigned length)
368 {
369 struct dwc3_event_buffer *evt;
370
371 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
372 if (!evt)
373 return ERR_PTR(-ENOMEM);
374
375 evt->dwc = dwc;
376 evt->length = length;
377 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
378 if (!evt->cache)
379 return ERR_PTR(-ENOMEM);
380
381 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
382 &evt->dma, GFP_KERNEL);
383 if (!evt->buf)
384 return ERR_PTR(-ENOMEM);
385
386 return evt;
387 }
388
389 /**
390 * dwc3_free_event_buffers - frees all allocated event buffers
391 * @dwc: Pointer to our controller context structure
392 */
dwc3_free_event_buffers(struct dwc3 * dwc)393 static void dwc3_free_event_buffers(struct dwc3 *dwc)
394 {
395 struct dwc3_event_buffer *evt;
396
397 evt = dwc->ev_buf;
398 if (evt)
399 dwc3_free_one_event_buffer(dwc, evt);
400 }
401
402 /**
403 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
404 * @dwc: pointer to our controller context structure
405 * @length: size of event buffer
406 *
407 * Returns 0 on success otherwise negative errno. In the error case, dwc
408 * may contain some buffers allocated but not all which were requested.
409 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)410 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
411 {
412 struct dwc3_event_buffer *evt;
413
414 evt = dwc3_alloc_one_event_buffer(dwc, length);
415 if (IS_ERR(evt)) {
416 dev_err(dwc->dev, "can't allocate event buffer\n");
417 return PTR_ERR(evt);
418 }
419 dwc->ev_buf = evt;
420
421 return 0;
422 }
423
424 /**
425 * dwc3_event_buffers_setup - setup our allocated event buffers
426 * @dwc: pointer to our controller context structure
427 *
428 * Returns 0 on success otherwise negative errno.
429 */
dwc3_event_buffers_setup(struct dwc3 * dwc)430 int dwc3_event_buffers_setup(struct dwc3 *dwc)
431 {
432 struct dwc3_event_buffer *evt;
433
434 evt = dwc->ev_buf;
435 evt->lpos = 0;
436 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
437 lower_32_bits(evt->dma));
438 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
439 upper_32_bits(evt->dma));
440 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
441 DWC3_GEVNTSIZ_SIZE(evt->length));
442 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
443
444 return 0;
445 }
446
dwc3_event_buffers_cleanup(struct dwc3 * dwc)447 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
448 {
449 struct dwc3_event_buffer *evt;
450
451 evt = dwc->ev_buf;
452
453 evt->lpos = 0;
454
455 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
456 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
457 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
458 | DWC3_GEVNTSIZ_SIZE(0));
459 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
460 }
461
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)462 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
463 {
464 if (!dwc->has_hibernation)
465 return 0;
466
467 if (!dwc->nr_scratch)
468 return 0;
469
470 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
471 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
472 if (!dwc->scratchbuf)
473 return -ENOMEM;
474
475 return 0;
476 }
477
dwc3_setup_scratch_buffers(struct dwc3 * dwc)478 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
479 {
480 dma_addr_t scratch_addr;
481 u32 param;
482 int ret;
483
484 if (!dwc->has_hibernation)
485 return 0;
486
487 if (!dwc->nr_scratch)
488 return 0;
489
490 /* should never fall here */
491 if (!WARN_ON(dwc->scratchbuf))
492 return 0;
493
494 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
495 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
496 DMA_BIDIRECTIONAL);
497 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
498 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
499 ret = -EFAULT;
500 goto err0;
501 }
502
503 dwc->scratch_addr = scratch_addr;
504
505 param = lower_32_bits(scratch_addr);
506
507 ret = dwc3_send_gadget_generic_command(dwc,
508 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
509 if (ret < 0)
510 goto err1;
511
512 param = upper_32_bits(scratch_addr);
513
514 ret = dwc3_send_gadget_generic_command(dwc,
515 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
516 if (ret < 0)
517 goto err1;
518
519 return 0;
520
521 err1:
522 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
523 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
524
525 err0:
526 return ret;
527 }
528
dwc3_free_scratch_buffers(struct dwc3 * dwc)529 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
530 {
531 if (!dwc->has_hibernation)
532 return;
533
534 if (!dwc->nr_scratch)
535 return;
536
537 /* should never fall here */
538 if (!WARN_ON(dwc->scratchbuf))
539 return;
540
541 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
542 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
543 kfree(dwc->scratchbuf);
544 }
545
dwc3_core_num_eps(struct dwc3 * dwc)546 static void dwc3_core_num_eps(struct dwc3 *dwc)
547 {
548 struct dwc3_hwparams *parms = &dwc->hwparams;
549
550 dwc->num_eps = DWC3_NUM_EPS(parms);
551 }
552
dwc3_cache_hwparams(struct dwc3 * dwc)553 static void dwc3_cache_hwparams(struct dwc3 *dwc)
554 {
555 struct dwc3_hwparams *parms = &dwc->hwparams;
556
557 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
558 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
559 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
560 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
561 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
562 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
563 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
564 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
565 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
566
567 if (DWC3_IP_IS(DWC32))
568 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
569 }
570
dwc3_core_ulpi_init(struct dwc3 * dwc)571 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
572 {
573 int intf;
574 int ret = 0;
575
576 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
577
578 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
579 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
580 dwc->hsphy_interface &&
581 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
582 ret = dwc3_ulpi_init(dwc);
583
584 return ret;
585 }
586
587 /**
588 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
589 * @dwc: Pointer to our controller context structure
590 *
591 * Returns 0 on success. The USB PHY interfaces are configured but not
592 * initialized. The PHY interfaces and the PHYs get initialized together with
593 * the core in dwc3_core_init.
594 */
dwc3_phy_setup(struct dwc3 * dwc)595 static int dwc3_phy_setup(struct dwc3 *dwc)
596 {
597 unsigned int hw_mode;
598 u32 reg;
599
600 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
601
602 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
603
604 /*
605 * Make sure UX_EXIT_PX is cleared as that causes issues with some
606 * PHYs. Also, this bit is not supposed to be used in normal operation.
607 */
608 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
609
610 /*
611 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
612 * to '0' during coreConsultant configuration. So default value
613 * will be '0' when the core is reset. Application needs to set it
614 * to '1' after the core initialization is completed.
615 */
616 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
617 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
618
619 /*
620 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
621 * power-on reset, and it can be set after core initialization, which is
622 * after device soft-reset during initialization.
623 */
624 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
625 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
626
627 if (dwc->u2ss_inp3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
629
630 if (dwc->dis_rxdet_inp3_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
632
633 if (dwc->req_p1p2p3_quirk)
634 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
635
636 if (dwc->del_p1p2p3_quirk)
637 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
638
639 if (dwc->del_phy_power_chg_quirk)
640 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
641
642 if (dwc->lfps_filter_quirk)
643 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
644
645 if (dwc->rx_detect_poll_quirk)
646 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
647
648 if (dwc->tx_de_emphasis_quirk)
649 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
650
651 if (dwc->dis_u3_susphy_quirk)
652 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
653
654 if (dwc->dis_del_phy_power_chg_quirk)
655 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
656
657 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
658
659 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
660
661 /* Select the HS PHY interface */
662 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
663 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
664 if (dwc->hsphy_interface &&
665 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
666 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
667 break;
668 } else if (dwc->hsphy_interface &&
669 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
670 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
671 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
672 } else {
673 /* Relying on default value. */
674 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
675 break;
676 }
677 fallthrough;
678 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
679 default:
680 break;
681 }
682
683 switch (dwc->hsphy_mode) {
684 case USBPHY_INTERFACE_MODE_UTMI:
685 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
686 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
687 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
688 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
689 break;
690 case USBPHY_INTERFACE_MODE_UTMIW:
691 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
692 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
693 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
694 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
695 break;
696 default:
697 break;
698 }
699
700 /*
701 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
702 * '0' during coreConsultant configuration. So default value will
703 * be '0' when the core is reset. Application needs to set it to
704 * '1' after the core initialization is completed.
705 */
706 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
707 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
708
709 /*
710 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
711 * power-on reset, and it can be set after core initialization, which is
712 * after device soft-reset during initialization.
713 */
714 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
715 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
716
717 if (dwc->dis_u2_susphy_quirk)
718 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
719
720 if (dwc->dis_enblslpm_quirk)
721 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
722 else
723 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
724
725 if (dwc->dis_u2_freeclk_exists_quirk)
726 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
727
728 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
729
730 return 0;
731 }
732
dwc3_core_exit(struct dwc3 * dwc)733 static void dwc3_core_exit(struct dwc3 *dwc)
734 {
735 dwc3_event_buffers_cleanup(dwc);
736
737 usb_phy_set_suspend(dwc->usb2_phy, 1);
738 usb_phy_set_suspend(dwc->usb3_phy, 1);
739 phy_power_off(dwc->usb2_generic_phy);
740 phy_power_off(dwc->usb3_generic_phy);
741
742 usb_phy_shutdown(dwc->usb2_phy);
743 usb_phy_shutdown(dwc->usb3_phy);
744 phy_exit(dwc->usb2_generic_phy);
745 phy_exit(dwc->usb3_generic_phy);
746
747 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
748 reset_control_assert(dwc->reset);
749 }
750
dwc3_core_is_valid(struct dwc3 * dwc)751 static bool dwc3_core_is_valid(struct dwc3 *dwc)
752 {
753 u32 reg;
754
755 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
756 dwc->ip = DWC3_GSNPS_ID(reg);
757
758 /* This should read as U3 followed by revision number */
759 if (DWC3_IP_IS(DWC3)) {
760 dwc->revision = reg;
761 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
762 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
763 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
764 } else {
765 return false;
766 }
767
768 return true;
769 }
770
dwc3_core_setup_global_control(struct dwc3 * dwc)771 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
772 {
773 u32 hwparams4 = dwc->hwparams.hwparams4;
774 u32 reg;
775
776 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
777 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
778
779 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
780 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
781 /**
782 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
783 * issue which would cause xHCI compliance tests to fail.
784 *
785 * Because of that we cannot enable clock gating on such
786 * configurations.
787 *
788 * Refers to:
789 *
790 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
791 * SOF/ITP Mode Used
792 */
793 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
794 dwc->dr_mode == USB_DR_MODE_OTG) &&
795 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
796 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
797 else
798 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
799 break;
800 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
801 /* enable hibernation here */
802 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
803
804 /*
805 * REVISIT Enabling this bit so that host-mode hibernation
806 * will work. Device-mode hibernation is not yet implemented.
807 */
808 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
809 break;
810 default:
811 /* nothing */
812 break;
813 }
814
815 /* check if current dwc3 is on simulation board */
816 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
817 dev_info(dwc->dev, "Running with FPGA optimizations\n");
818 dwc->is_fpga = true;
819 }
820
821 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
822 "disable_scramble cannot be used on non-FPGA builds\n");
823
824 if (dwc->disable_scramble_quirk && dwc->is_fpga)
825 reg |= DWC3_GCTL_DISSCRAMBLE;
826 else
827 reg &= ~DWC3_GCTL_DISSCRAMBLE;
828
829 if (dwc->u2exit_lfps_quirk)
830 reg |= DWC3_GCTL_U2EXIT_LFPS;
831
832 /*
833 * WORKAROUND: DWC3 revisions <1.90a have a bug
834 * where the device can fail to connect at SuperSpeed
835 * and falls back to high-speed mode which causes
836 * the device to enter a Connect/Disconnect loop
837 */
838 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
839 reg |= DWC3_GCTL_U2RSTECN;
840
841 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
842 }
843
844 static int dwc3_core_get_phy(struct dwc3 *dwc);
845 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
846
847 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)848 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
849 {
850 struct device *dev = dwc->dev;
851 /* incrx_mode : for INCR burst type. */
852 bool incrx_mode;
853 /* incrx_size : for size of INCRX burst. */
854 u32 incrx_size;
855 u32 *vals;
856 u32 cfg;
857 int ntype;
858 int ret;
859 int i;
860
861 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
862
863 /*
864 * Handle property "snps,incr-burst-type-adjustment".
865 * Get the number of value from this property:
866 * result <= 0, means this property is not supported.
867 * result = 1, means INCRx burst mode supported.
868 * result > 1, means undefined length burst mode supported.
869 */
870 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
871 if (ntype <= 0)
872 return;
873
874 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
875 if (!vals) {
876 dev_err(dev, "Error to get memory\n");
877 return;
878 }
879
880 /* Get INCR burst type, and parse it */
881 ret = device_property_read_u32_array(dev,
882 "snps,incr-burst-type-adjustment", vals, ntype);
883 if (ret) {
884 kfree(vals);
885 dev_err(dev, "Error to get property\n");
886 return;
887 }
888
889 incrx_size = *vals;
890
891 if (ntype > 1) {
892 /* INCRX (undefined length) burst mode */
893 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
894 for (i = 1; i < ntype; i++) {
895 if (vals[i] > incrx_size)
896 incrx_size = vals[i];
897 }
898 } else {
899 /* INCRX burst mode */
900 incrx_mode = INCRX_BURST_MODE;
901 }
902
903 kfree(vals);
904
905 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
906 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
907 if (incrx_mode)
908 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
909 switch (incrx_size) {
910 case 256:
911 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
912 break;
913 case 128:
914 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
915 break;
916 case 64:
917 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
918 break;
919 case 32:
920 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
921 break;
922 case 16:
923 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
924 break;
925 case 8:
926 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
927 break;
928 case 4:
929 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
930 break;
931 case 1:
932 break;
933 default:
934 dev_err(dev, "Invalid property\n");
935 break;
936 }
937
938 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
939 }
940
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)941 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
942 {
943 struct device *dev = dwc->dev;
944 struct device_node *node = dev->of_node;
945 struct clk *suspend_clk;
946 u32 scale;
947 u32 reg;
948
949 if (dwc->num_clks == 0)
950 return;
951
952 /*
953 * The power down scale field specifies how many suspend_clk
954 * periods fit into a 16KHz clock period. When performing
955 * the division, round up the remainder.
956 *
957 * The power down scale value is calculated using the fastest
958 * frequency of the suspend_clk. If it isn't fixed (but within
959 * the accuracy requirement), the driver may not know the max
960 * rate of the suspend_clk, so only update the power down scale
961 * if the default is less than the calculated value from
962 * clk_get_rate() or if the default is questionably high
963 * (3x or more) to be within the requirement.
964 */
965 suspend_clk = of_clk_get_by_name(node, "suspend");
966 if (IS_ERR(suspend_clk))
967 return;
968
969 scale = DIV_ROUND_UP(clk_get_rate(suspend_clk), 16000);
970 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
971 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
972 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
973 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
974 reg |= DWC3_GCTL_PWRDNSCALE(scale);
975 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
976 }
977 }
978
979 /**
980 * dwc3_core_init - Low-level initialization of DWC3 Core
981 * @dwc: Pointer to our controller context structure
982 *
983 * Returns 0 on success otherwise negative errno.
984 */
dwc3_core_init(struct dwc3 * dwc)985 static int dwc3_core_init(struct dwc3 *dwc)
986 {
987 unsigned int hw_mode;
988 u32 reg;
989 int ret;
990
991 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
992
993 /*
994 * Write Linux Version Code to our GUID register so it's easy to figure
995 * out which kernel version a bug was found.
996 */
997 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
998
999 ret = dwc3_phy_setup(dwc);
1000 if (ret)
1001 goto err0;
1002
1003 if (!dwc->ulpi_ready) {
1004 ret = dwc3_core_ulpi_init(dwc);
1005 if (ret) {
1006 if (ret == -ETIMEDOUT) {
1007 dwc3_core_soft_reset(dwc);
1008 ret = -EPROBE_DEFER;
1009 }
1010 goto err0;
1011 }
1012 dwc->ulpi_ready = true;
1013 }
1014
1015 if (!dwc->phys_ready) {
1016 ret = dwc3_core_get_phy(dwc);
1017 if (ret)
1018 goto err0a;
1019 dwc->phys_ready = true;
1020 }
1021
1022 usb_phy_init(dwc->usb2_phy);
1023 usb_phy_init(dwc->usb3_phy);
1024 ret = phy_init(dwc->usb2_generic_phy);
1025 if (ret < 0)
1026 goto err0a;
1027
1028 ret = phy_init(dwc->usb3_generic_phy);
1029 if (ret < 0) {
1030 phy_exit(dwc->usb2_generic_phy);
1031 goto err0a;
1032 }
1033
1034 ret = dwc3_core_soft_reset(dwc);
1035 if (ret)
1036 goto err1;
1037
1038 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1039 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1040 if (!dwc->dis_u3_susphy_quirk) {
1041 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1042 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1043 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1044 }
1045
1046 if (!dwc->dis_u2_susphy_quirk) {
1047 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1048 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1049 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1050 }
1051 }
1052
1053 dwc3_core_setup_global_control(dwc);
1054 dwc3_core_num_eps(dwc);
1055
1056 ret = dwc3_setup_scratch_buffers(dwc);
1057 if (ret)
1058 goto err1;
1059
1060 /* Set power down scale of suspend_clk */
1061 dwc3_set_power_down_clk_scale(dwc);
1062
1063 /* Adjust Frame Length */
1064 dwc3_frame_length_adjustment(dwc);
1065
1066 dwc3_set_incr_burst_type(dwc);
1067
1068 usb_phy_set_suspend(dwc->usb2_phy, 0);
1069 usb_phy_set_suspend(dwc->usb3_phy, 0);
1070 ret = phy_power_on(dwc->usb2_generic_phy);
1071 if (ret < 0)
1072 goto err2;
1073
1074 ret = phy_power_on(dwc->usb3_generic_phy);
1075 if (ret < 0)
1076 goto err3;
1077
1078 ret = dwc3_event_buffers_setup(dwc);
1079 if (ret) {
1080 dev_err(dwc->dev, "failed to setup event buffers\n");
1081 goto err4;
1082 }
1083
1084 /*
1085 * ENDXFER polling is available on version 3.10a and later of
1086 * the DWC_usb3 controller. It is NOT available in the
1087 * DWC_usb31 controller.
1088 */
1089 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1090 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1091 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1092 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1093 }
1094
1095 /*
1096 * When configured in HOST mode, after issuing U3/L2 exit controller
1097 * fails to send proper CRC checksum in CRC5 feild. Because of this
1098 * behaviour Transaction Error is generated, resulting in reset and
1099 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1100 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1101 * will correct this problem. This option is to support certain
1102 * legacy ULPI PHYs.
1103 */
1104 if (dwc->resume_hs_terminations) {
1105 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1106 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1107 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1108 }
1109
1110 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1111 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1112
1113 /*
1114 * Enable hardware control of sending remote wakeup
1115 * in HS when the device is in the L1 state.
1116 */
1117 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1118 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1119
1120 /*
1121 * Decouple USB 2.0 L1 & L2 events which will allow for
1122 * gadget driver to only receive U3/L2 suspend & wakeup
1123 * events and prevent the more frequent L1 LPM transitions
1124 * from interrupting the driver.
1125 */
1126 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1127 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1128
1129 if (dwc->dis_tx_ipgap_linecheck_quirk)
1130 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1131
1132 if (dwc->parkmode_disable_ss_quirk)
1133 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1134
1135 if (dwc->parkmode_disable_hs_quirk)
1136 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1137
1138 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1139 (dwc->maximum_speed == USB_SPEED_HIGH ||
1140 dwc->maximum_speed == USB_SPEED_FULL))
1141 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1142
1143 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1144 }
1145
1146 /*
1147 * Must config both number of packets and max burst settings to enable
1148 * RX and/or TX threshold.
1149 */
1150 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1151 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1152 u8 rx_maxburst = dwc->rx_max_burst_prd;
1153 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1154 u8 tx_maxburst = dwc->tx_max_burst_prd;
1155
1156 if (rx_thr_num && rx_maxburst) {
1157 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1158 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1159
1160 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1161 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1162
1163 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1164 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1165
1166 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1167 }
1168
1169 if (tx_thr_num && tx_maxburst) {
1170 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1171 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1172
1173 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1174 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1175
1176 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1177 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1178
1179 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1180 }
1181 }
1182
1183 return 0;
1184
1185 err4:
1186 phy_power_off(dwc->usb3_generic_phy);
1187
1188 err3:
1189 phy_power_off(dwc->usb2_generic_phy);
1190
1191 err2:
1192 usb_phy_set_suspend(dwc->usb2_phy, 1);
1193 usb_phy_set_suspend(dwc->usb3_phy, 1);
1194
1195 err1:
1196 usb_phy_shutdown(dwc->usb2_phy);
1197 usb_phy_shutdown(dwc->usb3_phy);
1198 phy_exit(dwc->usb2_generic_phy);
1199 phy_exit(dwc->usb3_generic_phy);
1200
1201 err0a:
1202 dwc3_ulpi_exit(dwc);
1203
1204 err0:
1205 return ret;
1206 }
1207
dwc3_core_get_phy(struct dwc3 * dwc)1208 static int dwc3_core_get_phy(struct dwc3 *dwc)
1209 {
1210 struct device *dev = dwc->dev;
1211 struct device_node *node = dev->of_node;
1212 int ret;
1213
1214 if (node) {
1215 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1216 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1217 } else {
1218 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1219 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1220 }
1221
1222 if (IS_ERR(dwc->usb2_phy)) {
1223 ret = PTR_ERR(dwc->usb2_phy);
1224 if (ret == -ENXIO || ret == -ENODEV) {
1225 dwc->usb2_phy = NULL;
1226 } else {
1227 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1228 }
1229 }
1230
1231 if (IS_ERR(dwc->usb3_phy)) {
1232 ret = PTR_ERR(dwc->usb3_phy);
1233 if (ret == -ENXIO || ret == -ENODEV) {
1234 dwc->usb3_phy = NULL;
1235 } else {
1236 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1237 }
1238 }
1239
1240 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1241 if (IS_ERR(dwc->usb2_generic_phy)) {
1242 ret = PTR_ERR(dwc->usb2_generic_phy);
1243 if (ret == -ENOSYS || ret == -ENODEV) {
1244 dwc->usb2_generic_phy = NULL;
1245 } else {
1246 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1247 }
1248 }
1249
1250 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1251 if (IS_ERR(dwc->usb3_generic_phy)) {
1252 ret = PTR_ERR(dwc->usb3_generic_phy);
1253 if (ret == -ENOSYS || ret == -ENODEV) {
1254 dwc->usb3_generic_phy = NULL;
1255 } else {
1256 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1257 }
1258 }
1259
1260 return 0;
1261 }
1262
dwc3_core_init_mode(struct dwc3 * dwc)1263 static int dwc3_core_init_mode(struct dwc3 *dwc)
1264 {
1265 struct device *dev = dwc->dev;
1266 int ret;
1267
1268 switch (dwc->dr_mode) {
1269 case USB_DR_MODE_PERIPHERAL:
1270 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1271
1272 if (dwc->usb2_phy)
1273 otg_set_vbus(dwc->usb2_phy->otg, false);
1274 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1275 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1276
1277 ret = dwc3_gadget_init(dwc);
1278 if (ret)
1279 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1280 break;
1281 case USB_DR_MODE_HOST:
1282 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1283
1284 if (dwc->usb2_phy)
1285 otg_set_vbus(dwc->usb2_phy->otg, true);
1286 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1287 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1288
1289 ret = dwc3_host_init(dwc);
1290 if (ret)
1291 return dev_err_probe(dev, ret, "failed to initialize host\n");
1292 break;
1293 case USB_DR_MODE_OTG:
1294 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1295 ret = dwc3_drd_init(dwc);
1296 if (ret)
1297 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1298 break;
1299 default:
1300 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1301 return -EINVAL;
1302 }
1303
1304 return 0;
1305 }
1306
dwc3_core_exit_mode(struct dwc3 * dwc)1307 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1308 {
1309 switch (dwc->dr_mode) {
1310 case USB_DR_MODE_PERIPHERAL:
1311 dwc3_gadget_exit(dwc);
1312 break;
1313 case USB_DR_MODE_HOST:
1314 dwc3_host_exit(dwc);
1315 break;
1316 case USB_DR_MODE_OTG:
1317 dwc3_drd_exit(dwc);
1318 break;
1319 default:
1320 /* do nothing */
1321 break;
1322 }
1323
1324 /* de-assert DRVVBUS for HOST and OTG mode */
1325 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1326 }
1327
dwc3_get_properties(struct dwc3 * dwc)1328 static void dwc3_get_properties(struct dwc3 *dwc)
1329 {
1330 struct device *dev = dwc->dev;
1331 u8 lpm_nyet_threshold;
1332 u8 tx_de_emphasis;
1333 u8 hird_threshold;
1334 u8 rx_thr_num_pkt_prd = 0;
1335 u8 rx_max_burst_prd = 0;
1336 u8 tx_thr_num_pkt_prd = 0;
1337 u8 tx_max_burst_prd = 0;
1338 u8 tx_fifo_resize_max_num;
1339 const char *usb_psy_name;
1340 int ret;
1341
1342 /* default to highest possible threshold */
1343 lpm_nyet_threshold = 0xf;
1344
1345 /* default to -3.5dB de-emphasis */
1346 tx_de_emphasis = 1;
1347
1348 /*
1349 * default to assert utmi_sleep_n and use maximum allowed HIRD
1350 * threshold value of 0b1100
1351 */
1352 hird_threshold = 12;
1353
1354 /*
1355 * default to a TXFIFO size large enough to fit 6 max packets. This
1356 * allows for systems with larger bus latencies to have some headroom
1357 * for endpoints that have a large bMaxBurst value.
1358 */
1359 tx_fifo_resize_max_num = 6;
1360
1361 dwc->maximum_speed = usb_get_maximum_speed(dev);
1362 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1363 dwc->dr_mode = usb_get_dr_mode(dev);
1364 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1365
1366 dwc->sysdev_is_parent = device_property_read_bool(dev,
1367 "linux,sysdev_is_parent");
1368 if (dwc->sysdev_is_parent)
1369 dwc->sysdev = dwc->dev->parent;
1370 else
1371 dwc->sysdev = dwc->dev;
1372
1373 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1374 if (ret >= 0) {
1375 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1376 if (!dwc->usb_psy)
1377 dev_err(dev, "couldn't get usb power supply\n");
1378 }
1379
1380 dwc->has_lpm_erratum = device_property_read_bool(dev,
1381 "snps,has-lpm-erratum");
1382 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1383 &lpm_nyet_threshold);
1384 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1385 "snps,is-utmi-l1-suspend");
1386 device_property_read_u8(dev, "snps,hird-threshold",
1387 &hird_threshold);
1388 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1389 "snps,dis-start-transfer-quirk");
1390 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1391 "snps,usb3_lpm_capable");
1392 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1393 "snps,usb2-lpm-disable");
1394 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1395 "snps,usb2-gadget-lpm-disable");
1396 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1397 &rx_thr_num_pkt_prd);
1398 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1399 &rx_max_burst_prd);
1400 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1401 &tx_thr_num_pkt_prd);
1402 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1403 &tx_max_burst_prd);
1404 dwc->do_fifo_resize = device_property_read_bool(dev,
1405 "tx-fifo-resize");
1406 if (dwc->do_fifo_resize)
1407 device_property_read_u8(dev, "tx-fifo-max-num",
1408 &tx_fifo_resize_max_num);
1409
1410 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1411 "snps,disable_scramble_quirk");
1412 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1413 "snps,u2exit_lfps_quirk");
1414 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1415 "snps,u2ss_inp3_quirk");
1416 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1417 "snps,req_p1p2p3_quirk");
1418 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1419 "snps,del_p1p2p3_quirk");
1420 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1421 "snps,del_phy_power_chg_quirk");
1422 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1423 "snps,lfps_filter_quirk");
1424 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1425 "snps,rx_detect_poll_quirk");
1426 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1427 "snps,dis_u3_susphy_quirk");
1428 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1429 "snps,dis_u2_susphy_quirk");
1430 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1431 "snps,dis_enblslpm_quirk");
1432 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1433 "snps,dis-u1-entry-quirk");
1434 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1435 "snps,dis-u2-entry-quirk");
1436 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1437 "snps,dis_rxdet_inp3_quirk");
1438 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1439 "snps,dis-u2-freeclk-exists-quirk");
1440 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1441 "snps,dis-del-phy-power-chg-quirk");
1442 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1443 "snps,dis-tx-ipgap-linecheck-quirk");
1444 dwc->resume_hs_terminations = device_property_read_bool(dev,
1445 "snps,resume-hs-terminations");
1446 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1447 "snps,parkmode-disable-ss-quirk");
1448 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1449 "snps,parkmode-disable-hs-quirk");
1450
1451 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1452 "snps,tx_de_emphasis_quirk");
1453 device_property_read_u8(dev, "snps,tx_de_emphasis",
1454 &tx_de_emphasis);
1455 device_property_read_string(dev, "snps,hsphy_interface",
1456 &dwc->hsphy_interface);
1457 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1458 &dwc->fladj);
1459
1460 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1461 "snps,dis_metastability_quirk");
1462
1463 dwc->dis_split_quirk = device_property_read_bool(dev,
1464 "snps,dis-split-quirk");
1465
1466 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1467 dwc->tx_de_emphasis = tx_de_emphasis;
1468
1469 dwc->hird_threshold = hird_threshold;
1470
1471 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1472 dwc->rx_max_burst_prd = rx_max_burst_prd;
1473
1474 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1475 dwc->tx_max_burst_prd = tx_max_burst_prd;
1476
1477 dwc->imod_interval = 0;
1478
1479 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1480 }
1481
1482 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1483 bool dwc3_has_imod(struct dwc3 *dwc)
1484 {
1485 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1486 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1487 DWC3_IP_IS(DWC32);
1488 }
1489
dwc3_check_params(struct dwc3 * dwc)1490 static void dwc3_check_params(struct dwc3 *dwc)
1491 {
1492 struct device *dev = dwc->dev;
1493 unsigned int hwparam_gen =
1494 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1495
1496 /* Check for proper value of imod_interval */
1497 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1498 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1499 dwc->imod_interval = 0;
1500 }
1501
1502 /*
1503 * Workaround for STAR 9000961433 which affects only version
1504 * 3.00a of the DWC_usb3 core. This prevents the controller
1505 * interrupt from being masked while handling events. IMOD
1506 * allows us to work around this issue. Enable it for the
1507 * affected version.
1508 */
1509 if (!dwc->imod_interval &&
1510 DWC3_VER_IS(DWC3, 300A))
1511 dwc->imod_interval = 1;
1512
1513 /* Check the maximum_speed parameter */
1514 switch (dwc->maximum_speed) {
1515 case USB_SPEED_FULL:
1516 case USB_SPEED_HIGH:
1517 break;
1518 case USB_SPEED_SUPER:
1519 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1520 dev_warn(dev, "UDC doesn't support Gen 1\n");
1521 break;
1522 case USB_SPEED_SUPER_PLUS:
1523 if ((DWC3_IP_IS(DWC32) &&
1524 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1525 (!DWC3_IP_IS(DWC32) &&
1526 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1527 dev_warn(dev, "UDC doesn't support SSP\n");
1528 break;
1529 default:
1530 dev_err(dev, "invalid maximum_speed parameter %d\n",
1531 dwc->maximum_speed);
1532 fallthrough;
1533 case USB_SPEED_UNKNOWN:
1534 switch (hwparam_gen) {
1535 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1536 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1537 break;
1538 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1539 if (DWC3_IP_IS(DWC32))
1540 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1541 else
1542 dwc->maximum_speed = USB_SPEED_SUPER;
1543 break;
1544 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1545 dwc->maximum_speed = USB_SPEED_HIGH;
1546 break;
1547 default:
1548 dwc->maximum_speed = USB_SPEED_SUPER;
1549 break;
1550 }
1551 break;
1552 }
1553
1554 /*
1555 * Currently the controller does not have visibility into the HW
1556 * parameter to determine the maximum number of lanes the HW supports.
1557 * If the number of lanes is not specified in the device property, then
1558 * set the default to support dual-lane for DWC_usb32 and single-lane
1559 * for DWC_usb31 for super-speed-plus.
1560 */
1561 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1562 switch (dwc->max_ssp_rate) {
1563 case USB_SSP_GEN_2x1:
1564 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1565 dev_warn(dev, "UDC only supports Gen 1\n");
1566 break;
1567 case USB_SSP_GEN_1x2:
1568 case USB_SSP_GEN_2x2:
1569 if (DWC3_IP_IS(DWC31))
1570 dev_warn(dev, "UDC only supports single lane\n");
1571 break;
1572 case USB_SSP_GEN_UNKNOWN:
1573 default:
1574 switch (hwparam_gen) {
1575 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1576 if (DWC3_IP_IS(DWC32))
1577 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1578 else
1579 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1580 break;
1581 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1582 if (DWC3_IP_IS(DWC32))
1583 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1584 break;
1585 }
1586 break;
1587 }
1588 }
1589 }
1590
dwc3_probe(struct platform_device * pdev)1591 static int dwc3_probe(struct platform_device *pdev)
1592 {
1593 struct device *dev = &pdev->dev;
1594 struct resource *res, dwc_res;
1595 struct dwc3 *dwc;
1596
1597 int ret;
1598
1599 void __iomem *regs;
1600
1601 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1602 if (!dwc)
1603 return -ENOMEM;
1604
1605 dwc->dev = dev;
1606
1607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1608 if (!res) {
1609 dev_err(dev, "missing memory resource\n");
1610 return -ENODEV;
1611 }
1612
1613 dwc->xhci_resources[0].start = res->start;
1614 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1615 DWC3_XHCI_REGS_END;
1616 dwc->xhci_resources[0].flags = res->flags;
1617 dwc->xhci_resources[0].name = res->name;
1618
1619 /*
1620 * Request memory region but exclude xHCI regs,
1621 * since it will be requested by the xhci-plat driver.
1622 */
1623 dwc_res = *res;
1624 dwc_res.start += DWC3_GLOBALS_REGS_START;
1625
1626 if (dev->of_node) {
1627 struct device_node *parent = of_get_parent(dev->of_node);
1628
1629 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1630 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1631 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1632 }
1633
1634 of_node_put(parent);
1635 }
1636
1637 regs = devm_ioremap_resource(dev, &dwc_res);
1638 if (IS_ERR(regs))
1639 return PTR_ERR(regs);
1640
1641 dwc->regs = regs;
1642 dwc->regs_size = resource_size(&dwc_res);
1643
1644 dwc3_get_properties(dwc);
1645
1646 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1647 if (IS_ERR(dwc->reset))
1648 return PTR_ERR(dwc->reset);
1649
1650 if (dev->of_node) {
1651 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1652 if (ret == -EPROBE_DEFER)
1653 return ret;
1654 /*
1655 * Clocks are optional, but new DT platforms should support all
1656 * clocks as required by the DT-binding.
1657 */
1658 if (ret < 0)
1659 dwc->num_clks = 0;
1660 else
1661 dwc->num_clks = ret;
1662
1663 }
1664
1665 ret = reset_control_deassert(dwc->reset);
1666 if (ret)
1667 return ret;
1668
1669 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1670 if (ret)
1671 goto assert_reset;
1672
1673 if (!dwc3_core_is_valid(dwc)) {
1674 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1675 ret = -ENODEV;
1676 goto disable_clks;
1677 }
1678
1679 platform_set_drvdata(pdev, dwc);
1680 dwc3_cache_hwparams(dwc);
1681
1682 if (!dwc->sysdev_is_parent &&
1683 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1684 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1685 if (ret)
1686 goto disable_clks;
1687 }
1688
1689 spin_lock_init(&dwc->lock);
1690 mutex_init(&dwc->mutex);
1691
1692 pm_runtime_get_noresume(dev);
1693 pm_runtime_set_active(dev);
1694 pm_runtime_use_autosuspend(dev);
1695 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1696 pm_runtime_enable(dev);
1697
1698 pm_runtime_forbid(dev);
1699
1700 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1701 if (ret) {
1702 dev_err(dwc->dev, "failed to allocate event buffers\n");
1703 ret = -ENOMEM;
1704 goto err2;
1705 }
1706
1707 ret = dwc3_get_dr_mode(dwc);
1708 if (ret)
1709 goto err3;
1710
1711 ret = dwc3_alloc_scratch_buffers(dwc);
1712 if (ret)
1713 goto err3;
1714
1715 ret = dwc3_core_init(dwc);
1716 if (ret) {
1717 dev_err_probe(dev, ret, "failed to initialize core\n");
1718 goto err4;
1719 }
1720
1721 dwc3_check_params(dwc);
1722 dwc3_debugfs_init(dwc);
1723
1724 ret = dwc3_core_init_mode(dwc);
1725 if (ret)
1726 goto err5;
1727
1728 pm_runtime_put(dev);
1729
1730 dma_set_max_seg_size(dev, UINT_MAX);
1731
1732 return 0;
1733
1734 err5:
1735 dwc3_debugfs_exit(dwc);
1736 dwc3_event_buffers_cleanup(dwc);
1737
1738 usb_phy_set_suspend(dwc->usb2_phy, 1);
1739 usb_phy_set_suspend(dwc->usb3_phy, 1);
1740 phy_power_off(dwc->usb2_generic_phy);
1741 phy_power_off(dwc->usb3_generic_phy);
1742
1743 usb_phy_shutdown(dwc->usb2_phy);
1744 usb_phy_shutdown(dwc->usb3_phy);
1745 phy_exit(dwc->usb2_generic_phy);
1746 phy_exit(dwc->usb3_generic_phy);
1747
1748 dwc3_ulpi_exit(dwc);
1749
1750 err4:
1751 dwc3_free_scratch_buffers(dwc);
1752
1753 err3:
1754 dwc3_free_event_buffers(dwc);
1755
1756 err2:
1757 pm_runtime_allow(dev);
1758 pm_runtime_disable(dev);
1759 pm_runtime_set_suspended(dev);
1760 pm_runtime_put_noidle(dev);
1761 disable_clks:
1762 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1763 assert_reset:
1764 reset_control_assert(dwc->reset);
1765
1766 if (dwc->usb_psy)
1767 power_supply_put(dwc->usb_psy);
1768
1769 return ret;
1770 }
1771
dwc3_remove(struct platform_device * pdev)1772 static int dwc3_remove(struct platform_device *pdev)
1773 {
1774 struct dwc3 *dwc = platform_get_drvdata(pdev);
1775
1776 pm_runtime_get_sync(&pdev->dev);
1777
1778 dwc3_core_exit_mode(dwc);
1779 dwc3_debugfs_exit(dwc);
1780
1781 dwc3_core_exit(dwc);
1782 dwc3_ulpi_exit(dwc);
1783
1784 pm_runtime_allow(&pdev->dev);
1785 pm_runtime_disable(&pdev->dev);
1786 pm_runtime_put_noidle(&pdev->dev);
1787 /*
1788 * HACK: Clear the driver data, which is currently accessed by parent
1789 * glue drivers, before allowing the parent to suspend.
1790 */
1791 platform_set_drvdata(pdev, NULL);
1792 pm_runtime_set_suspended(&pdev->dev);
1793
1794 dwc3_free_event_buffers(dwc);
1795 dwc3_free_scratch_buffers(dwc);
1796
1797 if (dwc->usb_psy)
1798 power_supply_put(dwc->usb_psy);
1799
1800 return 0;
1801 }
1802
1803 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1804 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1805 {
1806 int ret;
1807
1808 ret = reset_control_deassert(dwc->reset);
1809 if (ret)
1810 return ret;
1811
1812 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1813 if (ret)
1814 goto assert_reset;
1815
1816 ret = dwc3_core_init(dwc);
1817 if (ret)
1818 goto disable_clks;
1819
1820 return 0;
1821
1822 disable_clks:
1823 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1824 assert_reset:
1825 reset_control_assert(dwc->reset);
1826
1827 return ret;
1828 }
1829
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1830 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1831 {
1832 unsigned long flags;
1833 u32 reg;
1834
1835 switch (dwc->current_dr_role) {
1836 case DWC3_GCTL_PRTCAP_DEVICE:
1837 if (pm_runtime_suspended(dwc->dev))
1838 break;
1839 dwc3_gadget_suspend(dwc);
1840 synchronize_irq(dwc->irq_gadget);
1841 dwc3_core_exit(dwc);
1842 break;
1843 case DWC3_GCTL_PRTCAP_HOST:
1844 if (!PMSG_IS_AUTO(msg)) {
1845 dwc3_core_exit(dwc);
1846 break;
1847 }
1848
1849 /* Let controller to suspend HSPHY before PHY driver suspends */
1850 if (dwc->dis_u2_susphy_quirk ||
1851 dwc->dis_enblslpm_quirk) {
1852 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1853 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1854 DWC3_GUSB2PHYCFG_SUSPHY;
1855 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1856
1857 /* Give some time for USB2 PHY to suspend */
1858 usleep_range(5000, 6000);
1859 }
1860
1861 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1862 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1863 break;
1864 case DWC3_GCTL_PRTCAP_OTG:
1865 /* do nothing during runtime_suspend */
1866 if (PMSG_IS_AUTO(msg))
1867 break;
1868
1869 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1870 spin_lock_irqsave(&dwc->lock, flags);
1871 dwc3_gadget_suspend(dwc);
1872 spin_unlock_irqrestore(&dwc->lock, flags);
1873 synchronize_irq(dwc->irq_gadget);
1874 }
1875
1876 dwc3_otg_exit(dwc);
1877 dwc3_core_exit(dwc);
1878 break;
1879 default:
1880 /* do nothing */
1881 break;
1882 }
1883
1884 return 0;
1885 }
1886
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1887 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1888 {
1889 unsigned long flags;
1890 int ret;
1891 u32 reg;
1892
1893 switch (dwc->current_dr_role) {
1894 case DWC3_GCTL_PRTCAP_DEVICE:
1895 ret = dwc3_core_init_for_resume(dwc);
1896 if (ret)
1897 return ret;
1898
1899 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1900 dwc3_gadget_resume(dwc);
1901 break;
1902 case DWC3_GCTL_PRTCAP_HOST:
1903 if (!PMSG_IS_AUTO(msg)) {
1904 ret = dwc3_core_init_for_resume(dwc);
1905 if (ret)
1906 return ret;
1907 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1908 break;
1909 }
1910 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1911 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1912 if (dwc->dis_u2_susphy_quirk)
1913 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1914
1915 if (dwc->dis_enblslpm_quirk)
1916 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1917
1918 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1919
1920 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1921 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1922 break;
1923 case DWC3_GCTL_PRTCAP_OTG:
1924 /* nothing to do on runtime_resume */
1925 if (PMSG_IS_AUTO(msg))
1926 break;
1927
1928 ret = dwc3_core_init_for_resume(dwc);
1929 if (ret)
1930 return ret;
1931
1932 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1933
1934 dwc3_otg_init(dwc);
1935 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1936 dwc3_otg_host_init(dwc);
1937 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1938 spin_lock_irqsave(&dwc->lock, flags);
1939 dwc3_gadget_resume(dwc);
1940 spin_unlock_irqrestore(&dwc->lock, flags);
1941 }
1942
1943 break;
1944 default:
1945 /* do nothing */
1946 break;
1947 }
1948
1949 return 0;
1950 }
1951
dwc3_runtime_checks(struct dwc3 * dwc)1952 static int dwc3_runtime_checks(struct dwc3 *dwc)
1953 {
1954 switch (dwc->current_dr_role) {
1955 case DWC3_GCTL_PRTCAP_DEVICE:
1956 if (dwc->connected)
1957 return -EBUSY;
1958 break;
1959 case DWC3_GCTL_PRTCAP_HOST:
1960 default:
1961 /* do nothing */
1962 break;
1963 }
1964
1965 return 0;
1966 }
1967
dwc3_runtime_suspend(struct device * dev)1968 static int dwc3_runtime_suspend(struct device *dev)
1969 {
1970 struct dwc3 *dwc = dev_get_drvdata(dev);
1971 int ret;
1972
1973 if (dwc3_runtime_checks(dwc))
1974 return -EBUSY;
1975
1976 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1977 if (ret)
1978 return ret;
1979
1980 device_init_wakeup(dev, true);
1981
1982 return 0;
1983 }
1984
dwc3_runtime_resume(struct device * dev)1985 static int dwc3_runtime_resume(struct device *dev)
1986 {
1987 struct dwc3 *dwc = dev_get_drvdata(dev);
1988 int ret;
1989
1990 device_init_wakeup(dev, false);
1991
1992 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1993 if (ret)
1994 return ret;
1995
1996 switch (dwc->current_dr_role) {
1997 case DWC3_GCTL_PRTCAP_DEVICE:
1998 dwc3_gadget_process_pending_events(dwc);
1999 break;
2000 case DWC3_GCTL_PRTCAP_HOST:
2001 default:
2002 /* do nothing */
2003 break;
2004 }
2005
2006 pm_runtime_mark_last_busy(dev);
2007
2008 return 0;
2009 }
2010
dwc3_runtime_idle(struct device * dev)2011 static int dwc3_runtime_idle(struct device *dev)
2012 {
2013 struct dwc3 *dwc = dev_get_drvdata(dev);
2014
2015 switch (dwc->current_dr_role) {
2016 case DWC3_GCTL_PRTCAP_DEVICE:
2017 if (dwc3_runtime_checks(dwc))
2018 return -EBUSY;
2019 break;
2020 case DWC3_GCTL_PRTCAP_HOST:
2021 default:
2022 /* do nothing */
2023 break;
2024 }
2025
2026 pm_runtime_mark_last_busy(dev);
2027 pm_runtime_autosuspend(dev);
2028
2029 return 0;
2030 }
2031 #endif /* CONFIG_PM */
2032
2033 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2034 static int dwc3_suspend(struct device *dev)
2035 {
2036 struct dwc3 *dwc = dev_get_drvdata(dev);
2037 int ret;
2038
2039 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2040 if (ret)
2041 return ret;
2042
2043 pinctrl_pm_select_sleep_state(dev);
2044
2045 return 0;
2046 }
2047
dwc3_resume(struct device * dev)2048 static int dwc3_resume(struct device *dev)
2049 {
2050 struct dwc3 *dwc = dev_get_drvdata(dev);
2051 int ret;
2052
2053 pinctrl_pm_select_default_state(dev);
2054
2055 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2056 if (ret)
2057 return ret;
2058
2059 pm_runtime_disable(dev);
2060 pm_runtime_set_active(dev);
2061 pm_runtime_enable(dev);
2062
2063 return 0;
2064 }
2065
dwc3_complete(struct device * dev)2066 static void dwc3_complete(struct device *dev)
2067 {
2068 struct dwc3 *dwc = dev_get_drvdata(dev);
2069 u32 reg;
2070
2071 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2072 dwc->dis_split_quirk) {
2073 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2074 reg |= DWC3_GUCTL3_SPLITDISABLE;
2075 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2076 }
2077 }
2078 #else
2079 #define dwc3_complete NULL
2080 #endif /* CONFIG_PM_SLEEP */
2081
2082 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2083 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2084 .complete = dwc3_complete,
2085 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2086 dwc3_runtime_idle)
2087 };
2088
2089 #ifdef CONFIG_OF
2090 static const struct of_device_id of_dwc3_match[] = {
2091 {
2092 .compatible = "snps,dwc3"
2093 },
2094 {
2095 .compatible = "synopsys,dwc3"
2096 },
2097 { },
2098 };
2099 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2100 #endif
2101
2102 #ifdef CONFIG_ACPI
2103
2104 #define ACPI_ID_INTEL_BSW "808622B7"
2105
2106 static const struct acpi_device_id dwc3_acpi_match[] = {
2107 { ACPI_ID_INTEL_BSW, 0 },
2108 { },
2109 };
2110 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2111 #endif
2112
2113 static struct platform_driver dwc3_driver = {
2114 .probe = dwc3_probe,
2115 .remove = dwc3_remove,
2116 .driver = {
2117 .name = "dwc3",
2118 .of_match_table = of_match_ptr(of_dwc3_match),
2119 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2120 .pm = &dwc3_dev_pm_ops,
2121 },
2122 };
2123
2124 module_platform_driver(dwc3_driver);
2125
2126 MODULE_ALIAS("platform:dwc3");
2127 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2128 MODULE_LICENSE("GPL v2");
2129 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2130