| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_interrupts.c | 129 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, in dpu_hw_intr_clear_intr_status_nolock() argument
134 if (!intr) in dpu_hw_intr_clear_intr_status_nolock()
138 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_clear_intr_status_nolock()
144 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, in dpu_hw_intr_dispatch_irq() argument
155 if (!intr) in dpu_hw_intr_dispatch_irq()
163 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_dispatch_irq()
165 if (!test_bit(reg_idx, &intr->irq_mask)) in dpu_hw_intr_dispatch_irq()
169 irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); in dpu_hw_intr_dispatch_irq()
172 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); in dpu_hw_intr_dispatch_irq()
176 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_dispatch_irq()
[all …]
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| D | dpu_hw_interrupts.h | 50 struct dpu_hw_intr *intr,
60 struct dpu_hw_intr *intr,
70 struct dpu_hw_intr *intr);
78 struct dpu_hw_intr *intr);
89 struct dpu_hw_intr *intr,
101 struct dpu_hw_intr *intr,
111 struct dpu_hw_intr *intr);
119 struct dpu_hw_intr *intr, unsigned long irq_flags);
153 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
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| /drivers/irqchip/ |
| D | irq-ti-sci-intr.c | 62 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_irq_domain_translate() local
68 *type = intr->type; in ti_sci_intr_irq_domain_translate()
80 static int ti_sci_intr_xlate_irq(struct ti_sci_intr_irq_domain *intr, u32 irq) in ti_sci_intr_xlate_irq() argument
82 struct device_node *np = dev_of_node(intr->dev); in ti_sci_intr_xlate_irq()
111 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_irq_domain_free() local
118 intr->sci->ops.rm_irq_ops.free_irq(intr->sci, in ti_sci_intr_irq_domain_free()
119 intr->ti_sci_id, data->hwirq, in ti_sci_intr_irq_domain_free()
120 intr->ti_sci_id, out_irq); in ti_sci_intr_irq_domain_free()
121 ti_sci_release_resource(intr->out_irqs, out_irq); in ti_sci_intr_irq_domain_free()
137 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_alloc_parent_irq() local
[all …]
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| D | irq-mips-gic.c | 69 static void gic_clear_pcpu_masks(unsigned int intr) in gic_clear_pcpu_masks() argument
75 clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); in gic_clear_pcpu_masks()
78 static bool gic_local_irq_is_routable(int intr) in gic_local_irq_is_routable() argument
87 switch (intr) { in gic_local_irq_is_routable()
153 unsigned int intr; in gic_handle_shared_int() local
169 for_each_set_bit(intr, pending, gic_shared_intrs) { in gic_handle_shared_int()
172 GIC_SHARED_TO_HWIRQ(intr)); in gic_handle_shared_int()
175 GIC_SHARED_TO_HWIRQ(intr)); in gic_handle_shared_int()
181 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); in gic_mask_irq() local
183 write_gic_rmask(intr); in gic_mask_irq()
[all …]
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| /drivers/net/ethernet/cisco/enic/ |
| D | vnic_intr.c | 30 void vnic_intr_free(struct vnic_intr *intr) in vnic_intr_free() argument
32 intr->ctrl = NULL; in vnic_intr_free()
35 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in vnic_intr_alloc() argument
38 intr->index = index; in vnic_intr_alloc()
39 intr->vdev = vdev; in vnic_intr_alloc()
41 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in vnic_intr_alloc()
42 if (!intr->ctrl) { in vnic_intr_alloc()
51 void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer, in vnic_intr_init() argument
54 vnic_intr_coalescing_timer_set(intr, coalescing_timer); in vnic_intr_init()
55 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
[all …]
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| D | vnic_intr.h | 54 static inline void vnic_intr_unmask(struct vnic_intr *intr) in vnic_intr_unmask() argument
56 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
59 static inline void vnic_intr_mask(struct vnic_intr *intr) in vnic_intr_mask() argument
61 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
64 static inline int vnic_intr_masked(struct vnic_intr *intr) in vnic_intr_masked() argument
66 return ioread32(&intr->ctrl->mask); in vnic_intr_masked()
69 static inline void vnic_intr_return_credits(struct vnic_intr *intr, in vnic_intr_return_credits() argument
79 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in vnic_intr_return_credits()
82 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) in vnic_intr_credits() argument
84 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
[all …]
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| /drivers/scsi/fnic/ |
| D | vnic_intr.c | 27 void vnic_intr_free(struct vnic_intr *intr) in vnic_intr_free() argument
29 intr->ctrl = NULL; in vnic_intr_free()
32 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in vnic_intr_alloc() argument
35 intr->index = index; in vnic_intr_alloc()
36 intr->vdev = vdev; in vnic_intr_alloc()
38 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in vnic_intr_alloc()
39 if (!intr->ctrl) { in vnic_intr_alloc()
48 void vnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer, in vnic_intr_init() argument
51 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); in vnic_intr_init()
52 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
[all …]
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| D | vnic_intr.h | 68 static inline void vnic_intr_unmask(struct vnic_intr *intr) in vnic_intr_unmask() argument
70 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
73 static inline void vnic_intr_mask(struct vnic_intr *intr) in vnic_intr_mask() argument
75 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
78 static inline void vnic_intr_return_credits(struct vnic_intr *intr, in vnic_intr_return_credits() argument
88 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in vnic_intr_return_credits()
91 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) in vnic_intr_credits() argument
93 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
96 static inline void vnic_intr_return_all_credits(struct vnic_intr *intr) in vnic_intr_return_all_credits() argument
98 unsigned int credits = vnic_intr_credits(intr); in vnic_intr_return_all_credits()
[all …]
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| /drivers/scsi/snic/ |
| D | vnic_intr.c | 26 void svnic_intr_free(struct vnic_intr *intr) in svnic_intr_free() argument
28 intr->ctrl = NULL; in svnic_intr_free()
31 int svnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, in svnic_intr_alloc() argument
34 intr->index = index; in svnic_intr_alloc()
35 intr->vdev = vdev; in svnic_intr_alloc()
37 intr->ctrl = svnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in svnic_intr_alloc()
38 if (!intr->ctrl) { in svnic_intr_alloc()
47 void svnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer, in svnic_intr_init() argument
50 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); in svnic_intr_init()
51 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in svnic_intr_init()
[all …]
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| D | vnic_intr.h | 54 svnic_intr_unmask(struct vnic_intr *intr) in svnic_intr_unmask() argument
56 iowrite32(0, &intr->ctrl->mask); in svnic_intr_unmask()
60 svnic_intr_mask(struct vnic_intr *intr) in svnic_intr_mask() argument
62 iowrite32(1, &intr->ctrl->mask); in svnic_intr_mask()
66 svnic_intr_return_credits(struct vnic_intr *intr, in svnic_intr_return_credits() argument
78 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in svnic_intr_return_credits()
82 svnic_intr_credits(struct vnic_intr *intr) in svnic_intr_credits() argument
84 return ioread32(&intr->ctrl->int_credits); in svnic_intr_credits()
88 svnic_intr_return_all_credits(struct vnic_intr *intr) in svnic_intr_return_all_credits() argument
90 unsigned int credits = svnic_intr_credits(intr); in svnic_intr_return_all_credits()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| D | gp100.c | 66 u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; in gp100_ce_intr() local
67 if (intr & 0x00000001) { //XXX: guess in gp100_ce_intr()
70 intr &= ~0x00000001; in gp100_ce_intr()
72 if (intr & 0x00000002) { //XXX: guess in gp100_ce_intr()
75 intr &= ~0x00000002; in gp100_ce_intr()
77 if (intr & 0x00000004) { in gp100_ce_intr()
80 intr &= ~0x00000004; in gp100_ce_intr()
82 if (intr) { in gp100_ce_intr()
83 nvkm_warn(subdev, "intr %08x\n", intr); in gp100_ce_intr()
84 nvkm_wr32(device, 0x104410 + base, intr); in gp100_ce_intr()
[all …]
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| D | gk104.c | 65 u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; in gk104_ce_intr() local
66 if (intr & 0x00000001) { in gk104_ce_intr()
69 intr &= ~0x00000001; in gk104_ce_intr()
71 if (intr & 0x00000002) { in gk104_ce_intr()
74 intr &= ~0x00000002; in gk104_ce_intr()
76 if (intr & 0x00000004) { in gk104_ce_intr()
79 intr &= ~0x00000004; in gk104_ce_intr()
81 if (intr) { in gk104_ce_intr()
82 nvkm_warn(subdev, "intr %08x\n", intr); in gk104_ce_intr()
83 nvkm_wr32(device, 0x104908 + base, intr); in gk104_ce_intr()
[all …]
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| /drivers/net/wireless/zydas/zd1211rw/ |
| D | zd_usb.c | 361 struct zd_usb_interrupt *intr = &usb->intr; in handle_regs_int_override() local
364 spin_lock_irqsave(&intr->lock, flags); in handle_regs_int_override()
365 if (atomic_read(&intr->read_regs_enabled)) { in handle_regs_int_override()
366 atomic_set(&intr->read_regs_enabled, 0); in handle_regs_int_override()
367 intr->read_regs_int_overridden = 1; in handle_regs_int_override()
368 complete(&intr->read_regs.completion); in handle_regs_int_override()
370 spin_unlock_irqrestore(&intr->lock, flags); in handle_regs_int_override()
376 struct zd_usb_interrupt *intr = &usb->intr; in handle_regs_int() local
381 spin_lock_irqsave(&intr->lock, flags); in handle_regs_int()
391 } else if (atomic_read(&intr->read_regs_enabled)) { in handle_regs_int()
[all …]
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| /drivers/usb/mtu3/ |
| D | mtu3_trace.h | 38 TP_PROTO(u32 intr),
39 TP_ARGS(intr),
41 __field(u32, intr)
44 __entry->intr = intr;
46 TP_printk("(%08x) %s %s %s %s %s %s", __entry->intr,
47 __entry->intr & HOT_RST_INTR ? "HOT_RST" : "",
48 __entry->intr & WARM_RST_INTR ? "WARM_RST" : "",
49 __entry->intr & ENTER_U3_INTR ? "ENT_U3" : "",
50 __entry->intr & EXIT_U3_INTR ? "EXIT_U3" : "",
51 __entry->intr & VBUS_RISE_INTR ? "VBUS_RISE" : "",
[all …]
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| /drivers/gpu/host1x/ |
| D | intr.c | 174 spin_lock(&syncpt->intr.lock); in process_wait_list()
176 remove_completed_waiters(&syncpt->intr.wait_head, threshold, in process_wait_list()
179 empty = list_empty(&syncpt->intr.wait_head); in process_wait_list()
183 reset_threshold_interrupt(host, &syncpt->intr.wait_head, in process_wait_list()
186 spin_unlock(&syncpt->intr.lock); in process_wait_list()
203 container_of(syncpt_intr, struct host1x_syncpt, intr); in syncpt_thresh_work()
234 spin_lock(&syncpt->intr.lock); in host1x_intr_add_action()
236 queue_was_empty = list_empty(&syncpt->intr.wait_head); in host1x_intr_add_action()
238 if (add_waiter_to_queue(waiter, &syncpt->intr.wait_head)) { in host1x_intr_add_action()
250 spin_unlock(&syncpt->intr.lock); in host1x_intr_add_action()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | g84.c | 145 uint32_t intr; in g84_therm_intr() local
149 intr = nvkm_rd32(device, 0x20100) & 0x3ff; in g84_therm_intr()
152 if (intr & 0x002) { in g84_therm_intr()
156 intr &= ~0x002; in g84_therm_intr()
160 if (intr & 0x004) { in g84_therm_intr()
164 intr &= ~0x004; in g84_therm_intr()
168 if (intr & 0x008) { in g84_therm_intr()
172 intr &= ~0x008; in g84_therm_intr()
176 if (intr & 0x010) { in g84_therm_intr()
180 intr &= ~0x010; in g84_therm_intr()
[all …]
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| /drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | core.c | 16 u32 intr; in mt7603_irq_handler() local
18 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7603_irq_handler()
19 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); in mt7603_irq_handler()
24 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7603_irq_handler()
26 intr &= dev->mt76.mmio.irqmask; in mt7603_irq_handler()
28 if (intr & MT_INT_MAC_IRQ3) { in mt7603_irq_handler()
39 if (intr & MT_INT_TX_DONE_ALL) { in mt7603_irq_handler()
44 if (intr & MT_INT_RX_DONE(0)) { in mt7603_irq_handler()
50 if (intr & MT_INT_RX_DONE(1)) { in mt7603_irq_handler()
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| /drivers/mtd/nand/onenand/ |
| D | onenand_omap2.c | 129 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) in wait_err() argument
132 msg, state, ctrl, intr); in wait_err()
136 unsigned int intr) in wait_warn() argument
139 "intr 0x%04x\n", msg, state, ctrl, intr); in wait_warn()
146 unsigned int intr = 0; in omap2_onenand_wait() local
170 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
171 if (intr & ONENAND_INT_MASTER) in omap2_onenand_wait()
176 wait_err("controller error", state, ctrl, intr); in omap2_onenand_wait()
179 if ((intr & intr_flags) == intr_flags) in omap2_onenand_wait()
200 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/mc/ |
| D | base.c | 44 for (map = mc->func->intr; !mask && map->stat; map++) { in nvkm_mc_intr_mask()
71 u32 intr = mc->func->intr_stat(mc); in nvkm_mc_intr_stat() local
72 if (WARN_ON_ONCE(intr == 0xffffffff)) in nvkm_mc_intr_stat()
73 intr = 0; /* likely fallen off the bus */ in nvkm_mc_intr_stat()
74 return intr; in nvkm_mc_intr_stat()
85 u32 stat, intr; in nvkm_mc_intr() local
90 stat = intr = nvkm_mc_intr_stat(mc); in nvkm_mc_intr()
94 if (tdev->intr >= 0 && (stat & BIT(tdev->intr))) { in nvkm_mc_intr()
98 stat &= ~BIT(tdev->intr); in nvkm_mc_intr()
106 for (map = mc->func->intr; map->stat; map++) { in nvkm_mc_intr()
[all …]
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| D | ga100.c | 37 ga100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 intr) in ga100_mc_intr_mask() argument
39 nvkm_wr32(mc->subdev.device, 0xb81210, mask & intr ); in ga100_mc_intr_mask()
40 nvkm_wr32(mc->subdev.device, 0xb81410, mask & ~(mask & intr)); in ga100_mc_intr_mask()
46 u32 intr_top = nvkm_rd32(mc->subdev.device, 0xb81600), intr = 0x00000000; in ga100_mc_intr_stat() local
48 intr = nvkm_mask(mc->subdev.device, 0xb81010, 0x00000000, 0x00000000); in ga100_mc_intr_stat()
49 return intr; in ga100_mc_intr_stat()
62 .intr = gp100_mc_intr,
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| D | gp100.c | 30 bool intr; member
38 u32 mask = mc->intr ? mc->mask : 0, i; in gp100_mc_intr_update()
51 mc->intr = false; in gp100_mc_intr_unarm()
62 mc->intr = true; in gp100_mc_intr_rearm()
68 gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) in gp100_mc_intr_mask() argument
73 mc->mask = (mc->mask & ~mask) | intr; in gp100_mc_intr_mask()
99 .intr = gp100_mc_intr,
119 mc->intr = false; in gp100_mc_new_()
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| D | tu102.c | 28 bool intr; member
36 u32 mask = mc->intr ? mc->mask : 0, i; in tu102_mc_intr_update()
56 mc->intr = false; in tu102_mc_intr_unarm()
68 mc->intr = true; in tu102_mc_intr_rearm()
74 tu102_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) in tu102_mc_intr_mask() argument
80 mc->mask = (mc->mask & ~mask) | intr; in tu102_mc_intr_mask()
107 .intr = gp100_mc_intr,
127 mc->intr = false; in tu102_mc_new_()
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| /drivers/net/wireless/mediatek/mt76/mt7915/ |
| D | pci.c | 100 u32 intr, intr1, mask; in mt7915_irq_tasklet() local
106 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7915_irq_tasklet()
107 intr &= dev->mt76.mmio.irqmask; in mt7915_irq_tasklet()
108 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); in mt7915_irq_tasklet()
115 intr |= intr1; in mt7915_irq_tasklet()
118 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7915_irq_tasklet()
120 mask = intr & MT_INT_RX_DONE_ALL; in mt7915_irq_tasklet()
121 if (intr & MT_INT_TX_DONE_MCU) in mt7915_irq_tasklet()
126 if (intr & MT_INT_TX_DONE_MCU) in mt7915_irq_tasklet()
129 if (intr & MT_INT_RX_DONE_DATA0) in mt7915_irq_tasklet()
[all …]
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| /drivers/scsi/ |
| D | mac53c94.c | 46 int intr; member
200 int nb, stat, seq, intr; in mac53c94_interrupt() local
209 intr = readb(®s->interrupt); in mac53c94_interrupt()
213 intr, stat, seq, state->phase); in mac53c94_interrupt()
216 if (intr & INTR_RESET) { in mac53c94_interrupt()
224 if (intr & INTR_ILL_CMD) { in mac53c94_interrupt()
226 intr, stat, seq, state->phase); in mac53c94_interrupt()
234 intr, stat, seq, state->phase); in mac53c94_interrupt()
250 if (intr & INTR_DISCONNECT) { in mac53c94_interrupt()
255 if (intr != INTR_BUS_SERV + INTR_DONE) { in mac53c94_interrupt()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| D | gt215.c | 144 u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); in gt215_pmu_intr() local
146 if (intr & 0x00000020) { in gt215_pmu_intr()
153 intr &= ~0x00000020; in gt215_pmu_intr()
157 if (intr & 0x00000040) { in gt215_pmu_intr()
160 intr &= ~0x00000040; in gt215_pmu_intr()
163 if (intr & 0x00000080) { in gt215_pmu_intr()
168 intr &= ~0x00000080; in gt215_pmu_intr()
171 if (intr) { in gt215_pmu_intr()
172 nvkm_error(subdev, "intr %08x\n", intr); in gt215_pmu_intr()
173 nvkm_wr32(device, 0x10a004, intr); in gt215_pmu_intr()
[all …]
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