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Searched refs:ix (Results 1 – 25 of 67) sorted by relevance

123

/drivers/hwmon/
Ddme1737.c74 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ argument
75 (ix) < 7 ? 0x94 + (ix) : \
77 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ argument
78 : 0x91 + (ix) * 2)
79 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ argument
80 : 0x92 + (ix) * 2)
83 #define DME1737_REG_TEMP(ix) (0x25 + (ix)) argument
84 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) argument
85 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) argument
86 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ argument
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Dvt1211.c62 #define VT1211_REG_IN(ix) (0x21 + (ix)) argument
63 #define VT1211_REG_IN_MIN(ix) ((ix) == 0 ? 0x3e : 0x2a + 2 * (ix)) argument
64 #define VT1211_REG_IN_MAX(ix) ((ix) == 0 ? 0x3d : 0x29 + 2 * (ix)) argument
72 #define VT1211_REG_FAN(ix) (0x29 + (ix)) argument
73 #define VT1211_REG_FAN_MIN(ix) (0x3b + (ix)) argument
78 #define VT1211_REG_PWM(ix) (0x60 + (ix)) argument
82 #define VT1211_REG_PWM_AUTO_PWM(ix, ap) (0x58 + 2 * (ix) - (ap)) argument
134 #define ISVOLT(ix, uch_config) ((ix) > 4 ? 1 : \ argument
135 !(((uch_config) >> ((ix) + 2)) & 1))
138 #define ISTEMP(ix, uch_config) ((ix) < 2 ? 1 : \ argument
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Damc6821.c271 int ix = to_sensor_dev_attr(devattr)->index; in temp_show() local
273 return sprintf(buf, "%d\n", data->temp[ix] * 1000); in temp_show()
281 int ix = to_sensor_dev_attr(attr)->index; in temp_store() local
290 data->temp[ix] = val; in temp_store()
291 if (i2c_smbus_write_byte_data(client, temp_reg[ix], data->temp[ix])) { in temp_store()
303 int ix = to_sensor_dev_attr(devattr)->index; in temp_alarm_show() local
306 switch (ix) { in temp_alarm_show()
326 dev_dbg(dev, "Unknown attr->index (%d).\n", ix); in temp_alarm_show()
436 int ix = to_sensor_dev_attr_2(devattr)->index; in temp_auto_point_temp_show() local
442 data->temp1_auto_point_temp[ix] * 1000); in temp_auto_point_temp_show()
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/drivers/net/ethernet/mellanox/mlx5/core/en/
Drx_res.c286 int ix; in mlx5e_rx_res_channels_init() local
298 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
299 err = mlx5e_rqt_init_direct(&res->channels[ix].direct_rqt, in mlx5e_rx_res_channels_init()
303 err, ix); in mlx5e_rx_res_channels_init()
308 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
310 mlx5e_rqt_get_rqtn(&res->channels[ix].direct_rqt), in mlx5e_rx_res_channels_init()
315 err = mlx5e_tir_init(&res->channels[ix].direct_tir, builder, res->mdev, true); in mlx5e_rx_res_channels_init()
318 err, ix); in mlx5e_rx_res_channels_init()
328 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
329 err = mlx5e_rqt_init_direct(&res->channels[ix].xsk_rqt, in mlx5e_rx_res_channels_init()
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Dchannels.c13 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn) in mlx5e_channels_get_regular_rqn() argument
17 WARN_ON(ix >= mlx5e_channels_get_num(chs)); in mlx5e_channels_get_regular_rqn()
18 c = chs->c[ix]; in mlx5e_channels_get_regular_rqn()
23 bool mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn) in mlx5e_channels_get_xsk_rqn() argument
27 WARN_ON(ix >= mlx5e_channels_get_num(chs)); in mlx5e_channels_get_xsk_rqn()
28 c = chs->c[ix]; in mlx5e_channels_get_xsk_rqn()
Drqt.c72 unsigned int ix = i; in mlx5e_calc_indir_rqns() local
75 ix = mlx5e_bits_invert(ix, ilog2(MLX5E_INDIR_RQT_SIZE)); in mlx5e_calc_indir_rqns()
77 ix = indir->table[ix]; in mlx5e_calc_indir_rqns()
79 if (WARN_ON(ix >= num_rqns)) in mlx5e_calc_indir_rqns()
84 rss_rqns[i] = rqns[ix]; in mlx5e_calc_indir_rqns()
Dfs_tt_redirect.c150 int ix = 0; in fs_udp_create_groups() local
180 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
181 ix += MLX5E_FS_UDP_GROUP1_SIZE; in fs_udp_create_groups()
182 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
190 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
191 ix += MLX5E_FS_UDP_GROUP2_SIZE; in fs_udp_create_groups()
192 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
429 int ix = 0; in fs_any_create_groups() local
448 MLX5_SET_CFG(in, start_flow_index, ix); in fs_any_create_groups()
449 ix += MLX5E_FS_ANY_GROUP1_SIZE; in fs_any_create_groups()
[all …]
Drx_res.h34 u32 mlx5e_rx_res_get_tirn_direct(struct mlx5e_rx_res *res, unsigned int ix);
35 u32 mlx5e_rx_res_get_tirn_xsk(struct mlx5e_rx_res *res, unsigned int ix);
44 unsigned int ix);
45 int mlx5e_rx_res_xsk_deactivate(struct mlx5e_rx_res *res, unsigned int ix);
Dparams.h57 u16 *ix) in mlx5e_qid_get_ch_if_in_group() argument
65 *ix = ch; in mlx5e_qid_get_ch_if_in_group()
71 u16 *ix, in mlx5e_qid_get_ch_and_group() argument
76 *ix = qid % nch; in mlx5e_qid_get_ch_and_group()
/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
Dpool.c46 static int mlx5e_xsk_add_pool(struct mlx5e_xsk *xsk, struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_add_pool() argument
54 xsk->pools[ix] = pool; in mlx5e_xsk_add_pool()
58 static void mlx5e_xsk_remove_pool(struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_remove_pool() argument
60 xsk->pools[ix] = NULL; in mlx5e_xsk_remove_pool()
78 struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_enable_locked() argument
85 if (unlikely(mlx5e_xsk_get_pool(&priv->channels.params, &priv->xsk, ix))) in mlx5e_xsk_enable_locked()
95 err = mlx5e_xsk_add_pool(&priv->xsk, pool, ix); in mlx5e_xsk_enable_locked()
113 c = priv->channels.c[ix]; in mlx5e_xsk_enable_locked()
125 err = mlx5e_rx_res_xsk_activate(priv->rx_res, &priv->channels, ix); in mlx5e_xsk_enable_locked()
136 mlx5e_xsk_remove_pool(&priv->xsk, ix); in mlx5e_xsk_enable_locked()
[all …]
Dpool.h10 struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_get_pool() argument
15 if (unlikely(ix >= params->num_channels)) in mlx5e_xsk_get_pool()
18 return xsk->pools[ix]; in mlx5e_xsk_get_pool()
/drivers/net/ethernet/mellanox/mlx5/core/
Dwq.h82 void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides);
157 static inline void *mlx5_wq_cyc_get_wqe(struct mlx5_wq_cyc *wq, u16 ix) in mlx5_wq_cyc_get_wqe() argument
159 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_cyc_get_wqe()
162 static inline u16 mlx5_wq_cyc_get_contig_wqebbs(struct mlx5_wq_cyc *wq, u16 ix) in mlx5_wq_cyc_get_contig_wqebbs() argument
164 return mlx5_frag_buf_get_idx_last_contig_stride(&wq->fbc, ix) - ix + 1; in mlx5_wq_cyc_get_contig_wqebbs()
200 static inline struct mlx5_cqe64 *mlx5_cqwq_get_wqe(struct mlx5_cqwq *wq, u32 ix) in mlx5_cqwq_get_wqe() argument
202 struct mlx5_cqe64 *cqe = mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_cqwq_get_wqe()
266 static inline void *mlx5_wq_ll_get_wqe(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe() argument
268 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_ll_get_wqe()
271 static inline u16 mlx5_wq_ll_get_wqe_next_ix(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe_next_ix() argument
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Den_fs.c82 int ix = mlx5e_hash_l2(addr); in mlx5e_add_l2_to_hash() local
85 hlist_for_each_entry(hn, &hash[ix], hlist) in mlx5e_add_l2_to_hash()
103 hlist_add_head(&hn->hlist, &hash[ix]); in mlx5e_add_l2_to_hash()
982 int ix = 0; in mlx5e_create_l2_table_groups() local
1003 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5e_create_l2_table_groups()
1004 ix += MLX5E_L2_GROUP1_SIZE; in mlx5e_create_l2_table_groups()
1005 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5e_create_l2_table_groups()
1014 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5e_create_l2_table_groups()
1015 ix += MLX5E_L2_GROUP2_SIZE; in mlx5e_create_l2_table_groups()
1016 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5e_create_l2_table_groups()
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/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_ttc.c291 int ix = 0; in mlx5_create_ttc_table_groups() local
314 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
315 ix += MLX5_TTC_GROUP1_SIZE; in mlx5_create_ttc_table_groups()
316 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
324 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
325 ix += MLX5_TTC_GROUP2_SIZE; in mlx5_create_ttc_table_groups()
326 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
334 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
335 ix += MLX5_TTC_GROUP3_SIZE; in mlx5_create_ttc_table_groups()
336 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
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Dmpfs.c79 static int alloc_l2table_index(struct mlx5_mpfs *l2table, u32 *ix) in alloc_l2table_index() argument
83 *ix = find_first_zero_bit(l2table->bitmap, l2table->size); in alloc_l2table_index()
84 if (*ix >= l2table->size) in alloc_l2table_index()
87 __set_bit(*ix, l2table->bitmap); in alloc_l2table_index()
92 static void free_l2table_index(struct mlx5_mpfs *l2table, u32 ix) in free_l2table_index() argument
94 __clear_bit(ix, l2table->bitmap); in free_l2table_index()
Dmpfs.h53 int ix = MLX5_L2_ADDR_HASH(mac); \
57 hlist_for_each_entry(ptr, &(hash)[ix], node.hlist) \
68 int ix = MLX5_L2_ADDR_HASH(mac); \
74 hlist_add_head(&ptr->node.hlist, &(hash)[ix]);\
/drivers/media/dvb-frontends/
Dmxl692.c205 u32 ix, div_size; in mxl692_checksum() local
212 for (ix = 0; ix < div_size; ix++) in mxl692_checksum()
213 cur_cksum += be32_to_cpu(buf[ix]); in mxl692_checksum()
224 u32 ix, temp; in mxl692_validate_fw_header() local
244 for (ix = 16; ix < buf_len; ix++) in mxl692_validate_fw_header()
245 temp_cksum += buffer[ix]; in mxl692_validate_fw_header()
260 u32 ix = 0, total_len = 0, addr = 0, chunk_len = 0, prevchunk_len = 0; in mxl692_write_fw_block() local
264 ix = *index; in mxl692_write_fw_block()
266 if (buffer[ix] == 0x53) { in mxl692_write_fw_block()
267 total_len = buffer[ix + 1] << 16 | buffer[ix + 2] << 8 | buffer[ix + 3]; in mxl692_write_fw_block()
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/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.h155 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
159 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
167 cgs_write_ind_register(device, port, ix##reg, \
168 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
172 cgs_write_ind_register(device, port, ix##reg, \
173 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
181 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
192 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
206 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
220 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/drivers/input/misc/
Dyealink.c282 int ix, len; in yealink_set_ringtone() local
298 ix = 0; in yealink_set_ringtone()
299 while (size != ix) { in yealink_set_ringtone()
300 len = size - ix; in yealink_set_ringtone()
304 p->offset = cpu_to_be16(ix); in yealink_set_ringtone()
305 memcpy(p->data, &buf[ix], len); in yealink_set_ringtone()
307 ix += len; in yealink_set_ringtone()
317 int i, ix, len; in yealink_do_idle_tasks() local
319 ix = yld->stat_ix; in yealink_do_idle_tasks()
327 if (ix >= sizeof(yld->master)) { in yealink_do_idle_tasks()
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/drivers/net/wireless/marvell/mwifiex/
Dutil.c723 int ix; in mwifiex_hist_data_reset() local
727 for (ix = 0; ix < MWIFIEX_MAX_AC_RX_RATES; ix++) in mwifiex_hist_data_reset()
728 atomic_set(&phist_data->rx_rate[ix], 0); in mwifiex_hist_data_reset()
729 for (ix = 0; ix < MWIFIEX_MAX_SNR; ix++) in mwifiex_hist_data_reset()
730 atomic_set(&phist_data->snr[ix], 0); in mwifiex_hist_data_reset()
731 for (ix = 0; ix < MWIFIEX_MAX_NOISE_FLR; ix++) in mwifiex_hist_data_reset()
732 atomic_set(&phist_data->noise_flr[ix], 0); in mwifiex_hist_data_reset()
733 for (ix = 0; ix < MWIFIEX_MAX_SIG_STRENGTH; ix++) in mwifiex_hist_data_reset()
734 atomic_set(&phist_data->sig_str[ix], 0); in mwifiex_hist_data_reset()
/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dconn.c103 unsigned int ix; in mlx5_fpga_conn_post_recv() local
115 ix = conn->qp.rq.pc & (conn->qp.rq.size - 1); in mlx5_fpga_conn_post_recv()
116 data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix); in mlx5_fpga_conn_post_recv()
122 conn->qp.rq.bufs[ix] = buf; in mlx5_fpga_conn_post_recv()
146 unsigned int ix, sgi; in mlx5_fpga_conn_post_send() local
149 ix = conn->qp.sq.pc & (conn->qp.sq.size - 1); in mlx5_fpga_conn_post_send()
151 ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix); in mlx5_fpga_conn_post_send()
171 conn->qp.sq.bufs[ix] = buf; in mlx5_fpga_conn_post_send()
254 int ix, err; in mlx5_fpga_conn_rq_cqe() local
256 ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.rq.size - 1); in mlx5_fpga_conn_rq_cqe()
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/drivers/gpu/drm/radeon/
Dtrinity_dpm.c545 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_divider_value() local
552 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()
555 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
562 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()
565 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
572 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ds_dividers() local
574 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()
577 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
584 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ss_dividers() local
586 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers()
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/drivers/infiniband/core/
Dcache.c383 struct ib_gid_table *table, int ix) in del_gid() argument
391 ix, table->data_vec[ix]->attr.gid.raw); in del_gid()
394 entry = table->data_vec[ix]; in del_gid()
400 table->data_vec[ix] = NULL; in del_gid()
553 int ix; in __ib_cache_gid_add() local
566 ix = find_gid(table, gid, attr, default_gid, mask, &empty); in __ib_cache_gid_add()
567 if (ix >= 0) in __ib_cache_gid_add()
607 int ix; in _ib_cache_gid_del() local
613 ix = find_gid(table, gid, attr, default_gid, mask, NULL); in _ib_cache_gid_del()
614 if (ix < 0) { in _ib_cache_gid_del()
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/drivers/s390/char/
Dcon3215.c175 int len, count, ix, lines; in raw3215_mk_write_req() local
200 ix = req->start; in raw3215_mk_write_req()
201 while (lines < RAW3215_MAX_NEWLINE && ix != raw->head) { in raw3215_mk_write_req()
202 if (raw->buffer[ix] == 0x15) in raw3215_mk_write_req()
204 ix = (ix + 1) & (RAW3215_BUFFER_SIZE - 1); in raw3215_mk_write_req()
206 len = ((ix - 1 - req->start) & (RAW3215_BUFFER_SIZE - 1)) + 1; in raw3215_mk_write_req()
213 req->delayable = (ix == raw->head) && (len < RAW3215_MIN_WRITE); in raw3215_mk_write_req()
215 ix = req->start; in raw3215_mk_write_req()
222 (__u32) __pa(raw->buffer + ix); in raw3215_mk_write_req()
224 if (ix + count > RAW3215_BUFFER_SIZE) in raw3215_mk_write_req()
[all …]
/drivers/net/ethernet/mscc/
Docelot_vcap.c56 u16 ix, int cmd, int sel) in vcap_cmd() argument
59 VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) | in vcap_cmd()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
174 struct vcap_data *data, int ix) in vcap_data_offset_get() argument
194 col = (ix % num_entries_per_row); in vcap_data_offset_get()
344 static void is2_entry_set(struct ocelot *ocelot, int ix, in is2_entry_set() argument
352 int row = (ix / 2); in is2_entry_set()
363 vcap_data_offset_get(vcap, &data, ix); in is2_entry_set()
668 static void is1_entry_set(struct ocelot *ocelot, int ix, in is1_entry_set() argument
675 int row = ix / 2; in is1_entry_set()
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