| /drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_mailbox.c | 36 int octeon_mbox_read(struct octeon_mbox *mbox) in octeon_mbox_read() argument
41 spin_lock(&mbox->lock); in octeon_mbox_read()
43 msg.u64 = readq(mbox->mbox_read_reg); in octeon_mbox_read()
46 spin_unlock(&mbox->lock); in octeon_mbox_read()
50 if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) { in octeon_mbox_read()
51 mbox->mbox_req.data[mbox->mbox_req.recv_len - 1] = msg.u64; in octeon_mbox_read()
52 mbox->mbox_req.recv_len++; in octeon_mbox_read()
54 if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) { in octeon_mbox_read()
55 mbox->mbox_resp.data[mbox->mbox_resp.recv_len - 1] = in octeon_mbox_read()
57 mbox->mbox_resp.recv_len++; in octeon_mbox_read()
[all …]
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| /drivers/mailbox/ |
| D | mailbox-altera.c | 60 static inline int altera_mbox_full(struct altera_mbox *mbox) in altera_mbox_full() argument
64 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
68 static inline int altera_mbox_pending(struct altera_mbox *mbox) in altera_mbox_pending() argument
72 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
76 static void altera_mbox_rx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_rx_intmask() argument
80 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
85 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
88 static void altera_mbox_tx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_tx_intmask() argument
92 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
97 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
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| D | hi6220-mailbox.c | 89 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
94 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
96 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
99 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
104 mode = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
106 writel(mode, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
112 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_last_tx_done() local
116 BUG_ON(mbox->tx_irq_mode); in hi6220_mbox_last_tx_done()
118 state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); in hi6220_mbox_last_tx_done()
125 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_send_data() local
[all …]
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| D | mailbox-mpfs.c | 73 static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) in mpfs_mbox_busy() argument
77 status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_busy()
84 struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; in mpfs_mbox_last_tx_done() local
86 return !mpfs_mbox_busy(mbox); in mpfs_mbox_last_tx_done()
91 struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; in mpfs_mbox_send_data() local
97 mbox->response = msg->response; in mpfs_mbox_send_data()
98 mbox->resp_offset = msg->resp_offset; in mpfs_mbox_send_data()
100 if (mpfs_mbox_busy(mbox)) in mpfs_mbox_send_data()
110 mbox->mbox_base + msg->mbox_offset + index * 0x4); in mpfs_mbox_send_data()
116 val = readl_relaxed(mbox->mbox_base + msg->mbox_offset + index * 0x4); in mpfs_mbox_send_data()
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| D | sun6i-msgbox.c | 44 #define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__) argument
58 return chan - chan->mbox->chans; in channel_number()
68 struct sun6i_msgbox *mbox = dev_id; in sun6i_msgbox_irq() local
73 status = readl(mbox->regs + LOCAL_IRQ_EN_REG) & in sun6i_msgbox_irq()
74 readl(mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
80 struct mbox_chan *chan = &mbox->controller.chans[n]; in sun6i_msgbox_irq()
86 uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n)); in sun6i_msgbox_irq()
88 mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg); in sun6i_msgbox_irq()
93 writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
101 struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan); in sun6i_msgbox_send_data() local
[all …]
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| D | armada-37xx-rwtm-mailbox.c | 45 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_receive() local
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
59 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_irq_handler() local
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
68 dev_err(mbox->dev, "Secure processor command queue full\n"); in a37xx_mbox_irq_handler()
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
79 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_send_data() local
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); in a37xx_mbox_send_data()
89 dev_warn(mbox->dev, "Secure processor not ready\n"); in a37xx_mbox_send_data()
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| D | omap-mailbox.c | 68 struct omap_mbox *mbox; member
144 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
148 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
151 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write()
155 mbox_write_reg(mbox->parent, msg, fifo->msg); in mbox_fifo_write()
158 static int mbox_fifo_empty(struct omap_mbox *mbox) in mbox_fifo_empty() argument
160 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_empty()
162 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); in mbox_fifo_empty()
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| D | bcm2835-mailbox.c | 63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
68 struct bcm2835_mbox *mbox = dev_id; in bcm2835_mbox_irq() local
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
72 while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { in bcm2835_mbox_irq()
73 u32 msg = readl(mbox->regs + MAIL0_RD); in bcm2835_mbox_irq()
82 struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); in bcm2835_send_data() local
85 spin_lock(&mbox->lock); in bcm2835_send_data()
86 writel(msg, mbox->regs + MAIL1_WRT); in bcm2835_send_data()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
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| D | mailbox.c | 77 err = chan->mbox->ops->send_data(chan, data); in msg_submit()
87 spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags); in msg_submit()
88 hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL); in msg_submit()
89 spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags); in msg_submit()
119 struct mbox_controller *mbox = in txdone_hrtimer() local
125 for (i = 0; i < mbox->num_chans; i++) { in txdone_hrtimer()
126 struct mbox_chan *chan = &mbox->chans[i]; in txdone_hrtimer()
129 txdone = chan->mbox->ops->last_tx_done(chan); in txdone_hrtimer()
138 spin_lock_irqsave(&mbox->poll_hrt_lock, flags); in txdone_hrtimer()
140 hrtimer_forward_now(hrtimer, ms_to_ktime(mbox->txpoll_period)); in txdone_hrtimer()
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| D | hi3660-mailbox.c | 24 #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) argument
81 static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) in to_hi3660_mbox() argument
83 return container_of(mbox, struct hi3660_mbox, controller); in to_hi3660_mbox()
89 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_check_state() local
90 struct hi3660_chan_info *mchan = &mbox->mchan[ch]; in hi3660_mbox_check_state()
91 void __iomem *base = MBOX_BASE(mbox, ch); in hi3660_mbox_check_state()
103 dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); in hi3660_mbox_check_state()
115 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_unlock() local
119 writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
121 val = readl(mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
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| D | arm_mhu_db.c | 42 struct mbox_controller mbox; member
60 mhu_db_mbox_to_channel(struct mbox_controller *mbox, unsigned int pchan, in mhu_db_mbox_to_channel() argument
66 for (i = 0; i < mbox->num_chans; i++) { in mhu_db_mbox_to_channel()
67 chan_info = mbox->chans[i].con_priv; in mhu_db_mbox_to_channel()
70 return &mbox->chans[i]; in mhu_db_mbox_to_channel()
100 struct mbox_controller *mbox = &mhu->mbox; in mhu_db_mbox_irq_to_channel() local
113 chan = mhu_db_mbox_to_channel(mbox, pchan, doorbell); in mhu_db_mbox_irq_to_channel()
116 dev_err(mbox->dev, in mhu_db_mbox_irq_to_channel()
169 struct mbox_controller *mbox = &chan_info->mhu->mbox; in mhu_db_shutdown() local
172 for (i = 0; i < mbox->num_chans; i++) in mhu_db_shutdown()
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| D | mailbox-sti.c | 55 struct mbox_controller *mbox; member
97 struct mbox_chan *sti_mbox_to_channel(struct mbox_controller *mbox, in sti_mbox_to_channel() argument
104 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_to_channel()
105 chan_info = mbox->chans[i].con_priv; in sti_mbox_to_channel()
109 return &mbox->chans[i]; in sti_mbox_to_channel()
112 dev_err(mbox->dev, in sti_mbox_to_channel()
163 struct mbox_controller *mbox = mdev->mbox; in sti_mbox_irq_to_channel() local
179 chan = sti_mbox_to_channel(mbox, instance, channel); in sti_mbox_irq_to_channel()
181 dev_dbg(mbox->dev, in sti_mbox_irq_to_channel()
303 struct mbox_controller *mbox = chan_info->mdev->mbox; in sti_mbox_shutdown_chan() local
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mbox.c | 18 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in __otx2_mbox_reset() argument
20 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in __otx2_mbox_reset()
24 tx_hdr = hw_mbase + mbox->tx_start; in __otx2_mbox_reset()
25 rx_hdr = hw_mbase + mbox->rx_start; in __otx2_mbox_reset()
36 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in otx2_mbox_reset() argument
38 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in otx2_mbox_reset()
41 __otx2_mbox_reset(mbox, devid); in otx2_mbox_reset()
46 void otx2_mbox_destroy(struct otx2_mbox *mbox) in otx2_mbox_destroy() argument
48 mbox->reg_base = NULL; in otx2_mbox_destroy()
49 mbox->hwbase = NULL; in otx2_mbox_destroy()
[all …]
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| /drivers/net/ethernet/marvell/octeontx2/nic/ |
| D | otx2_dmac_flt.c | 17 mutex_lock(&pf->mbox.lock); in otx2_dmacflt_do_add()
19 req = otx2_mbox_alloc_msg_cgx_mac_addr_add(&pf->mbox); in otx2_dmacflt_do_add()
21 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_do_add()
26 err = otx2_sync_mbox_msg(&pf->mbox); in otx2_dmacflt_do_add()
30 otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &req->hdr); in otx2_dmacflt_do_add()
34 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_do_add()
43 mutex_lock(&pf->mbox.lock); in otx2_dmacflt_add_pfmac()
45 req = otx2_mbox_alloc_msg_cgx_mac_addr_set(&pf->mbox); in otx2_dmacflt_add_pfmac()
47 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_add_pfmac()
52 err = otx2_sync_mbox_msg(&pf->mbox); in otx2_dmacflt_add_pfmac()
[all …]
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| D | otx2_vf.c | 91 struct otx2_mbox *mbox; in otx2vf_vfaf_mbox_handler() local
92 struct mbox *af_mbox; in otx2vf_vfaf_mbox_handler()
95 af_mbox = container_of(work, struct mbox, mbox_wrk); in otx2vf_vfaf_mbox_handler()
96 mbox = &af_mbox->mbox; in otx2vf_vfaf_mbox_handler()
97 mdev = &mbox->dev[0]; in otx2vf_vfaf_mbox_handler()
98 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); in otx2vf_vfaf_mbox_handler()
101 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); in otx2vf_vfaf_mbox_handler()
106 offset = mbox->rx_start + msg->next_msgoff; in otx2vf_vfaf_mbox_handler()
108 __otx2_mbox_reset(mbox, 0); in otx2vf_vfaf_mbox_handler()
121 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); in otx2vf_process_mbox_msg_up()
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| D | otx2_pf.c | 107 struct mbox *mbox = &pf->mbox; in otx2_flr_handler() local
113 mutex_lock(&mbox->lock); in otx2_flr_handler()
114 req = otx2_mbox_alloc_msg_vf_flr(mbox); in otx2_flr_handler()
116 mutex_unlock(&mbox->lock); in otx2_flr_handler()
122 if (!otx2_sync_mbox_msg(&pf->mbox)) { in otx2_flr_handler()
132 mutex_unlock(&mbox->lock); in otx2_flr_handler()
286 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, in otx2_queue_work()
290 struct otx2_mbox *mbox; in otx2_queue_work() local
299 mbox = &mw->mbox; in otx2_queue_work()
300 mdev = &mbox->dev[i]; in otx2_queue_work()
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| D | otx2_common.c | 50 mutex_lock(&pfvf->mbox.lock); in otx2_update_lmac_stats()
51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); in otx2_update_lmac_stats()
53 mutex_unlock(&pfvf->mbox.lock); in otx2_update_lmac_stats()
57 otx2_sync_mbox_msg(&pfvf->mbox); in otx2_update_lmac_stats()
58 mutex_unlock(&pfvf->mbox.lock); in otx2_update_lmac_stats()
67 mutex_lock(&pfvf->mbox.lock); in otx2_update_lmac_fec_stats()
68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); in otx2_update_lmac_fec_stats()
70 otx2_sync_mbox_msg(&pfvf->mbox); in otx2_update_lmac_fec_stats()
71 mutex_unlock(&pfvf->mbox.lock); in otx2_update_lmac_fec_stats()
150 mutex_lock(&pfvf->mbox.lock); in otx2_hw_set_mac_addr()
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| D | otx2_common.h | 157 struct mbox { struct
158 struct otx2_mbox mbox; member
348 struct mbox mbox; member
349 struct mbox *mbox_pfvf;
498 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) in otx2_mbox_bbuf_init() argument
503 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); in otx2_mbox_bbuf_init()
504 if (!mbox->bbuf_base) in otx2_mbox_bbuf_init()
511 otx2_mbox = &mbox->mbox; in otx2_mbox_bbuf_init()
513 mdev->mbase = mbox->bbuf_base; in otx2_mbox_bbuf_init()
515 otx2_mbox = &mbox->mbox_up; in otx2_mbox_bbuf_init()
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| /drivers/crypto/marvell/octeontx2/ |
| D | otx2_cpt_mbox_common.c | 7 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_mbox_msg() argument
11 otx2_mbox_msg_send(mbox, 0); in otx2_cpt_send_mbox_msg()
12 ret = otx2_mbox_wait_for_rsp(mbox, 0); in otx2_cpt_send_mbox_msg()
23 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_ready_msg() argument
27 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), in otx2_cpt_send_ready_msg()
37 return otx2_cpt_send_mbox_msg(mbox, pdev); in otx2_cpt_send_ready_msg()
40 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_af_reg_requests() argument
42 return otx2_cpt_send_mbox_msg(mbox, pdev); in otx2_cpt_send_af_reg_requests()
45 int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, in otx2_cpt_add_read_af_reg() argument
51 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg), in otx2_cpt_add_read_af_reg()
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| /drivers/net/wireless/ti/wl18xx/ |
| D | event.c | 118 struct wl18xx_event_mailbox *mbox = wl->mbox; in wl18xx_process_mailbox_events() local
121 vector = le32_to_cpu(mbox->events_vector); in wl18xx_process_mailbox_events()
126 mbox->number_of_scan_results); in wl18xx_process_mailbox_events()
134 mbox->time_sync_tsf_high_msb, in wl18xx_process_mailbox_events()
135 mbox->time_sync_tsf_high_lsb, in wl18xx_process_mailbox_events()
136 mbox->time_sync_tsf_low_msb, in wl18xx_process_mailbox_events()
137 mbox->time_sync_tsf_low_lsb); in wl18xx_process_mailbox_events()
141 mbox->radar_channel, in wl18xx_process_mailbox_events()
142 wl18xx_radar_type_decode(mbox->radar_type)); in wl18xx_process_mailbox_events()
151 mbox->number_of_sched_scan_results); in wl18xx_process_mailbox_events()
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| /drivers/rapidio/devices/ |
| D | tsi721.c | 614 int mbox; in tsi721_omsg_msix() local
616 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX; in tsi721_omsg_msix()
617 tsi721_omsg_handler(priv, mbox); in tsi721_omsg_msix()
631 int mbox; in tsi721_imsg_msix() local
633 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX; in tsi721_imsg_msix()
634 tsi721_imsg_handler(priv, mbox + 4); in tsi721_imsg_msix()
1667 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, in tsi721_add_outb_message() argument
1675 if (!priv->omsg_init[mbox] || in tsi721_add_outb_message()
1679 spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags); in tsi721_add_outb_message()
1681 tx_slot = priv->omsg_ring[mbox].tx_slot; in tsi721_add_outb_message()
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | pci.c | 284 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, in mlxsw_pci_sdq_init() argument
300 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); in mlxsw_pci_sdq_init()
301 mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp); in mlxsw_pci_sdq_init()
302 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); in mlxsw_pci_sdq_init()
303 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ in mlxsw_pci_sdq_init()
307 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); in mlxsw_pci_sdq_init()
310 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); in mlxsw_pci_sdq_init()
390 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, in mlxsw_pci_rdq_init() argument
404 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); in mlxsw_pci_rdq_init()
405 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ in mlxsw_pci_rdq_init()
[all …]
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| /drivers/scsi/ |
| D | myrs.c | 95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd() local
97 memset(mbox, 0, sizeof(union myrs_cmd_mbox)); in myrs_reset_cmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd() local
110 cs->write_cmd_mbox(next_mbox, mbox); in myrs_qcmd()
161 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_get_ctlr_info() local
179 mbox->ctlr_info.id = MYRS_DCMD_TAG; in myrs_get_ctlr_info()
180 mbox->ctlr_info.opcode = MYRS_CMD_OP_IOCTL; in myrs_get_ctlr_info()
181 mbox->ctlr_info.control.dma_ctrl_to_host = true; in myrs_get_ctlr_info()
182 mbox->ctlr_info.control.no_autosense = true; in myrs_get_ctlr_info()
183 mbox->ctlr_info.dma_size = sizeof(struct myrs_ctlr_info); in myrs_get_ctlr_info()
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| /drivers/net/wireless/ti/wl12xx/ |
| D | event.c | 36 struct wl12xx_event_mailbox *mbox = wl->mbox; in wl12xx_process_mailbox_events() local
40 vector = le32_to_cpu(mbox->events_vector); in wl12xx_process_mailbox_events()
41 vector &= ~(le32_to_cpu(mbox->events_mask)); in wl12xx_process_mailbox_events()
47 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
56 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
63 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
66 mbox->soft_gemini_sense_info); in wl12xx_process_mailbox_events()
72 wlcore_event_rssi_trigger(wl, mbox->rssi_snr_trigger_metric); in wl12xx_process_mailbox_events()
76 BIT(mbox->role_id), in wl12xx_process_mailbox_events()
77 mbox->rx_ba_allowed); in wl12xx_process_mailbox_events()
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| /drivers/scsi/lpfc/ |
| D | lpfc_mbox.c | 847 LPFC_MBOXQ_t *mbox; in lpfc_sli4_unreg_all_rpis() local
850 mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); in lpfc_sli4_unreg_all_rpis()
851 if (mbox) { in lpfc_sli4_unreg_all_rpis()
860 mbox); in lpfc_sli4_unreg_all_rpis()
861 mbox->u.mb.un.varUnregLogin.rsvd1 = 0x4000; in lpfc_sli4_unreg_all_rpis()
862 mbox->vport = vport; in lpfc_sli4_unreg_all_rpis()
863 mbox->mbox_cmpl = lpfc_sli_def_mbox_cmpl; in lpfc_sli4_unreg_all_rpis()
864 mbox->ctx_ndlp = NULL; in lpfc_sli4_unreg_all_rpis()
865 rc = lpfc_sli_issue_mbox(phba, mbox, MBX_NOWAIT); in lpfc_sli4_unreg_all_rpis()
867 mempool_free(mbox, phba->mbox_mem_pool); in lpfc_sli4_unreg_all_rpis()
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