1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <net/tso.h>
11
12 #include "otx2_reg.h"
13 #include "otx2_common.h"
14 #include "otx2_struct.h"
15 #include "cn10k.h"
16
otx2_nix_rq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)17 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
18 struct otx2_nic *pfvf, int qidx)
19 {
20 u64 incr = (u64)qidx << 32;
21 u64 *ptr;
22
23 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
24 stats->bytes = otx2_atomic64_add(incr, ptr);
25
26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
27 stats->pkts = otx2_atomic64_add(incr, ptr);
28 }
29
otx2_nix_sq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)30 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
31 struct otx2_nic *pfvf, int qidx)
32 {
33 u64 incr = (u64)qidx << 32;
34 u64 *ptr;
35
36 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
37 stats->bytes = otx2_atomic64_add(incr, ptr);
38
39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
40 stats->pkts = otx2_atomic64_add(incr, ptr);
41 }
42
otx2_update_lmac_stats(struct otx2_nic * pfvf)43 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
44 {
45 struct msg_req *req;
46
47 if (!netif_running(pfvf->netdev))
48 return;
49
50 mutex_lock(&pfvf->mbox.lock);
51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
52 if (!req) {
53 mutex_unlock(&pfvf->mbox.lock);
54 return;
55 }
56
57 otx2_sync_mbox_msg(&pfvf->mbox);
58 mutex_unlock(&pfvf->mbox.lock);
59 }
60
otx2_update_lmac_fec_stats(struct otx2_nic * pfvf)61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
62 {
63 struct msg_req *req;
64
65 if (!netif_running(pfvf->netdev))
66 return;
67 mutex_lock(&pfvf->mbox.lock);
68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
69 if (req)
70 otx2_sync_mbox_msg(&pfvf->mbox);
71 mutex_unlock(&pfvf->mbox.lock);
72 }
73
otx2_update_rq_stats(struct otx2_nic * pfvf,int qidx)74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
75 {
76 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
77
78 if (!pfvf->qset.rq)
79 return 0;
80
81 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
82 return 1;
83 }
84
otx2_update_sq_stats(struct otx2_nic * pfvf,int qidx)85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
86 {
87 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
88
89 if (!pfvf->qset.sq)
90 return 0;
91
92 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
93 return 1;
94 }
95
otx2_get_dev_stats(struct otx2_nic * pfvf)96 void otx2_get_dev_stats(struct otx2_nic *pfvf)
97 {
98 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
99
100 #define OTX2_GET_RX_STATS(reg) \
101 otx2_read64(pfvf, NIX_LF_RX_STATX(reg))
102 #define OTX2_GET_TX_STATS(reg) \
103 otx2_read64(pfvf, NIX_LF_TX_STATX(reg))
104
105 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
106 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
107 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
108 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
109 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
110 dev_stats->rx_frames = dev_stats->rx_bcast_frames +
111 dev_stats->rx_mcast_frames +
112 dev_stats->rx_ucast_frames;
113
114 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
115 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
116 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
117 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
118 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
119 dev_stats->tx_frames = dev_stats->tx_bcast_frames +
120 dev_stats->tx_mcast_frames +
121 dev_stats->tx_ucast_frames;
122 }
123
otx2_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)124 void otx2_get_stats64(struct net_device *netdev,
125 struct rtnl_link_stats64 *stats)
126 {
127 struct otx2_nic *pfvf = netdev_priv(netdev);
128 struct otx2_dev_stats *dev_stats;
129
130 otx2_get_dev_stats(pfvf);
131
132 dev_stats = &pfvf->hw.dev_stats;
133 stats->rx_bytes = dev_stats->rx_bytes;
134 stats->rx_packets = dev_stats->rx_frames;
135 stats->rx_dropped = dev_stats->rx_drops;
136 stats->multicast = dev_stats->rx_mcast_frames;
137
138 stats->tx_bytes = dev_stats->tx_bytes;
139 stats->tx_packets = dev_stats->tx_frames;
140 stats->tx_dropped = dev_stats->tx_drops;
141 }
142 EXPORT_SYMBOL(otx2_get_stats64);
143
144 /* Sync MAC address with RVU AF */
otx2_hw_set_mac_addr(struct otx2_nic * pfvf,u8 * mac)145 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
146 {
147 struct nix_set_mac_addr *req;
148 int err;
149
150 mutex_lock(&pfvf->mbox.lock);
151 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
152 if (!req) {
153 mutex_unlock(&pfvf->mbox.lock);
154 return -ENOMEM;
155 }
156
157 ether_addr_copy(req->mac_addr, mac);
158
159 err = otx2_sync_mbox_msg(&pfvf->mbox);
160 mutex_unlock(&pfvf->mbox.lock);
161 return err;
162 }
163
otx2_hw_get_mac_addr(struct otx2_nic * pfvf,struct net_device * netdev)164 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
165 struct net_device *netdev)
166 {
167 struct nix_get_mac_addr_rsp *rsp;
168 struct mbox_msghdr *msghdr;
169 struct msg_req *req;
170 int err;
171
172 mutex_lock(&pfvf->mbox.lock);
173 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
174 if (!req) {
175 mutex_unlock(&pfvf->mbox.lock);
176 return -ENOMEM;
177 }
178
179 err = otx2_sync_mbox_msg(&pfvf->mbox);
180 if (err) {
181 mutex_unlock(&pfvf->mbox.lock);
182 return err;
183 }
184
185 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
186 if (IS_ERR(msghdr)) {
187 mutex_unlock(&pfvf->mbox.lock);
188 return PTR_ERR(msghdr);
189 }
190 rsp = (struct nix_get_mac_addr_rsp *)msghdr;
191 eth_hw_addr_set(netdev, rsp->mac_addr);
192 mutex_unlock(&pfvf->mbox.lock);
193
194 return 0;
195 }
196
otx2_set_mac_address(struct net_device * netdev,void * p)197 int otx2_set_mac_address(struct net_device *netdev, void *p)
198 {
199 struct otx2_nic *pfvf = netdev_priv(netdev);
200 struct sockaddr *addr = p;
201
202 if (!is_valid_ether_addr(addr->sa_data))
203 return -EADDRNOTAVAIL;
204
205 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
206 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
207 /* update dmac field in vlan offload rule */
208 if (netif_running(netdev) &&
209 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
210 otx2_install_rxvlan_offload_flow(pfvf);
211 /* update dmac address in ntuple and DMAC filter list */
212 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
213 otx2_dmacflt_update_pfmac_flow(pfvf);
214 } else {
215 return -EPERM;
216 }
217
218 return 0;
219 }
220 EXPORT_SYMBOL(otx2_set_mac_address);
221
otx2_hw_set_mtu(struct otx2_nic * pfvf,int mtu)222 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
223 {
224 struct nix_frs_cfg *req;
225 int err;
226
227 mutex_lock(&pfvf->mbox.lock);
228 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
229 if (!req) {
230 mutex_unlock(&pfvf->mbox.lock);
231 return -ENOMEM;
232 }
233
234 req->maxlen = pfvf->max_frs;
235
236 err = otx2_sync_mbox_msg(&pfvf->mbox);
237 mutex_unlock(&pfvf->mbox.lock);
238 return err;
239 }
240
otx2_config_pause_frm(struct otx2_nic * pfvf)241 int otx2_config_pause_frm(struct otx2_nic *pfvf)
242 {
243 struct cgx_pause_frm_cfg *req;
244 int err;
245
246 if (is_otx2_lbkvf(pfvf->pdev))
247 return 0;
248
249 mutex_lock(&pfvf->mbox.lock);
250 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
251 if (!req) {
252 err = -ENOMEM;
253 goto unlock;
254 }
255
256 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
257 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
258 req->set = 1;
259
260 err = otx2_sync_mbox_msg(&pfvf->mbox);
261 unlock:
262 mutex_unlock(&pfvf->mbox.lock);
263 return err;
264 }
265 EXPORT_SYMBOL(otx2_config_pause_frm);
266
otx2_set_flowkey_cfg(struct otx2_nic * pfvf)267 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
268 {
269 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
270 struct nix_rss_flowkey_cfg_rsp *rsp;
271 struct nix_rss_flowkey_cfg *req;
272 int err;
273
274 mutex_lock(&pfvf->mbox.lock);
275 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
276 if (!req) {
277 mutex_unlock(&pfvf->mbox.lock);
278 return -ENOMEM;
279 }
280 req->mcam_index = -1; /* Default or reserved index */
281 req->flowkey_cfg = rss->flowkey_cfg;
282 req->group = DEFAULT_RSS_CONTEXT_GROUP;
283
284 err = otx2_sync_mbox_msg(&pfvf->mbox);
285 if (err)
286 goto fail;
287
288 rsp = (struct nix_rss_flowkey_cfg_rsp *)
289 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
290 if (IS_ERR(rsp)) {
291 err = PTR_ERR(rsp);
292 goto fail;
293 }
294
295 pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
296 fail:
297 mutex_unlock(&pfvf->mbox.lock);
298 return err;
299 }
300
otx2_set_rss_table(struct otx2_nic * pfvf,int ctx_id)301 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
302 {
303 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
304 const int index = rss->rss_size * ctx_id;
305 struct mbox *mbox = &pfvf->mbox;
306 struct otx2_rss_ctx *rss_ctx;
307 struct nix_aq_enq_req *aq;
308 int idx, err;
309
310 mutex_lock(&mbox->lock);
311 rss_ctx = rss->rss_ctx[ctx_id];
312 /* Get memory to put this msg */
313 for (idx = 0; idx < rss->rss_size; idx++) {
314 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
315 if (!aq) {
316 /* The shared memory buffer can be full.
317 * Flush it and retry
318 */
319 err = otx2_sync_mbox_msg(mbox);
320 if (err) {
321 mutex_unlock(&mbox->lock);
322 return err;
323 }
324 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
325 if (!aq) {
326 mutex_unlock(&mbox->lock);
327 return -ENOMEM;
328 }
329 }
330
331 aq->rss.rq = rss_ctx->ind_tbl[idx];
332
333 /* Fill AQ info */
334 aq->qidx = index + idx;
335 aq->ctype = NIX_AQ_CTYPE_RSS;
336 aq->op = NIX_AQ_INSTOP_INIT;
337 }
338 err = otx2_sync_mbox_msg(mbox);
339 mutex_unlock(&mbox->lock);
340 return err;
341 }
342
otx2_set_rss_key(struct otx2_nic * pfvf)343 void otx2_set_rss_key(struct otx2_nic *pfvf)
344 {
345 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
346 u64 *key = (u64 *)&rss->key[4];
347 int idx;
348
349 /* 352bit or 44byte key needs to be configured as below
350 * NIX_LF_RX_SECRETX0 = key<351:288>
351 * NIX_LF_RX_SECRETX1 = key<287:224>
352 * NIX_LF_RX_SECRETX2 = key<223:160>
353 * NIX_LF_RX_SECRETX3 = key<159:96>
354 * NIX_LF_RX_SECRETX4 = key<95:32>
355 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
356 */
357 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
358 (u64)(*((u32 *)&rss->key)) << 32);
359 idx = sizeof(rss->key) / sizeof(u64);
360 while (idx > 0) {
361 idx--;
362 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
363 }
364 }
365
otx2_rss_init(struct otx2_nic * pfvf)366 int otx2_rss_init(struct otx2_nic *pfvf)
367 {
368 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
369 struct otx2_rss_ctx *rss_ctx;
370 int idx, ret = 0;
371
372 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
373
374 /* Init RSS key if it is not setup already */
375 if (!rss->enable)
376 netdev_rss_key_fill(rss->key, sizeof(rss->key));
377 otx2_set_rss_key(pfvf);
378
379 if (!netif_is_rxfh_configured(pfvf->netdev)) {
380 /* Set RSS group 0 as default indirection table */
381 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
382 GFP_KERNEL);
383 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
384 return -ENOMEM;
385
386 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
387 for (idx = 0; idx < rss->rss_size; idx++)
388 rss_ctx->ind_tbl[idx] =
389 ethtool_rxfh_indir_default(idx,
390 pfvf->hw.rx_queues);
391 }
392 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
393 if (ret)
394 return ret;
395
396 /* Flowkey or hash config to be used for generating flow tag */
397 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
398 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
399 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
400 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
401 NIX_FLOW_KEY_TYPE_IPV4_PROTO;
402
403 ret = otx2_set_flowkey_cfg(pfvf);
404 if (ret)
405 return ret;
406
407 rss->enable = true;
408 return 0;
409 }
410
411 /* Setup UDP segmentation algorithm in HW */
otx2_setup_udp_segmentation(struct nix_lso_format_cfg * lso,bool v4)412 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
413 {
414 struct nix_lso_format *field;
415
416 field = (struct nix_lso_format *)&lso->fields[0];
417 lso->field_mask = GENMASK(18, 0);
418
419 /* IP's Length field */
420 field->layer = NIX_TXLAYER_OL3;
421 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
422 field->offset = v4 ? 2 : 4;
423 field->sizem1 = 1; /* i.e 2 bytes */
424 field->alg = NIX_LSOALG_ADD_PAYLEN;
425 field++;
426
427 /* No ID field in IPv6 header */
428 if (v4) {
429 /* Increment IPID */
430 field->layer = NIX_TXLAYER_OL3;
431 field->offset = 4;
432 field->sizem1 = 1; /* i.e 2 bytes */
433 field->alg = NIX_LSOALG_ADD_SEGNUM;
434 field++;
435 }
436
437 /* Update length in UDP header */
438 field->layer = NIX_TXLAYER_OL4;
439 field->offset = 4;
440 field->sizem1 = 1;
441 field->alg = NIX_LSOALG_ADD_PAYLEN;
442 }
443
444 /* Setup segmentation algorithms in HW and retrieve algorithm index */
otx2_setup_segmentation(struct otx2_nic * pfvf)445 void otx2_setup_segmentation(struct otx2_nic *pfvf)
446 {
447 struct nix_lso_format_cfg_rsp *rsp;
448 struct nix_lso_format_cfg *lso;
449 struct otx2_hw *hw = &pfvf->hw;
450 int err;
451
452 mutex_lock(&pfvf->mbox.lock);
453
454 /* UDPv4 segmentation */
455 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
456 if (!lso)
457 goto fail;
458
459 /* Setup UDP/IP header fields that HW should update per segment */
460 otx2_setup_udp_segmentation(lso, true);
461
462 err = otx2_sync_mbox_msg(&pfvf->mbox);
463 if (err)
464 goto fail;
465
466 rsp = (struct nix_lso_format_cfg_rsp *)
467 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
468 if (IS_ERR(rsp))
469 goto fail;
470
471 hw->lso_udpv4_idx = rsp->lso_format_idx;
472
473 /* UDPv6 segmentation */
474 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
475 if (!lso)
476 goto fail;
477
478 /* Setup UDP/IP header fields that HW should update per segment */
479 otx2_setup_udp_segmentation(lso, false);
480
481 err = otx2_sync_mbox_msg(&pfvf->mbox);
482 if (err)
483 goto fail;
484
485 rsp = (struct nix_lso_format_cfg_rsp *)
486 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
487 if (IS_ERR(rsp))
488 goto fail;
489
490 hw->lso_udpv6_idx = rsp->lso_format_idx;
491 mutex_unlock(&pfvf->mbox.lock);
492 return;
493 fail:
494 mutex_unlock(&pfvf->mbox.lock);
495 netdev_info(pfvf->netdev,
496 "Failed to get LSO index for UDP GSO offload, disabling\n");
497 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
498 }
499
otx2_config_irq_coalescing(struct otx2_nic * pfvf,int qidx)500 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
501 {
502 /* Configure CQE interrupt coalescing parameters
503 *
504 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
505 * set 1 less than cq_ecount_wait. And cq_time_wait is in
506 * usecs, convert that to 100ns count.
507 */
508 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
509 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
510 ((u64)pfvf->hw.cq_qcount_wait << 32) |
511 (pfvf->hw.cq_ecount_wait - 1));
512 }
513
__otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)514 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
515 dma_addr_t *dma)
516 {
517 u8 *buf;
518
519 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
520 if (unlikely(!buf))
521 return -ENOMEM;
522
523 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
524 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
525 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
526 page_frag_free(buf);
527 return -ENOMEM;
528 }
529
530 return 0;
531 }
532
otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)533 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
534 dma_addr_t *dma)
535 {
536 int ret;
537
538 local_bh_disable();
539 ret = __otx2_alloc_rbuf(pfvf, pool, dma);
540 local_bh_enable();
541 return ret;
542 }
543
otx2_alloc_buffer(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,dma_addr_t * dma)544 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
545 dma_addr_t *dma)
546 {
547 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) {
548 struct refill_work *work;
549 struct delayed_work *dwork;
550
551 work = &pfvf->refill_wrk[cq->cq_idx];
552 dwork = &work->pool_refill_work;
553 /* Schedule a task if no other task is running */
554 if (!cq->refill_task_sched) {
555 cq->refill_task_sched = true;
556 schedule_delayed_work(dwork,
557 msecs_to_jiffies(100));
558 }
559 return -ENOMEM;
560 }
561 return 0;
562 }
563
otx2_tx_timeout(struct net_device * netdev,unsigned int txq)564 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
565 {
566 struct otx2_nic *pfvf = netdev_priv(netdev);
567
568 schedule_work(&pfvf->reset_task);
569 }
570 EXPORT_SYMBOL(otx2_tx_timeout);
571
otx2_get_mac_from_af(struct net_device * netdev)572 void otx2_get_mac_from_af(struct net_device *netdev)
573 {
574 struct otx2_nic *pfvf = netdev_priv(netdev);
575 int err;
576
577 err = otx2_hw_get_mac_addr(pfvf, netdev);
578 if (err)
579 dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
580
581 /* If AF doesn't provide a valid MAC, generate a random one */
582 if (!is_valid_ether_addr(netdev->dev_addr))
583 eth_hw_addr_random(netdev);
584 }
585 EXPORT_SYMBOL(otx2_get_mac_from_af);
586
otx2_txschq_config(struct otx2_nic * pfvf,int lvl)587 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl)
588 {
589 struct otx2_hw *hw = &pfvf->hw;
590 struct nix_txschq_config *req;
591 u64 schq, parent;
592 u64 dwrr_val;
593
594 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->max_frs);
595
596 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
597 if (!req)
598 return -ENOMEM;
599
600 req->lvl = lvl;
601 req->num_regs = 1;
602
603 schq = hw->txschq_list[lvl][0];
604 /* Set topology e.t.c configuration */
605 if (lvl == NIX_TXSCH_LVL_SMQ) {
606 req->reg[0] = NIX_AF_SMQX_CFG(schq);
607 req->regval[0] = ((pfvf->netdev->max_mtu + OTX2_ETH_HLEN) << 8)
608 | OTX2_MIN_MTU;
609
610 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
611 (0x2ULL << 36);
612 req->num_regs++;
613 /* MDQ config */
614 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0];
615 req->reg[1] = NIX_AF_MDQX_PARENT(schq);
616 req->regval[1] = parent << 16;
617 req->num_regs++;
618 /* Set DWRR quantum */
619 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
620 req->regval[2] = dwrr_val;
621 } else if (lvl == NIX_TXSCH_LVL_TL4) {
622 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0];
623 req->reg[0] = NIX_AF_TL4X_PARENT(schq);
624 req->regval[0] = parent << 16;
625 req->num_regs++;
626 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
627 req->regval[1] = dwrr_val;
628 } else if (lvl == NIX_TXSCH_LVL_TL3) {
629 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0];
630 req->reg[0] = NIX_AF_TL3X_PARENT(schq);
631 req->regval[0] = parent << 16;
632 req->num_regs++;
633 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
634 req->regval[1] = dwrr_val;
635 if (lvl == hw->txschq_link_cfg_lvl) {
636 req->num_regs++;
637 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
638 /* Enable this queue and backpressure */
639 req->regval[2] = BIT_ULL(13) | BIT_ULL(12);
640 }
641 } else if (lvl == NIX_TXSCH_LVL_TL2) {
642 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0];
643 req->reg[0] = NIX_AF_TL2X_PARENT(schq);
644 req->regval[0] = parent << 16;
645
646 req->num_regs++;
647 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
648 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
649
650 if (lvl == hw->txschq_link_cfg_lvl) {
651 req->num_regs++;
652 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
653 /* Enable this queue and backpressure */
654 req->regval[2] = BIT_ULL(13) | BIT_ULL(12);
655 }
656 } else if (lvl == NIX_TXSCH_LVL_TL1) {
657 /* Default config for TL1.
658 * For VF this is always ignored.
659 */
660
661 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will
662 * clip it to 16384, so configuring a 24bit max value
663 * will work on both OTx2 and CN10K.
664 */
665 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
666 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
667
668 req->num_regs++;
669 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
670 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
671
672 req->num_regs++;
673 req->reg[2] = NIX_AF_TL1X_CIR(schq);
674 req->regval[2] = 0;
675 }
676
677 return otx2_sync_mbox_msg(&pfvf->mbox);
678 }
679
otx2_txsch_alloc(struct otx2_nic * pfvf)680 int otx2_txsch_alloc(struct otx2_nic *pfvf)
681 {
682 struct nix_txsch_alloc_req *req;
683 int lvl;
684
685 /* Get memory to put this msg */
686 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
687 if (!req)
688 return -ENOMEM;
689
690 /* Request one schq per level */
691 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
692 req->schq[lvl] = 1;
693
694 return otx2_sync_mbox_msg(&pfvf->mbox);
695 }
696
otx2_txschq_stop(struct otx2_nic * pfvf)697 int otx2_txschq_stop(struct otx2_nic *pfvf)
698 {
699 struct nix_txsch_free_req *free_req;
700 int lvl, schq, err;
701
702 mutex_lock(&pfvf->mbox.lock);
703 /* Free the transmit schedulers */
704 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
705 if (!free_req) {
706 mutex_unlock(&pfvf->mbox.lock);
707 return -ENOMEM;
708 }
709
710 free_req->flags = TXSCHQ_FREE_ALL;
711 err = otx2_sync_mbox_msg(&pfvf->mbox);
712 mutex_unlock(&pfvf->mbox.lock);
713
714 /* Clear the txschq list */
715 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
716 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
717 pfvf->hw.txschq_list[lvl][schq] = 0;
718 }
719 return err;
720 }
721
otx2_sqb_flush(struct otx2_nic * pfvf)722 void otx2_sqb_flush(struct otx2_nic *pfvf)
723 {
724 int qidx, sqe_tail, sqe_head;
725 u64 incr, *ptr, val;
726 int timeout = 1000;
727
728 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
729 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) {
730 incr = (u64)qidx << 32;
731 while (timeout) {
732 val = otx2_atomic64_add(incr, ptr);
733 sqe_head = (val >> 20) & 0x3F;
734 sqe_tail = (val >> 28) & 0x3F;
735 if (sqe_head == sqe_tail)
736 break;
737 usleep_range(1, 3);
738 timeout--;
739 }
740 }
741 }
742
743 /* RED and drop levels of CQ on packet reception.
744 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
745 */
746 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize))
747 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize))
748
749 /* RED and drop levels of AURA for packet reception.
750 * For AURA level is measure of fullness (0x0 = empty, 255 = full).
751 * Eg: For RQ length 1K, for pass/drop level 204/230.
752 * RED accepts pkts if free pointers > 102 & <= 205.
753 * Drops pkts if free pointers < 102.
754 */
755 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */
756 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
757 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
758
otx2_rq_init(struct otx2_nic * pfvf,u16 qidx,u16 lpb_aura)759 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
760 {
761 struct otx2_qset *qset = &pfvf->qset;
762 struct nix_aq_enq_req *aq;
763
764 /* Get memory to put this msg */
765 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
766 if (!aq)
767 return -ENOMEM;
768
769 aq->rq.cq = qidx;
770 aq->rq.ena = 1;
771 aq->rq.pb_caching = 1;
772 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
773 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
774 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
775 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
776 aq->rq.qint_idx = 0;
777 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
778 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
779 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
780 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
781 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
782 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
783
784 /* Fill AQ info */
785 aq->qidx = qidx;
786 aq->ctype = NIX_AQ_CTYPE_RQ;
787 aq->op = NIX_AQ_INSTOP_INIT;
788
789 return otx2_sync_mbox_msg(&pfvf->mbox);
790 }
791
otx2_sq_aq_init(void * dev,u16 qidx,u16 sqb_aura)792 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
793 {
794 struct otx2_nic *pfvf = dev;
795 struct otx2_snd_queue *sq;
796 struct nix_aq_enq_req *aq;
797
798 sq = &pfvf->qset.sq[qidx];
799 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
800 /* Get memory to put this msg */
801 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
802 if (!aq)
803 return -ENOMEM;
804
805 aq->sq.cq = pfvf->hw.rx_queues + qidx;
806 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
807 aq->sq.cq_ena = 1;
808 aq->sq.ena = 1;
809 /* Only one SMQ is allocated, map all SQ's to that SMQ */
810 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
811 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->max_frs);
812 aq->sq.default_chan = pfvf->hw.tx_chan_base;
813 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
814 aq->sq.sqb_aura = sqb_aura;
815 aq->sq.sq_int_ena = NIX_SQINT_BITS;
816 aq->sq.qint_idx = 0;
817 /* Due pipelining impact minimum 2000 unused SQ CQE's
818 * need to maintain to avoid CQ overflow.
819 */
820 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
821
822 /* Fill AQ info */
823 aq->qidx = qidx;
824 aq->ctype = NIX_AQ_CTYPE_SQ;
825 aq->op = NIX_AQ_INSTOP_INIT;
826
827 return otx2_sync_mbox_msg(&pfvf->mbox);
828 }
829
otx2_sq_init(struct otx2_nic * pfvf,u16 qidx,u16 sqb_aura)830 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
831 {
832 struct otx2_qset *qset = &pfvf->qset;
833 struct otx2_snd_queue *sq;
834 struct otx2_pool *pool;
835 int err;
836
837 pool = &pfvf->qset.pool[sqb_aura];
838 sq = &qset->sq[qidx];
839 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
840 sq->sqe_cnt = qset->sqe_cnt;
841
842 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
843 if (err)
844 return err;
845
846 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
847 TSO_HEADER_SIZE);
848 if (err)
849 return err;
850
851 sq->sqe_base = sq->sqe->base;
852 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
853 if (!sq->sg)
854 return -ENOMEM;
855
856 if (pfvf->ptp) {
857 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
858 sizeof(*sq->timestamps));
859 if (err) {
860 kfree(sq->sg);
861 sq->sg = NULL;
862 return err;
863 }
864 }
865
866 sq->head = 0;
867 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
868 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
869 /* Set SQE threshold to 10% of total SQEs */
870 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
871 sq->aura_id = sqb_aura;
872 sq->aura_fc_addr = pool->fc_addr->base;
873 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
874
875 sq->stats.bytes = 0;
876 sq->stats.pkts = 0;
877
878 err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
879 if (err) {
880 kfree(sq->sg);
881 sq->sg = NULL;
882 return err;
883 }
884
885 return 0;
886
887 }
888
otx2_cq_init(struct otx2_nic * pfvf,u16 qidx)889 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
890 {
891 struct otx2_qset *qset = &pfvf->qset;
892 struct nix_aq_enq_req *aq;
893 struct otx2_cq_queue *cq;
894 int err, pool_id;
895
896 cq = &qset->cq[qidx];
897 cq->cq_idx = qidx;
898 if (qidx < pfvf->hw.rx_queues) {
899 cq->cq_type = CQ_RX;
900 cq->cint_idx = qidx;
901 cq->cqe_cnt = qset->rqe_cnt;
902 } else {
903 cq->cq_type = CQ_TX;
904 cq->cint_idx = qidx - pfvf->hw.rx_queues;
905 cq->cqe_cnt = qset->sqe_cnt;
906 }
907 cq->cqe_size = pfvf->qset.xqe_size;
908
909 /* Allocate memory for CQEs */
910 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
911 if (err)
912 return err;
913
914 /* Save CQE CPU base for faster reference */
915 cq->cqe_base = cq->cqe->base;
916 /* In case where all RQs auras point to single pool,
917 * all CQs receive buffer pool also point to same pool.
918 */
919 pool_id = ((cq->cq_type == CQ_RX) &&
920 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
921 cq->rbpool = &qset->pool[pool_id];
922 cq->refill_task_sched = false;
923
924 /* Get memory to put this msg */
925 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
926 if (!aq)
927 return -ENOMEM;
928
929 aq->cq.ena = 1;
930 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
931 aq->cq.caching = 1;
932 aq->cq.base = cq->cqe->iova;
933 aq->cq.cint_idx = cq->cint_idx;
934 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
935 aq->cq.qint_idx = 0;
936 aq->cq.avg_level = 255;
937
938 if (qidx < pfvf->hw.rx_queues) {
939 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
940 aq->cq.drop_ena = 1;
941
942 if (!is_otx2_lbkvf(pfvf->pdev)) {
943 /* Enable receive CQ backpressure */
944 aq->cq.bp_ena = 1;
945 aq->cq.bpid = pfvf->bpid[0];
946
947 /* Set backpressure level is same as cq pass level */
948 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
949 }
950 }
951
952 /* Fill AQ info */
953 aq->qidx = qidx;
954 aq->ctype = NIX_AQ_CTYPE_CQ;
955 aq->op = NIX_AQ_INSTOP_INIT;
956
957 return otx2_sync_mbox_msg(&pfvf->mbox);
958 }
959
otx2_pool_refill_task(struct work_struct * work)960 static void otx2_pool_refill_task(struct work_struct *work)
961 {
962 struct otx2_cq_queue *cq;
963 struct otx2_pool *rbpool;
964 struct refill_work *wrk;
965 int qidx, free_ptrs = 0;
966 struct otx2_nic *pfvf;
967 dma_addr_t bufptr;
968
969 wrk = container_of(work, struct refill_work, pool_refill_work.work);
970 pfvf = wrk->pf;
971 qidx = wrk - pfvf->refill_wrk;
972 cq = &pfvf->qset.cq[qidx];
973 rbpool = cq->rbpool;
974 free_ptrs = cq->pool_ptrs;
975
976 while (cq->pool_ptrs) {
977 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
978 /* Schedule a WQ if we fails to free atleast half of the
979 * pointers else enable napi for this RQ.
980 */
981 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) {
982 struct delayed_work *dwork;
983
984 dwork = &wrk->pool_refill_work;
985 schedule_delayed_work(dwork,
986 msecs_to_jiffies(100));
987 } else {
988 cq->refill_task_sched = false;
989 }
990 return;
991 }
992 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
993 cq->pool_ptrs--;
994 }
995 cq->refill_task_sched = false;
996 }
997
otx2_config_nix_queues(struct otx2_nic * pfvf)998 int otx2_config_nix_queues(struct otx2_nic *pfvf)
999 {
1000 int qidx, err;
1001
1002 /* Initialize RX queues */
1003 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1004 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1005
1006 err = otx2_rq_init(pfvf, qidx, lpb_aura);
1007 if (err)
1008 return err;
1009 }
1010
1011 /* Initialize TX queues */
1012 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) {
1013 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1014
1015 err = otx2_sq_init(pfvf, qidx, sqb_aura);
1016 if (err)
1017 return err;
1018 }
1019
1020 /* Initialize completion queues */
1021 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1022 err = otx2_cq_init(pfvf, qidx);
1023 if (err)
1024 return err;
1025 }
1026
1027 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1028 NIX_LF_CQ_OP_STATUS);
1029
1030 /* Initialize work queue for receive buffer refill */
1031 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1032 sizeof(struct refill_work), GFP_KERNEL);
1033 if (!pfvf->refill_wrk)
1034 return -ENOMEM;
1035
1036 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1037 pfvf->refill_wrk[qidx].pf = pfvf;
1038 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1039 otx2_pool_refill_task);
1040 }
1041 return 0;
1042 }
1043
otx2_config_nix(struct otx2_nic * pfvf)1044 int otx2_config_nix(struct otx2_nic *pfvf)
1045 {
1046 struct nix_lf_alloc_req *nixlf;
1047 struct nix_lf_alloc_rsp *rsp;
1048 int err;
1049
1050 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512;
1051
1052 /* Get memory to put this msg */
1053 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1054 if (!nixlf)
1055 return -ENOMEM;
1056
1057 /* Set RQ/SQ/CQ counts */
1058 nixlf->rq_cnt = pfvf->hw.rx_queues;
1059 nixlf->sq_cnt = pfvf->hw.tx_queues;
1060 nixlf->cq_cnt = pfvf->qset.cq_cnt;
1061 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1062 nixlf->rss_grps = MAX_RSS_GROUPS;
1063 nixlf->xqe_sz = NIX_XQESZ_W16;
1064 /* We don't know absolute NPA LF idx attached.
1065 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1066 * NPA LF attached to this RVU PF/VF.
1067 */
1068 nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1069 /* Disable alignment pad, enable L2 length check,
1070 * enable L4 TCP/UDP checksum verification.
1071 */
1072 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1073
1074 err = otx2_sync_mbox_msg(&pfvf->mbox);
1075 if (err)
1076 return err;
1077
1078 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1079 &nixlf->hdr);
1080 if (IS_ERR(rsp))
1081 return PTR_ERR(rsp);
1082
1083 if (rsp->qints < 1)
1084 return -ENXIO;
1085
1086 return rsp->hdr.rc;
1087 }
1088
otx2_sq_free_sqbs(struct otx2_nic * pfvf)1089 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1090 {
1091 struct otx2_qset *qset = &pfvf->qset;
1092 struct otx2_hw *hw = &pfvf->hw;
1093 struct otx2_snd_queue *sq;
1094 int sqb, qidx;
1095 u64 iova, pa;
1096
1097 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1098 sq = &qset->sq[qidx];
1099 if (!sq->sqb_ptrs)
1100 continue;
1101 for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1102 if (!sq->sqb_ptrs[sqb])
1103 continue;
1104 iova = sq->sqb_ptrs[sqb];
1105 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1106 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1107 DMA_FROM_DEVICE,
1108 DMA_ATTR_SKIP_CPU_SYNC);
1109 put_page(virt_to_page(phys_to_virt(pa)));
1110 }
1111 sq->sqb_count = 0;
1112 }
1113 }
1114
otx2_free_aura_ptr(struct otx2_nic * pfvf,int type)1115 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1116 {
1117 int pool_id, pool_start = 0, pool_end = 0, size = 0;
1118 u64 iova, pa;
1119
1120 if (type == AURA_NIX_SQ) {
1121 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1122 pool_end = pool_start + pfvf->hw.sqpool_cnt;
1123 size = pfvf->hw.sqb_size;
1124 }
1125 if (type == AURA_NIX_RQ) {
1126 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1127 pool_end = pfvf->hw.rqpool_cnt;
1128 size = pfvf->rbsize;
1129 }
1130
1131 /* Free SQB and RQB pointers from the aura pool */
1132 for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1133 iova = otx2_aura_allocptr(pfvf, pool_id);
1134 while (iova) {
1135 if (type == AURA_NIX_RQ)
1136 iova -= OTX2_HEAD_ROOM;
1137
1138 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1139 dma_unmap_page_attrs(pfvf->dev, iova, size,
1140 DMA_FROM_DEVICE,
1141 DMA_ATTR_SKIP_CPU_SYNC);
1142 put_page(virt_to_page(phys_to_virt(pa)));
1143 iova = otx2_aura_allocptr(pfvf, pool_id);
1144 }
1145 }
1146 }
1147
otx2_aura_pool_free(struct otx2_nic * pfvf)1148 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1149 {
1150 struct otx2_pool *pool;
1151 int pool_id;
1152
1153 if (!pfvf->qset.pool)
1154 return;
1155
1156 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1157 pool = &pfvf->qset.pool[pool_id];
1158 qmem_free(pfvf->dev, pool->stack);
1159 qmem_free(pfvf->dev, pool->fc_addr);
1160 }
1161 devm_kfree(pfvf->dev, pfvf->qset.pool);
1162 pfvf->qset.pool = NULL;
1163 }
1164
otx2_aura_init(struct otx2_nic * pfvf,int aura_id,int pool_id,int numptrs)1165 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1166 int pool_id, int numptrs)
1167 {
1168 struct npa_aq_enq_req *aq;
1169 struct otx2_pool *pool;
1170 int err;
1171
1172 pool = &pfvf->qset.pool[pool_id];
1173
1174 /* Allocate memory for HW to update Aura count.
1175 * Alloc one cache line, so that it fits all FC_STYPE modes.
1176 */
1177 if (!pool->fc_addr) {
1178 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1179 if (err)
1180 return err;
1181 }
1182
1183 /* Initialize this aura's context via AF */
1184 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1185 if (!aq) {
1186 /* Shared mbox memory buffer is full, flush it and retry */
1187 err = otx2_sync_mbox_msg(&pfvf->mbox);
1188 if (err)
1189 return err;
1190 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1191 if (!aq)
1192 return -ENOMEM;
1193 }
1194
1195 aq->aura_id = aura_id;
1196 /* Will be filled by AF with correct pool context address */
1197 aq->aura.pool_addr = pool_id;
1198 aq->aura.pool_caching = 1;
1199 aq->aura.shift = ilog2(numptrs) - 8;
1200 aq->aura.count = numptrs;
1201 aq->aura.limit = numptrs;
1202 aq->aura.avg_level = 255;
1203 aq->aura.ena = 1;
1204 aq->aura.fc_ena = 1;
1205 aq->aura.fc_addr = pool->fc_addr->iova;
1206 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1207
1208 /* Enable backpressure for RQ aura */
1209 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1210 aq->aura.bp_ena = 0;
1211 /* If NIX1 LF is attached then specify NIX1_RX.
1212 *
1213 * Below NPA_AURA_S[BP_ENA] is set according to the
1214 * NPA_BPINTF_E enumeration given as:
1215 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1216 * NIX0_RX is 0x0 + 0*0x1 = 0
1217 * NIX1_RX is 0x0 + 1*0x1 = 1
1218 * But in HRM it is given that
1219 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1220 * NIX-RX based on [BP] level. One bit per NIX-RX; index
1221 * enumerated by NPA_BPINTF_E."
1222 */
1223 if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1224 aq->aura.bp_ena = 1;
1225 aq->aura.nix0_bpid = pfvf->bpid[0];
1226
1227 /* Set backpressure level for RQ's Aura */
1228 aq->aura.bp = RQ_BP_LVL_AURA;
1229 }
1230
1231 /* Fill AQ info */
1232 aq->ctype = NPA_AQ_CTYPE_AURA;
1233 aq->op = NPA_AQ_INSTOP_INIT;
1234
1235 return 0;
1236 }
1237
otx2_pool_init(struct otx2_nic * pfvf,u16 pool_id,int stack_pages,int numptrs,int buf_size)1238 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1239 int stack_pages, int numptrs, int buf_size)
1240 {
1241 struct npa_aq_enq_req *aq;
1242 struct otx2_pool *pool;
1243 int err;
1244
1245 pool = &pfvf->qset.pool[pool_id];
1246 /* Alloc memory for stack which is used to store buffer pointers */
1247 err = qmem_alloc(pfvf->dev, &pool->stack,
1248 stack_pages, pfvf->hw.stack_pg_bytes);
1249 if (err)
1250 return err;
1251
1252 pool->rbsize = buf_size;
1253
1254 /* Initialize this pool's context via AF */
1255 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1256 if (!aq) {
1257 /* Shared mbox memory buffer is full, flush it and retry */
1258 err = otx2_sync_mbox_msg(&pfvf->mbox);
1259 if (err) {
1260 qmem_free(pfvf->dev, pool->stack);
1261 return err;
1262 }
1263 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1264 if (!aq) {
1265 qmem_free(pfvf->dev, pool->stack);
1266 return -ENOMEM;
1267 }
1268 }
1269
1270 aq->aura_id = pool_id;
1271 aq->pool.stack_base = pool->stack->iova;
1272 aq->pool.stack_caching = 1;
1273 aq->pool.ena = 1;
1274 aq->pool.buf_size = buf_size / 128;
1275 aq->pool.stack_max_pages = stack_pages;
1276 aq->pool.shift = ilog2(numptrs) - 8;
1277 aq->pool.ptr_start = 0;
1278 aq->pool.ptr_end = ~0ULL;
1279
1280 /* Fill AQ info */
1281 aq->ctype = NPA_AQ_CTYPE_POOL;
1282 aq->op = NPA_AQ_INSTOP_INIT;
1283
1284 return 0;
1285 }
1286
otx2_sq_aura_pool_init(struct otx2_nic * pfvf)1287 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1288 {
1289 int qidx, pool_id, stack_pages, num_sqbs;
1290 struct otx2_qset *qset = &pfvf->qset;
1291 struct otx2_hw *hw = &pfvf->hw;
1292 struct otx2_snd_queue *sq;
1293 struct otx2_pool *pool;
1294 dma_addr_t bufptr;
1295 int err, ptr;
1296
1297 /* Calculate number of SQBs needed.
1298 *
1299 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1300 * Last SQE is used for pointing to next SQB.
1301 */
1302 num_sqbs = (hw->sqb_size / 128) - 1;
1303 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1304
1305 /* Get no of stack pages needed */
1306 stack_pages =
1307 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1308
1309 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1310 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1311 /* Initialize aura context */
1312 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1313 if (err)
1314 goto fail;
1315
1316 /* Initialize pool context */
1317 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1318 num_sqbs, hw->sqb_size);
1319 if (err)
1320 goto fail;
1321 }
1322
1323 /* Flush accumulated messages */
1324 err = otx2_sync_mbox_msg(&pfvf->mbox);
1325 if (err)
1326 goto fail;
1327
1328 /* Allocate pointers and free them to aura/pool */
1329 for (qidx = 0; qidx < hw->tx_queues; qidx++) {
1330 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1331 pool = &pfvf->qset.pool[pool_id];
1332
1333 sq = &qset->sq[qidx];
1334 sq->sqb_count = 0;
1335 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1336 if (!sq->sqb_ptrs) {
1337 err = -ENOMEM;
1338 goto err_mem;
1339 }
1340
1341 for (ptr = 0; ptr < num_sqbs; ptr++) {
1342 err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1343 if (err)
1344 goto err_mem;
1345 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1346 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1347 }
1348 }
1349
1350 err_mem:
1351 return err ? -ENOMEM : 0;
1352
1353 fail:
1354 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1355 otx2_aura_pool_free(pfvf);
1356 return err;
1357 }
1358
otx2_rq_aura_pool_init(struct otx2_nic * pfvf)1359 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1360 {
1361 struct otx2_hw *hw = &pfvf->hw;
1362 int stack_pages, pool_id, rq;
1363 struct otx2_pool *pool;
1364 int err, ptr, num_ptrs;
1365 dma_addr_t bufptr;
1366
1367 num_ptrs = pfvf->qset.rqe_cnt;
1368
1369 stack_pages =
1370 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1371
1372 for (rq = 0; rq < hw->rx_queues; rq++) {
1373 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1374 /* Initialize aura context */
1375 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1376 if (err)
1377 goto fail;
1378 }
1379 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1380 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1381 num_ptrs, pfvf->rbsize);
1382 if (err)
1383 goto fail;
1384 }
1385
1386 /* Flush accumulated messages */
1387 err = otx2_sync_mbox_msg(&pfvf->mbox);
1388 if (err)
1389 goto fail;
1390
1391 /* Allocate pointers and free them to aura/pool */
1392 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1393 pool = &pfvf->qset.pool[pool_id];
1394 for (ptr = 0; ptr < num_ptrs; ptr++) {
1395 err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1396 if (err)
1397 return -ENOMEM;
1398 pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1399 bufptr + OTX2_HEAD_ROOM);
1400 }
1401 }
1402 return 0;
1403 fail:
1404 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1405 otx2_aura_pool_free(pfvf);
1406 return err;
1407 }
1408
otx2_config_npa(struct otx2_nic * pfvf)1409 int otx2_config_npa(struct otx2_nic *pfvf)
1410 {
1411 struct otx2_qset *qset = &pfvf->qset;
1412 struct npa_lf_alloc_req *npalf;
1413 struct otx2_hw *hw = &pfvf->hw;
1414 int aura_cnt;
1415
1416 /* Pool - Stack of free buffer pointers
1417 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1418 */
1419
1420 if (!hw->pool_cnt)
1421 return -EINVAL;
1422
1423 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1424 sizeof(struct otx2_pool), GFP_KERNEL);
1425 if (!qset->pool)
1426 return -ENOMEM;
1427
1428 /* Get memory to put this msg */
1429 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1430 if (!npalf)
1431 return -ENOMEM;
1432
1433 /* Set aura and pool counts */
1434 npalf->nr_pools = hw->pool_cnt;
1435 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1436 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1437
1438 return otx2_sync_mbox_msg(&pfvf->mbox);
1439 }
1440
otx2_detach_resources(struct mbox * mbox)1441 int otx2_detach_resources(struct mbox *mbox)
1442 {
1443 struct rsrc_detach *detach;
1444
1445 mutex_lock(&mbox->lock);
1446 detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1447 if (!detach) {
1448 mutex_unlock(&mbox->lock);
1449 return -ENOMEM;
1450 }
1451
1452 /* detach all */
1453 detach->partial = false;
1454
1455 /* Send detach request to AF */
1456 otx2_mbox_msg_send(&mbox->mbox, 0);
1457 mutex_unlock(&mbox->lock);
1458 return 0;
1459 }
1460 EXPORT_SYMBOL(otx2_detach_resources);
1461
otx2_attach_npa_nix(struct otx2_nic * pfvf)1462 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1463 {
1464 struct rsrc_attach *attach;
1465 struct msg_req *msix;
1466 int err;
1467
1468 mutex_lock(&pfvf->mbox.lock);
1469 /* Get memory to put this msg */
1470 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1471 if (!attach) {
1472 mutex_unlock(&pfvf->mbox.lock);
1473 return -ENOMEM;
1474 }
1475
1476 attach->npalf = true;
1477 attach->nixlf = true;
1478
1479 /* Send attach request to AF */
1480 err = otx2_sync_mbox_msg(&pfvf->mbox);
1481 if (err) {
1482 mutex_unlock(&pfvf->mbox.lock);
1483 return err;
1484 }
1485
1486 pfvf->nix_blkaddr = BLKADDR_NIX0;
1487
1488 /* If the platform has two NIX blocks then LF may be
1489 * allocated from NIX1.
1490 */
1491 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1492 pfvf->nix_blkaddr = BLKADDR_NIX1;
1493
1494 /* Get NPA and NIX MSIX vector offsets */
1495 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1496 if (!msix) {
1497 mutex_unlock(&pfvf->mbox.lock);
1498 return -ENOMEM;
1499 }
1500
1501 err = otx2_sync_mbox_msg(&pfvf->mbox);
1502 if (err) {
1503 mutex_unlock(&pfvf->mbox.lock);
1504 return err;
1505 }
1506 mutex_unlock(&pfvf->mbox.lock);
1507
1508 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1509 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1510 dev_err(pfvf->dev,
1511 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1512 return -EINVAL;
1513 }
1514
1515 return 0;
1516 }
1517 EXPORT_SYMBOL(otx2_attach_npa_nix);
1518
otx2_ctx_disable(struct mbox * mbox,int type,bool npa)1519 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1520 {
1521 struct hwctx_disable_req *req;
1522
1523 mutex_lock(&mbox->lock);
1524 /* Request AQ to disable this context */
1525 if (npa)
1526 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1527 else
1528 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1529
1530 if (!req) {
1531 mutex_unlock(&mbox->lock);
1532 return;
1533 }
1534
1535 req->ctype = type;
1536
1537 if (otx2_sync_mbox_msg(mbox))
1538 dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1539 __func__);
1540
1541 mutex_unlock(&mbox->lock);
1542 }
1543
otx2_nix_config_bp(struct otx2_nic * pfvf,bool enable)1544 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1545 {
1546 struct nix_bp_cfg_req *req;
1547
1548 if (enable)
1549 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1550 else
1551 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1552
1553 if (!req)
1554 return -ENOMEM;
1555
1556 req->chan_base = 0;
1557 req->chan_cnt = 1;
1558 req->bpid_per_chan = 0;
1559
1560 return otx2_sync_mbox_msg(&pfvf->mbox);
1561 }
1562
1563 /* Mbox message handlers */
mbox_handler_cgx_stats(struct otx2_nic * pfvf,struct cgx_stats_rsp * rsp)1564 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1565 struct cgx_stats_rsp *rsp)
1566 {
1567 int id;
1568
1569 for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1570 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1571 for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1572 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1573 }
1574
mbox_handler_cgx_fec_stats(struct otx2_nic * pfvf,struct cgx_fec_stats_rsp * rsp)1575 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1576 struct cgx_fec_stats_rsp *rsp)
1577 {
1578 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1579 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1580 }
1581
mbox_handler_nix_txsch_alloc(struct otx2_nic * pf,struct nix_txsch_alloc_rsp * rsp)1582 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
1583 struct nix_txsch_alloc_rsp *rsp)
1584 {
1585 int lvl, schq;
1586
1587 /* Setup transmit scheduler list */
1588 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
1589 for (schq = 0; schq < rsp->schq[lvl]; schq++)
1590 pf->hw.txschq_list[lvl][schq] =
1591 rsp->schq_list[lvl][schq];
1592
1593 pf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
1594 }
1595 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc);
1596
mbox_handler_npa_lf_alloc(struct otx2_nic * pfvf,struct npa_lf_alloc_rsp * rsp)1597 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1598 struct npa_lf_alloc_rsp *rsp)
1599 {
1600 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1601 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1602 }
1603 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1604
mbox_handler_nix_lf_alloc(struct otx2_nic * pfvf,struct nix_lf_alloc_rsp * rsp)1605 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1606 struct nix_lf_alloc_rsp *rsp)
1607 {
1608 pfvf->hw.sqb_size = rsp->sqb_size;
1609 pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1610 pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1611 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1612 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1613 pfvf->hw.cgx_links = rsp->cgx_links;
1614 pfvf->hw.lbk_links = rsp->lbk_links;
1615 pfvf->hw.tx_link = rsp->tx_link;
1616 }
1617 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1618
mbox_handler_msix_offset(struct otx2_nic * pfvf,struct msix_offset_rsp * rsp)1619 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1620 struct msix_offset_rsp *rsp)
1621 {
1622 pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1623 pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1624 }
1625 EXPORT_SYMBOL(mbox_handler_msix_offset);
1626
mbox_handler_nix_bp_enable(struct otx2_nic * pfvf,struct nix_bp_cfg_rsp * rsp)1627 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1628 struct nix_bp_cfg_rsp *rsp)
1629 {
1630 int chan, chan_id;
1631
1632 for (chan = 0; chan < rsp->chan_cnt; chan++) {
1633 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1634 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1635 }
1636 }
1637 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1638
otx2_free_cints(struct otx2_nic * pfvf,int n)1639 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1640 {
1641 struct otx2_qset *qset = &pfvf->qset;
1642 struct otx2_hw *hw = &pfvf->hw;
1643 int irq, qidx;
1644
1645 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1646 qidx < n;
1647 qidx++, irq++) {
1648 int vector = pci_irq_vector(pfvf->pdev, irq);
1649
1650 irq_set_affinity_hint(vector, NULL);
1651 free_cpumask_var(hw->affinity_mask[irq]);
1652 free_irq(vector, &qset->napi[qidx]);
1653 }
1654 }
1655
otx2_set_cints_affinity(struct otx2_nic * pfvf)1656 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1657 {
1658 struct otx2_hw *hw = &pfvf->hw;
1659 int vec, cpu, irq, cint;
1660
1661 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1662 cpu = cpumask_first(cpu_online_mask);
1663
1664 /* CQ interrupts */
1665 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1666 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1667 return;
1668
1669 cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1670
1671 irq = pci_irq_vector(pfvf->pdev, vec);
1672 irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1673
1674 cpu = cpumask_next(cpu, cpu_online_mask);
1675 if (unlikely(cpu >= nr_cpu_ids))
1676 cpu = 0;
1677 }
1678 }
1679
otx2_get_max_mtu(struct otx2_nic * pfvf)1680 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1681 {
1682 struct nix_hw_info *rsp;
1683 struct msg_req *req;
1684 u16 max_mtu;
1685 int rc;
1686
1687 mutex_lock(&pfvf->mbox.lock);
1688
1689 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1690 if (!req) {
1691 rc = -ENOMEM;
1692 goto out;
1693 }
1694
1695 rc = otx2_sync_mbox_msg(&pfvf->mbox);
1696 if (!rc) {
1697 rsp = (struct nix_hw_info *)
1698 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1699
1700 /* HW counts VLAN insertion bytes (8 for double tag)
1701 * irrespective of whether SQE is requesting to insert VLAN
1702 * in the packet or not. Hence these 8 bytes have to be
1703 * discounted from max packet size otherwise HW will throw
1704 * SMQ errors
1705 */
1706 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1707
1708 /* Also save DWRR MTU, needed for DWRR weight calculation */
1709 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu;
1710 if (!pfvf->hw.dwrr_mtu)
1711 pfvf->hw.dwrr_mtu = 1;
1712 }
1713
1714 out:
1715 mutex_unlock(&pfvf->mbox.lock);
1716 if (rc) {
1717 dev_warn(pfvf->dev,
1718 "Failed to get MTU from hardware setting default value(1500)\n");
1719 max_mtu = 1500;
1720 }
1721 return max_mtu;
1722 }
1723 EXPORT_SYMBOL(otx2_get_max_mtu);
1724
1725 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1726 int __weak \
1727 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
1728 struct _req_type *req, \
1729 struct _rsp_type *rsp) \
1730 { \
1731 /* Nothing to do here */ \
1732 return 0; \
1733 } \
1734 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1735 MBOX_UP_CGX_MESSAGES
1736 #undef M
1737