| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 148 .num_states = 1,
1215 unsigned int num_states = 0; in dcn303_update_bw_bounding_box() local
1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1298 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1299 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_update_bw_bounding_box()
1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1303 dram_speed_mts[num_states++] = in dcn303_update_bw_bounding_box()
1311 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1312 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1313 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_update_bw_bounding_box()
[all …]
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| /drivers/regulator/ |
| D | irq_helpers.c | 62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 166 .num_states = 1,
1285 unsigned int num_states = 0; in dcn302_update_bw_bounding_box() local
1369 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1371 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1372 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_update_bw_bounding_box()
1375 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1376 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_update_bw_bounding_box()
1383 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1384 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1385 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 183 .num_states = 1,
1903 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1906 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1919 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1928 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2093 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2334 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2384 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2470 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2472 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 306 .num_states = 8
1044 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1218 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
1229 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
1375 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth_fp()
1605 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { in update_bw_bounding_box()
1611 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { in update_bw_bounding_box()
1641 dcn2_1_soc.num_states = clk_table->num_entries + 1; in update_bw_bounding_box()
1645 …dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1… in update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 266 .num_states = 5,
1540 if (loaded_bb->num_states == 1) { in set_wm_ranges()
1548 } else if (loaded_bb->num_states > 1) { in set_wm_ranges()
1549 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { in set_wm_ranges()
1592 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
1616 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
1618 …dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states… in dcn301_update_bw_bounding_box()
1619 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
1639 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 301 .num_states = 5,
412 .num_states = 5,
2689 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
2694 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2839 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2910 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
3201 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn20_validate_bandwidth_internal()
3450 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
3485 for (i = bb->num_states - 1; i > 1; i--) { in dcn20_cap_soc_clocks()
3506 bb->num_states--; in dcn20_cap_soc_clocks()
[all …]
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| D | dcn20_resource.h | 103 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 78 uint32_t num_states; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_mode_vba_30.c | 2059 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3960 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3969 …utODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3970 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3975 …MCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3976 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3981 …MCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3982 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
4090 …(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->so… in dml30_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 229 unsigned int *clock_values_in_khz, unsigned int *num_states);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_mode_vba_20.c | 1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
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| D | display_mode_vba_20v2.c | 1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_mode_vba_31.c | 2183 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4099 for (i = 0; i < v->soc.num_states; i++) {
4109 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4110 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4117 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4118 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4125 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4126 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4255 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4256 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_mode_vba_21.c | 1642 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3551 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3593 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3947 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3949 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml21_ModeSupportAndSystemConfigurationFull()
3971 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
3978 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4055 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull()
4087 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4104 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_structs.h | 74 unsigned int num_states; member
|
| D | display_mode_lib.c | 266 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
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| D | display_mode_vba.c | 260 for (i = 0; i < mode_lib->vba.soc.num_states; i++) in fetch_socbb_params()
278 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in fetch_socbb_params()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 775 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
787 num_states)) in pp_nv_get_uclk_dpm_states()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 217 .num_states = 5,
1846 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn31_validate_bandwidth()
1890 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
1921 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/include/ |
| D | kgd_pp_interface.h | 396 unsigned int *num_states);
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | amdgpu_smu.h | 754 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 2064 … navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) in navi10_get_uclk_dpm_states() argument
2072 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) in navi10_get_uclk_dpm_states()
2082 *num_states = num_discrete_levels; in navi10_get_uclk_dpm_states()
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| D | sienna_cichlid_ppt.c | 1805 …cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) in sienna_cichlid_get_uclk_dpm_states() argument
1814 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) in sienna_cichlid_get_uclk_dpm_states()
1825 *num_states = num_discrete_levels; in sienna_cichlid_get_uclk_dpm_states()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 2911 unsigned int *num_states) in smu_get_uclk_dpm_states() argument
2922 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); in smu_get_uclk_dpm_states()
|