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Searched refs:performance_levels (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dni_dpm.c808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
813 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()
814 if (ps->performance_levels[i].vddci > max_limits->vddci) in ni_apply_state_adjust_rules()
815 ps->performance_levels[i].vddci = max_limits->vddci; in ni_apply_state_adjust_rules()
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
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Dsi_dpm.c2303 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2304 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2323 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2324 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2330 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2339 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2398 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
3012 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3013 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3017 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
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Dci_dpm.c807 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
808 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
809 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
810 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
817 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
818 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
820 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
821 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
831 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
832 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
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Dni_dpm.h175 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member
Dci_dpm.h50 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; member
/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.c2402 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2403 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2421 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2422 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2428 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2437 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2496 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
3163 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3164 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3181 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
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Dsi_dpm.h617 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c3313 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3314 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3315 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
3316 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
3366 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3367 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3372 mclk = smu7_ps->performance_levels in smu7_apply_state_adjust_rules()
3383 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
3384 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3386 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
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Dvega10_hwmgr.c3148 performance_level = &(vega10_power_state->performance_levels in vega10_get_pp_table_entry_callback_func()
3172 performance_level = &(vega10_power_state->performance_levels in vega10_get_pp_table_entry_callback_func()
3272 if (vega10_ps->performance_levels[i].mem_clock > in vega10_apply_state_adjust_rules()
3274 vega10_ps->performance_levels[i].mem_clock = in vega10_apply_state_adjust_rules()
3276 if (vega10_ps->performance_levels[i].gfx_clock > in vega10_apply_state_adjust_rules()
3278 vega10_ps->performance_levels[i].gfx_clock = in vega10_apply_state_adjust_rules()
3334 sclk = vega10_ps->performance_levels[0].gfx_clock; in vega10_apply_state_adjust_rules()
3335 mclk = vega10_ps->performance_levels[0].mem_clock; in vega10_apply_state_adjust_rules()
3345 vega10_ps->performance_levels[0].gfx_clock = sclk; in vega10_apply_state_adjust_rules()
3346 vega10_ps->performance_levels[0].mem_clock = mclk; in vega10_apply_state_adjust_rules()
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Dsmu7_hwmgr.h85 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; member
Dvega10_hwmgr.h112 struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; member
Dvega20_hwmgr.h129 struct vega20_performance_level performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS]; member
/drivers/platform/x86/
Dsamsung-laptop.c148 const struct sabi_performance_level performance_levels[4]; member
205 .performance_levels = {
268 .performance_levels = {
672 for (i = 0; config->performance_levels[i].name; ++i) { in get_performance_level()
673 if (sretval.data[0] == config->performance_levels[i].value) in get_performance_level()
674 return sprintf(buf, "%s\n", config->performance_levels[i].name); in get_performance_level()
691 for (i = 0; config->performance_levels[i].name; ++i) { in set_performance_level()
693 &config->performance_levels[i]; in set_performance_level()
702 if (!config->performance_levels[i].name) in set_performance_level()
1216 ok = !!samsung->config->performance_levels[0].name; in samsung_sysfs_is_visible()