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Searched refs:phy_reg (Results 1 – 25 of 26) sorted by relevance

12

/drivers/phy/realtek/
Dphy-rtk-usb3.c56 struct phy_reg { struct
77 struct phy_reg phy_reg; member
116 static int rtk_phy3_wait_vbusy(struct phy_reg *phy_reg) in rtk_phy3_wait_vbusy() argument
118 return utmi_wait_register(phy_reg->reg_mdio_ctl, USB_MDIO_CTRL_PHY_BUSY, 0); in rtk_phy3_wait_vbusy()
121 static u16 rtk_phy_read(struct phy_reg *phy_reg, char addr) in rtk_phy_read() argument
128 writel(tmp, phy_reg->reg_mdio_ctl); in rtk_phy_read()
130 rtk_phy3_wait_vbusy(phy_reg); in rtk_phy_read()
132 value = readl(phy_reg->reg_mdio_ctl); in rtk_phy_read()
138 static int rtk_phy_write(struct phy_reg *phy_reg, char addr, u16 data) in rtk_phy_write() argument
146 writel(val, phy_reg->reg_mdio_ctl); in rtk_phy_write()
[all …]
Dphy-rtk-usb2.c65 struct phy_reg { struct
104 struct phy_reg phy_reg; member
159 static char rtk_phy_read(struct phy_reg *phy_reg, char addr) in rtk_phy_read() argument
161 void __iomem *reg_gusb2phyacc0 = phy_reg->reg_gusb2phyacc0; in rtk_phy_read()
191 static int rtk_phy_write(struct phy_reg *phy_reg, char addr, char data) in rtk_phy_write() argument
194 void __iomem *reg_wrap_vstatus = phy_reg->reg_wrap_vstatus; in rtk_phy_write()
195 void __iomem *reg_gusb2phyacc0 = phy_reg->reg_gusb2phyacc0; in rtk_phy_write()
196 int shift_bits = phy_reg->vstatus_index * 8; in rtk_phy_write()
225 static int rtk_phy_set_page(struct phy_reg *phy_reg, int page) in rtk_phy_set_page() argument
229 return rtk_phy_write(phy_reg, SET_PAGE_OFFSET, SET_PAGE_0); in rtk_phy_set_page()
[all …]
/drivers/net/ethernet/dec/tulip/
Dpnic.c23 u32 phy_reg = ioread32(ioaddr + 0xB8); in pnic_do_nway() local
26 if (phy_reg & 0x78000000) { /* Ignore baseT4 */ in pnic_do_nway()
27 if (phy_reg & 0x20000000) dev->if_port = 5; in pnic_do_nway()
28 else if (phy_reg & 0x40000000) dev->if_port = 3; in pnic_do_nway()
29 else if (phy_reg & 0x10000000) dev->if_port = 4; in pnic_do_nway()
30 else if (phy_reg & 0x08000000) dev->if_port = 0; in pnic_do_nway()
36 if (phy_reg & 0x30000000) { in pnic_do_nway()
42 phy_reg, medianame[dev->if_port]); in pnic_do_nway()
56 int phy_reg = ioread32(ioaddr + 0xB8); in pnic_lnk_change() local
60 phy_reg, csr5); in pnic_lnk_change()
[all …]
Ddmfe.c1670 u16 phy_reg; in dmfe_set_phyxcer() local
1678 phy_reg = dmfe_phy_read(db->ioaddr, in dmfe_set_phyxcer()
1682 db->phy_addr, 18, phy_reg, db->chip_id); in dmfe_set_phyxcer()
1686 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; in dmfe_set_phyxcer()
1690 phy_reg |= db->PHY_reg4; in dmfe_set_phyxcer()
1694 case DMFE_10MHF: phy_reg |= 0x20; break; in dmfe_set_phyxcer()
1695 case DMFE_10MFD: phy_reg |= 0x40; break; in dmfe_set_phyxcer()
1696 case DMFE_100MHF: phy_reg |= 0x80; break; in dmfe_set_phyxcer()
1697 case DMFE_100MFD: phy_reg |= 0x100; break; in dmfe_set_phyxcer()
1699 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61; in dmfe_set_phyxcer()
[all …]
Duli526x.c1519 u16 phy_reg; in uli526x_set_phyxcer() local
1522 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0; in uli526x_set_phyxcer()
1526 phy_reg |= db->PHY_reg4; in uli526x_set_phyxcer()
1530 case ULI526X_10MHF: phy_reg |= 0x20; break; in uli526x_set_phyxcer()
1531 case ULI526X_10MFD: phy_reg |= 0x40; break; in uli526x_set_phyxcer()
1532 case ULI526X_100MHF: phy_reg |= 0x80; break; in uli526x_set_phyxcer()
1533 case ULI526X_100MFD: phy_reg |= 0x100; break; in uli526x_set_phyxcer()
1539 if ( !(phy_reg & 0x01e0)) { in uli526x_set_phyxcer()
1540 phy_reg|=db->PHY_reg4; in uli526x_set_phyxcer()
1543 phy->write(db, db->phy_addr, 4, phy_reg); in uli526x_set_phyxcer()
[all …]
/drivers/clk/hisilicon/
Dclk-hix5hd2.c139 u32 phy_reg; member
151 void __iomem *phy_reg; member
180 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
183 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
188 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
193 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
223 val = readl_relaxed(clk->phy_reg); in clk_complex_enable()
226 writel_relaxed(val, clk->phy_reg); in clk_complex_enable()
241 val = readl_relaxed(clk->phy_reg); in clk_complex_disable()
244 writel_relaxed(val, clk->phy_reg); in clk_complex_disable()
[all …]
/drivers/net/ethernet/mellanox/mlxbf_gige/
Dmlxbf_gige_mdio.c138 int phy_reg, u32 opcode) in mlxbf_gige_mdio_create_cmd() argument
143 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg); in mlxbf_gige_mdio_create_cmd()
154 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg) in mlxbf_gige_mdio_read() argument
161 if (phy_reg & MII_ADDR_C45) in mlxbf_gige_mdio_read()
165 cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ); in mlxbf_gige_mdio_read()
188 int phy_reg, u16 val) in mlxbf_gige_mdio_write() argument
195 if (phy_reg & MII_ADDR_C45) in mlxbf_gige_mdio_write()
199 cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg, in mlxbf_gige_mdio_write()
/drivers/net/ethernet/intel/e1000e/
Dich8lan.c178 u16 phy_reg = 0; in e1000_phy_is_accessible_pchlan() local
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
186 if (ret_val || (phy_reg == 0xFFFF)) in e1000_phy_is_accessible_pchlan()
188 phy_id = (u32)(phy_reg << 16); in e1000_phy_is_accessible_pchlan()
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
191 if (ret_val || (phy_reg == 0xFFFF)) { in e1000_phy_is_accessible_pchlan()
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; in e1000_phy_is_accessible_pchlan()
[all …]
Dethtool.c1323 u16 phy_reg = 0; in e1000_integrated_phy_loopback() local
1362 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1363 phy_reg &= ~0x0007; in e1000_integrated_phy_loopback()
1364 phy_reg |= 0x006; in e1000_integrated_phy_loopback()
1365 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1370 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1371 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1373 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1374 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1376 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
[all …]
Dphy.h48 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
49 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
Dphy.c2538 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) in e1000_enable_phy_wakeup_reg_access_bm() argument
2553 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); in e1000_enable_phy_wakeup_reg_access_bm()
2563 temp = *phy_reg; in e1000_enable_phy_wakeup_reg_access_bm()
2591 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) in e1000_disable_phy_wakeup_reg_access_bm() argument
2603 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); in e1000_disable_phy_wakeup_reg_access_bm()
2642 u16 phy_reg = 0; in e1000_access_phy_wakeup_reg_bm() local
2652 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_access_phy_wakeup_reg_bm()
2684 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_access_phy_wakeup_reg_bm()
Dnetdev.c6226 u16 phy_reg, wuc_enable; in e1000_init_phy_wakeup() local
6253 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); in e1000_init_phy_wakeup()
6256 phy_reg |= BM_RCTL_UPE; in e1000_init_phy_wakeup()
6258 phy_reg |= BM_RCTL_MPE; in e1000_init_phy_wakeup()
6259 phy_reg &= ~(BM_RCTL_MO_MASK); in e1000_init_phy_wakeup()
6261 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) in e1000_init_phy_wakeup()
6264 phy_reg |= BM_RCTL_BAM; in e1000_init_phy_wakeup()
6266 phy_reg |= BM_RCTL_PMCF; in e1000_init_phy_wakeup()
6269 phy_reg |= BM_RCTL_RFCE; in e1000_init_phy_wakeup()
6270 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); in e1000_init_phy_wakeup()
/drivers/usb/phy/
Dphy-am335x-control.c13 void __iomem *phy_reg; member
84 val = readl(usb_ctrl->phy_reg + reg); in am335x_phy_power()
98 writel(val, usb_ctrl->phy_reg + reg); in am335x_phy_power()
168 ctrl_usb->phy_reg = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl"); in am335x_control_usb_probe()
169 if (IS_ERR(ctrl_usb->phy_reg)) in am335x_control_usb_probe()
170 return PTR_ERR(ctrl_usb->phy_reg); in am335x_control_usb_probe()
/drivers/net/
Dsungem_phy.c601 u32 phy_reg; in bcm5421_poll_link() local
606 phy_reg = sungem_phy_read(phy, MII_NCONFIG); in bcm5421_poll_link()
608 mode = (phy_reg & BCM5421_MODE_MASK) >> 5; in bcm5421_poll_link()
615 phy_reg = sungem_phy_read(phy, MII_NCONFIG); in bcm5421_poll_link()
617 if (phy_reg & 0x0020) in bcm5421_poll_link()
625 u32 phy_reg; in bcm5421_read_link() local
630 phy_reg = sungem_phy_read(phy, MII_NCONFIG); in bcm5421_read_link()
632 mode = (phy_reg & BCM5421_MODE_MASK ) >> 5; in bcm5421_read_link()
641 phy_reg = sungem_phy_read(phy, MII_NCONFIG); in bcm5421_read_link()
643 if ( (phy_reg & 0x0080) >> 7) in bcm5421_read_link()
[all …]
/drivers/net/ethernet/intel/e1000/
De1000_ethtool.c1114 u16 phy_reg; in e1000_phy_reset_clk_and_crs() local
1120 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); in e1000_phy_reset_clk_and_crs()
1121 phy_reg |= M88E1000_EPSCR_TX_CLK_25; in e1000_phy_reset_clk_and_crs()
1122 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_reg); in e1000_phy_reset_clk_and_crs()
1128 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); in e1000_phy_reset_clk_and_crs()
1129 phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX; in e1000_phy_reset_clk_and_crs()
1130 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg); in e1000_phy_reset_clk_and_crs()
1137 u16 phy_reg; in e1000_nonintegrated_phy_loopback() local
1151 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1156 phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE; in e1000_nonintegrated_phy_loopback()
[all …]
/drivers/net/ethernet/realtek/
Dr8169_phy_config.c53 struct phy_reg { struct
59 const struct phy_reg *regs, int len) in __rtl_writephy_batch() argument
111 static const struct phy_reg phy_reg_init[] = { in rtl8169s_hw_phy_config()
185 static const struct phy_reg phy_reg_init[] = { in rtl8169scd_hw_phy_config()
231 static const struct phy_reg phy_reg_init[] = { in rtl8169sce_hw_phy_config()
315 static const struct phy_reg phy_reg_init[] = { in rtl8168c_1_hw_phy_config()
344 static const struct phy_reg phy_reg_init[] = { in rtl8168c_2_hw_phy_config()
372 static const struct phy_reg phy_reg_init[] = { in rtl8168c_3_hw_phy_config()
391 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
432 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
[all …]
/drivers/net/phy/
Dphy_device.c720 int phy_reg; in get_phy_c45_devs_in_pkg() local
722 phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2); in get_phy_c45_devs_in_pkg()
723 if (phy_reg < 0) in get_phy_c45_devs_in_pkg()
725 *devices_in_package = phy_reg << 16; in get_phy_c45_devs_in_pkg()
727 phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1); in get_phy_c45_devs_in_pkg()
728 if (phy_reg < 0) in get_phy_c45_devs_in_pkg()
730 *devices_in_package |= phy_reg; in get_phy_c45_devs_in_pkg()
753 int i, ret, phy_reg; in get_phy_c45_ids() local
774 phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg); in get_phy_c45_ids()
775 if (phy_reg < 0) in get_phy_c45_ids()
[all …]
/drivers/net/usb/
Dsr9800.c372 int phy_reg; in sr_get_phyid() local
378 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in sr_get_phyid()
379 if (phy_reg != 0 && phy_reg != 0xFFFF) in sr_get_phyid()
384 if (phy_reg <= 0 || phy_reg == 0xFFFF) in sr_get_phyid()
387 phy_id = (phy_reg & 0xffff) << 16; in sr_get_phyid()
389 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in sr_get_phyid()
390 if (phy_reg < 0) in sr_get_phyid()
393 phy_id |= (phy_reg & 0xffff); in sr_get_phyid()
Dasix_devices.c72 int phy_reg; in asix_get_phyid() local
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in asix_get_phyid()
79 if (phy_reg < 0) in asix_get_phyid()
81 if (phy_reg != 0 && phy_reg != 0xFFFF) in asix_get_phyid()
86 if (phy_reg <= 0 || phy_reg == 0xFFFF) in asix_get_phyid()
89 phy_id = (phy_reg & 0xffff) << 16; in asix_get_phyid()
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in asix_get_phyid()
92 if (phy_reg < 0) in asix_get_phyid()
95 phy_id |= (phy_reg & 0xffff); in asix_get_phyid()
/drivers/net/ethernet/ti/
Ddavinci_mdio.c377 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) in davinci_mdio_read() argument
383 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) in davinci_mdio_read()
392 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | in davinci_mdio_read()
421 int phy_reg, u16 phy_data) in davinci_mdio_write() argument
427 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) in davinci_mdio_write()
436 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | in davinci_mdio_write()
/drivers/net/ieee802154/
Dmcr20a.c1088 unsigned int phy_reg = 0; in mcr20a_phy_init() local
1170 phy_reg = (u8)(((index & DAR_SRC_CTRL_INDEX) << in mcr20a_phy_init()
1174 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg); in mcr20a_phy_init()
1177 phy_reg = 0; in mcr20a_phy_init()
1181 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg); in mcr20a_phy_init()
1186 phy_reg &= ~IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK; in mcr20a_phy_init()
1189 phy_reg |= MCR20A_PHY_INDIRECT_QUEUE_SIZE << in mcr20a_phy_init()
1191 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg); in mcr20a_phy_init()
/drivers/net/ethernet/
Dlantiq_etop.c304 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) in ltq_etop_mdio_wr() argument
308 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | in ltq_etop_mdio_wr()
318 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) in ltq_etop_mdio_rd() argument
322 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); in ltq_etop_mdio_rd()
/drivers/pinctrl/ti/
Dpinctrl-ti-iodelay.c747 u32 phy_reg; in ti_iodelay_alloc_pins() local
760 phy_reg = r->reg_start_offset + base_phy; in ti_iodelay_alloc_pins()
762 for (i = 0; i < nr_pins; i++, phy_reg += 4) { in ti_iodelay_alloc_pins()
/drivers/phy/rockchip/
Dphy-rockchip-typec.c389 struct phy_reg { struct
394 static struct phy_reg usb3_pll_cfg[] = { argument
411 static struct phy_reg dp_pll_cfg[] = {
/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.c97 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, in _mtk_mdio_write() argument
109 PHY_IAC_REG(phy_reg) | in _mtk_mdio_write()
121 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) in _mtk_mdio_read() argument
132 PHY_IAC_REG(phy_reg) | in _mtk_mdio_read()
144 int phy_reg, u16 val) in mtk_mdio_write() argument
148 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); in mtk_mdio_write()
151 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) in mtk_mdio_read() argument
155 return _mtk_mdio_read(eth, phy_addr, phy_reg); in mtk_mdio_read()

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