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Searched refs:pp_smu_nv_clock_table (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.h101 struct pp_smu_nv_clock_table max_clocks);
103 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
178 struct pp_smu_nv_clock_table max_clocks);
Ddcn20_resource.c3445 struct pp_smu_nv_clock_table max_clocks) in dcn20_cap_soc_clocks()
3511 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) in dcn20_update_bounding_box()
3649 struct pp_smu_nv_clock_table max_clocks = {0}; in init_soc_bounding_box()
/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h152 struct pp_smu_nv_clock_table { struct
224 struct pp_smu_nv_clock_table *max_clocks);
/drivers/gpu/drm/amd/pm/inc/
Dsmu_v13_0.h206 struct pp_smu_nv_clock_table *max_clocks);
Dsmu_v11_0.h246 struct pp_smu_nv_clock_table *max_clocks);
Damdgpu_smu.h1103 …int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max…
/drivers/gpu/drm/amd/include/
Dkgd_pp_interface.h290 struct pp_smu_nv_clock_table;
393 struct pp_smu_nv_clock_table *max_clocks);
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c758 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) in pp_nv_get_maximum_sustainable_clocks()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0.c1383 struct pp_smu_nv_clock_table *max_clocks) in smu_v13_0_get_max_sustainable_clocks_by_dc()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsmu_v11_0.c1551 struct pp_smu_nv_clock_table *max_clocks) in smu_v11_0_get_max_sustainable_clocks_by_dc()
/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c2891 struct pp_smu_nv_clock_table *max_clocks) in smu_get_max_sustainable_clocks_by_dc()