1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60
61 #define SMU13_VOLTAGE_SCALE 4
62
63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
64
65 #define LINK_WIDTH_MAX 6
66 #define LINK_SPEED_MAX 3
67
68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71 #define smnPCIE_LC_SPEED_CNTL 0x11140290
72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
74
75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76 static const int link_speed[] = {25, 50, 80, 160};
77
smu_v13_0_init_microcode(struct smu_context * smu)78 int smu_v13_0_init_microcode(struct smu_context *smu)
79 {
80 struct amdgpu_device *adev = smu->adev;
81 const char *chip_name;
82 char fw_name[30];
83 int err = 0;
84 const struct smc_firmware_header_v1_0 *hdr;
85 const struct common_firmware_header *header;
86 struct amdgpu_firmware_info *ucode = NULL;
87
88 /* doesn't need to load smu firmware in IOV mode */
89 if (amdgpu_sriov_vf(adev))
90 return 0;
91
92 switch (adev->asic_type) {
93 case CHIP_ALDEBARAN:
94 chip_name = "aldebaran";
95 break;
96 default:
97 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
98 return -EINVAL;
99 }
100
101 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
102
103 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
104 if (err)
105 goto out;
106 err = amdgpu_ucode_validate(adev->pm.fw);
107 if (err)
108 goto out;
109
110 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
111 amdgpu_ucode_print_smc_hdr(&hdr->header);
112 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
113
114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
115 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
116 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
117 ucode->fw = adev->pm.fw;
118 header = (const struct common_firmware_header *)ucode->fw->data;
119 adev->firmware.fw_size +=
120 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
121 }
122
123 out:
124 if (err) {
125 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
126 fw_name);
127 release_firmware(adev->pm.fw);
128 adev->pm.fw = NULL;
129 }
130 return err;
131 }
132
smu_v13_0_fini_microcode(struct smu_context * smu)133 void smu_v13_0_fini_microcode(struct smu_context *smu)
134 {
135 struct amdgpu_device *adev = smu->adev;
136
137 release_firmware(adev->pm.fw);
138 adev->pm.fw = NULL;
139 adev->pm.fw_version = 0;
140 }
141
smu_v13_0_load_microcode(struct smu_context * smu)142 int smu_v13_0_load_microcode(struct smu_context *smu)
143 {
144 #if 0
145 struct amdgpu_device *adev = smu->adev;
146 const uint32_t *src;
147 const struct smc_firmware_header_v1_0 *hdr;
148 uint32_t addr_start = MP1_SRAM;
149 uint32_t i;
150 uint32_t smc_fw_size;
151 uint32_t mp1_fw_flags;
152
153 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
154 src = (const uint32_t *)(adev->pm.fw->data +
155 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
156 smc_fw_size = hdr->header.ucode_size_bytes;
157
158 for (i = 1; i < smc_fw_size/4 - 1; i++) {
159 WREG32_PCIE(addr_start, src[i]);
160 addr_start += 4;
161 }
162
163 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
164 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
165 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
167
168 for (i = 0; i < adev->usec_timeout; i++) {
169 mp1_fw_flags = RREG32_PCIE(MP1_Public |
170 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
171 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
172 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
173 break;
174 udelay(1);
175 }
176
177 if (i == adev->usec_timeout)
178 return -ETIME;
179 #endif
180 return 0;
181 }
182
smu_v13_0_check_fw_status(struct smu_context * smu)183 int smu_v13_0_check_fw_status(struct smu_context *smu)
184 {
185 struct amdgpu_device *adev = smu->adev;
186 uint32_t mp1_fw_flags;
187
188 mp1_fw_flags = RREG32_PCIE(MP1_Public |
189 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
190
191 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
192 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
193 return 0;
194
195 return -EIO;
196 }
197
smu_v13_0_check_fw_version(struct smu_context * smu)198 int smu_v13_0_check_fw_version(struct smu_context *smu)
199 {
200 struct amdgpu_device *adev = smu->adev;
201 uint32_t if_version = 0xff, smu_version = 0xff;
202 uint16_t smu_major;
203 uint8_t smu_minor, smu_debug;
204 int ret = 0;
205
206 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
207 if (ret)
208 return ret;
209
210 smu_major = (smu_version >> 16) & 0xffff;
211 smu_minor = (smu_version >> 8) & 0xff;
212 smu_debug = (smu_version >> 0) & 0xff;
213 if (smu->is_apu)
214 adev->pm.fw_version = smu_version;
215
216 switch (smu->adev->asic_type) {
217 case CHIP_ALDEBARAN:
218 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
219 break;
220 case CHIP_YELLOW_CARP:
221 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
222 break;
223 default:
224 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
225 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
226 break;
227 }
228
229 dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
230 smu_version, smu_major, smu_minor, smu_debug);
231
232 /*
233 * 1. if_version mismatch is not critical as our fw is designed
234 * to be backward compatible.
235 * 2. New fw usually brings some optimizations. But that's visible
236 * only on the paired driver.
237 * Considering above, we just leave user a warning message instead
238 * of halt driver loading.
239 */
240 if (if_version != smu->smc_driver_if_version) {
241 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
242 "smu fw version = 0x%08x (%d.%d.%d)\n",
243 smu->smc_driver_if_version, if_version,
244 smu_version, smu_major, smu_minor, smu_debug);
245 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
246 }
247
248 return ret;
249 }
250
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)251 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
252 uint32_t *size, uint32_t pptable_id)
253 {
254 struct amdgpu_device *adev = smu->adev;
255 const struct smc_firmware_header_v2_1 *v2_1;
256 struct smc_soft_pptable_entry *entries;
257 uint32_t pptable_count = 0;
258 int i = 0;
259
260 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
261 entries = (struct smc_soft_pptable_entry *)
262 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
263 pptable_count = le32_to_cpu(v2_1->pptable_count);
264 for (i = 0; i < pptable_count; i++) {
265 if (le32_to_cpu(entries[i].id) == pptable_id) {
266 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
267 *size = le32_to_cpu(entries[i].ppt_size_bytes);
268 break;
269 }
270 }
271
272 if (i == pptable_count)
273 return -EINVAL;
274
275 return 0;
276 }
277
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)278 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
279 {
280 struct amdgpu_device *adev = smu->adev;
281 uint16_t atom_table_size;
282 uint8_t frev, crev;
283 int ret, index;
284
285 dev_info(adev->dev, "use vbios provided pptable\n");
286 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
287 powerplayinfo);
288
289 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
290 (uint8_t **)table);
291 if (ret)
292 return ret;
293
294 if (size)
295 *size = atom_table_size;
296
297 return 0;
298 }
299
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)300 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
301 uint32_t pptable_id)
302 {
303 const struct smc_firmware_header_v1_0 *hdr;
304 struct amdgpu_device *adev = smu->adev;
305 uint16_t version_major, version_minor;
306 int ret;
307
308 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
309 if (!hdr)
310 return -EINVAL;
311
312 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
313
314 version_major = le16_to_cpu(hdr->header.header_version_major);
315 version_minor = le16_to_cpu(hdr->header.header_version_minor);
316 if (version_major != 2) {
317 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
318 version_major, version_minor);
319 return -EINVAL;
320 }
321
322 switch (version_minor) {
323 case 1:
324 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
325 break;
326 default:
327 ret = -EINVAL;
328 break;
329 }
330
331 return ret;
332 }
333
smu_v13_0_setup_pptable(struct smu_context * smu)334 int smu_v13_0_setup_pptable(struct smu_context *smu)
335 {
336 struct amdgpu_device *adev = smu->adev;
337 uint32_t size = 0, pptable_id = 0;
338 void *table;
339 int ret = 0;
340
341 /* override pptable_id from driver parameter */
342 if (amdgpu_smu_pptable_id >= 0) {
343 pptable_id = amdgpu_smu_pptable_id;
344 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
345 } else {
346 pptable_id = smu->smu_table.boot_values.pp_table_id;
347 }
348
349 /* force using vbios pptable in sriov mode */
350 if (amdgpu_sriov_vf(adev) || !pptable_id)
351 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
352 else
353 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
354
355 if (ret)
356 return ret;
357
358 if (!smu->smu_table.power_play_table)
359 smu->smu_table.power_play_table = table;
360 if (!smu->smu_table.power_play_table_size)
361 smu->smu_table.power_play_table_size = size;
362
363 return 0;
364 }
365
smu_v13_0_init_smc_tables(struct smu_context * smu)366 int smu_v13_0_init_smc_tables(struct smu_context *smu)
367 {
368 struct smu_table_context *smu_table = &smu->smu_table;
369 struct smu_table *tables = smu_table->tables;
370 int ret = 0;
371
372 smu_table->driver_pptable =
373 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
374 if (!smu_table->driver_pptable) {
375 ret = -ENOMEM;
376 goto err0_out;
377 }
378
379 smu_table->max_sustainable_clocks =
380 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
381 if (!smu_table->max_sustainable_clocks) {
382 ret = -ENOMEM;
383 goto err1_out;
384 }
385
386 /* Aldebaran does not support OVERDRIVE */
387 if (tables[SMU_TABLE_OVERDRIVE].size) {
388 smu_table->overdrive_table =
389 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
390 if (!smu_table->overdrive_table) {
391 ret = -ENOMEM;
392 goto err2_out;
393 }
394
395 smu_table->boot_overdrive_table =
396 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
397 if (!smu_table->boot_overdrive_table) {
398 ret = -ENOMEM;
399 goto err3_out;
400 }
401 }
402
403 return 0;
404
405 err3_out:
406 kfree(smu_table->overdrive_table);
407 err2_out:
408 kfree(smu_table->max_sustainable_clocks);
409 err1_out:
410 kfree(smu_table->driver_pptable);
411 err0_out:
412 return ret;
413 }
414
smu_v13_0_fini_smc_tables(struct smu_context * smu)415 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
416 {
417 struct smu_table_context *smu_table = &smu->smu_table;
418 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
419
420 kfree(smu_table->gpu_metrics_table);
421 kfree(smu_table->boot_overdrive_table);
422 kfree(smu_table->overdrive_table);
423 kfree(smu_table->max_sustainable_clocks);
424 kfree(smu_table->driver_pptable);
425 smu_table->gpu_metrics_table = NULL;
426 smu_table->boot_overdrive_table = NULL;
427 smu_table->overdrive_table = NULL;
428 smu_table->max_sustainable_clocks = NULL;
429 smu_table->driver_pptable = NULL;
430 kfree(smu_table->hardcode_pptable);
431 smu_table->hardcode_pptable = NULL;
432
433 kfree(smu_table->metrics_table);
434 kfree(smu_table->watermarks_table);
435 smu_table->metrics_table = NULL;
436 smu_table->watermarks_table = NULL;
437 smu_table->metrics_time = 0;
438
439 kfree(smu_dpm->dpm_context);
440 kfree(smu_dpm->golden_dpm_context);
441 kfree(smu_dpm->dpm_current_power_state);
442 kfree(smu_dpm->dpm_request_power_state);
443 smu_dpm->dpm_context = NULL;
444 smu_dpm->golden_dpm_context = NULL;
445 smu_dpm->dpm_context_size = 0;
446 smu_dpm->dpm_current_power_state = NULL;
447 smu_dpm->dpm_request_power_state = NULL;
448
449 return 0;
450 }
451
smu_v13_0_init_power(struct smu_context * smu)452 int smu_v13_0_init_power(struct smu_context *smu)
453 {
454 struct smu_power_context *smu_power = &smu->smu_power;
455
456 if (smu_power->power_context || smu_power->power_context_size != 0)
457 return -EINVAL;
458
459 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
460 GFP_KERNEL);
461 if (!smu_power->power_context)
462 return -ENOMEM;
463 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
464
465 return 0;
466 }
467
smu_v13_0_fini_power(struct smu_context * smu)468 int smu_v13_0_fini_power(struct smu_context *smu)
469 {
470 struct smu_power_context *smu_power = &smu->smu_power;
471
472 if (!smu_power->power_context || smu_power->power_context_size == 0)
473 return -EINVAL;
474
475 kfree(smu_power->power_context);
476 smu_power->power_context = NULL;
477 smu_power->power_context_size = 0;
478
479 return 0;
480 }
481
smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)482 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
483 uint8_t clk_id,
484 uint8_t syspll_id,
485 uint32_t *clk_freq)
486 {
487 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
488 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
489 int ret, index;
490
491 input.clk_id = clk_id;
492 input.syspll_id = syspll_id;
493 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
494 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
495 getsmuclockinfo);
496
497 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
498 (uint32_t *)&input);
499 if (ret)
500 return -EINVAL;
501
502 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
503 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
504
505 return 0;
506 }
507
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)508 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
509 {
510 int ret, index;
511 uint16_t size;
512 uint8_t frev, crev;
513 struct atom_common_table_header *header;
514 struct atom_firmware_info_v3_4 *v_3_4;
515 struct atom_firmware_info_v3_3 *v_3_3;
516 struct atom_firmware_info_v3_1 *v_3_1;
517
518 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
519 firmwareinfo);
520
521 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
522 (uint8_t **)&header);
523 if (ret)
524 return ret;
525
526 if (header->format_revision != 3) {
527 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
528 return -EINVAL;
529 }
530
531 switch (header->content_revision) {
532 case 0:
533 case 1:
534 case 2:
535 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
536 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
537 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
538 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
539 smu->smu_table.boot_values.socclk = 0;
540 smu->smu_table.boot_values.dcefclk = 0;
541 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
542 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
543 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
544 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
545 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
546 smu->smu_table.boot_values.pp_table_id = 0;
547 break;
548 case 3:
549 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
550 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
551 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
552 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
553 smu->smu_table.boot_values.socclk = 0;
554 smu->smu_table.boot_values.dcefclk = 0;
555 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
556 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
557 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
558 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
559 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
560 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
561 break;
562 case 4:
563 default:
564 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
565 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
566 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
567 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
568 smu->smu_table.boot_values.socclk = 0;
569 smu->smu_table.boot_values.dcefclk = 0;
570 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
571 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
572 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
573 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
574 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
575 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
576 break;
577 }
578
579 smu->smu_table.boot_values.format_revision = header->format_revision;
580 smu->smu_table.boot_values.content_revision = header->content_revision;
581
582 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
583 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
584 (uint8_t)0,
585 &smu->smu_table.boot_values.socclk);
586
587 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
588 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
589 (uint8_t)0,
590 &smu->smu_table.boot_values.dcefclk);
591
592 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
593 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
594 (uint8_t)0,
595 &smu->smu_table.boot_values.eclk);
596
597 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
598 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
599 (uint8_t)0,
600 &smu->smu_table.boot_values.vclk);
601
602 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
603 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
604 (uint8_t)0,
605 &smu->smu_table.boot_values.dclk);
606
607 if ((smu->smu_table.boot_values.format_revision == 3) &&
608 (smu->smu_table.boot_values.content_revision >= 2))
609 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
610 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
611 (uint8_t)SMU11_SYSPLL1_2_ID,
612 &smu->smu_table.boot_values.fclk);
613
614 return 0;
615 }
616
617
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)618 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
619 {
620 struct smu_table_context *smu_table = &smu->smu_table;
621 struct smu_table *memory_pool = &smu_table->memory_pool;
622 int ret = 0;
623 uint64_t address;
624 uint32_t address_low, address_high;
625
626 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
627 return ret;
628
629 address = memory_pool->mc_address;
630 address_high = (uint32_t)upper_32_bits(address);
631 address_low = (uint32_t)lower_32_bits(address);
632
633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
634 address_high, NULL);
635 if (ret)
636 return ret;
637 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
638 address_low, NULL);
639 if (ret)
640 return ret;
641 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
642 (uint32_t)memory_pool->size, NULL);
643 if (ret)
644 return ret;
645
646 return ret;
647 }
648
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)649 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
650 {
651 int ret;
652
653 ret = smu_cmn_send_smc_msg_with_param(smu,
654 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
655 if (ret)
656 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
657
658 return ret;
659 }
660
smu_v13_0_set_driver_table_location(struct smu_context * smu)661 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
662 {
663 struct smu_table *driver_table = &smu->smu_table.driver_table;
664 int ret = 0;
665
666 if (driver_table->mc_address) {
667 ret = smu_cmn_send_smc_msg_with_param(smu,
668 SMU_MSG_SetDriverDramAddrHigh,
669 upper_32_bits(driver_table->mc_address),
670 NULL);
671 if (!ret)
672 ret = smu_cmn_send_smc_msg_with_param(smu,
673 SMU_MSG_SetDriverDramAddrLow,
674 lower_32_bits(driver_table->mc_address),
675 NULL);
676 }
677
678 return ret;
679 }
680
smu_v13_0_set_tool_table_location(struct smu_context * smu)681 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
682 {
683 int ret = 0;
684 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
685
686 if (tool_table->mc_address) {
687 ret = smu_cmn_send_smc_msg_with_param(smu,
688 SMU_MSG_SetToolsDramAddrHigh,
689 upper_32_bits(tool_table->mc_address),
690 NULL);
691 if (!ret)
692 ret = smu_cmn_send_smc_msg_with_param(smu,
693 SMU_MSG_SetToolsDramAddrLow,
694 lower_32_bits(tool_table->mc_address),
695 NULL);
696 }
697
698 return ret;
699 }
700
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)701 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
702 {
703 int ret = 0;
704
705 if (!smu->pm_enabled)
706 return ret;
707
708 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
709
710 return ret;
711 }
712
713
smu_v13_0_set_allowed_mask(struct smu_context * smu)714 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
715 {
716 struct smu_feature *feature = &smu->smu_feature;
717 int ret = 0;
718 uint32_t feature_mask[2];
719
720 mutex_lock(&feature->mutex);
721 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
722 goto failed;
723
724 bitmap_to_arr32(feature_mask, feature->allowed, 64);
725
726 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
727 feature_mask[1], NULL);
728 if (ret)
729 goto failed;
730
731 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
732 feature_mask[0], NULL);
733 if (ret)
734 goto failed;
735
736 failed:
737 mutex_unlock(&feature->mutex);
738 return ret;
739 }
740
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)741 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
742 {
743 int ret = 0;
744 struct amdgpu_device *adev = smu->adev;
745
746 switch (adev->asic_type) {
747 case CHIP_YELLOW_CARP:
748 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
749 return 0;
750 if (enable)
751 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
752 else
753 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
754 break;
755 default:
756 break;
757 }
758
759 return ret;
760 }
761
smu_v13_0_system_features_control(struct smu_context * smu,bool en)762 int smu_v13_0_system_features_control(struct smu_context *smu,
763 bool en)
764 {
765 struct smu_feature *feature = &smu->smu_feature;
766 uint32_t feature_mask[2];
767 int ret = 0;
768
769 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
770 SMU_MSG_DisableAllSmuFeatures), NULL);
771 if (ret)
772 return ret;
773
774 bitmap_zero(feature->enabled, feature->feature_num);
775 bitmap_zero(feature->supported, feature->feature_num);
776
777 if (en) {
778 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
779 if (ret)
780 return ret;
781
782 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
783 feature->feature_num);
784 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
785 feature->feature_num);
786 }
787
788 return ret;
789 }
790
smu_v13_0_notify_display_change(struct smu_context * smu)791 int smu_v13_0_notify_display_change(struct smu_context *smu)
792 {
793 int ret = 0;
794
795 if (!smu->pm_enabled)
796 return ret;
797
798 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
799 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
800 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
801
802 return ret;
803 }
804
805 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)806 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
807 enum smu_clk_type clock_select)
808 {
809 int ret = 0;
810 int clk_id;
811
812 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
813 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
814 return 0;
815
816 clk_id = smu_cmn_to_asic_specific_index(smu,
817 CMN2ASIC_MAPPING_CLK,
818 clock_select);
819 if (clk_id < 0)
820 return -EINVAL;
821
822 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
823 clk_id << 16, clock);
824 if (ret) {
825 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
826 return ret;
827 }
828
829 if (*clock != 0)
830 return 0;
831
832 /* if DC limit is zero, return AC limit */
833 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
834 clk_id << 16, clock);
835 if (ret) {
836 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
837 return ret;
838 }
839
840 return 0;
841 }
842
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)843 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
844 {
845 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
846 smu->smu_table.max_sustainable_clocks;
847 int ret = 0;
848
849 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
850 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
851 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
852 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
853 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
854 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
855
856 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
857 ret = smu_v13_0_get_max_sustainable_clock(smu,
858 &(max_sustainable_clocks->uclock),
859 SMU_UCLK);
860 if (ret) {
861 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
862 __func__);
863 return ret;
864 }
865 }
866
867 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
868 ret = smu_v13_0_get_max_sustainable_clock(smu,
869 &(max_sustainable_clocks->soc_clock),
870 SMU_SOCCLK);
871 if (ret) {
872 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
873 __func__);
874 return ret;
875 }
876 }
877
878 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
879 ret = smu_v13_0_get_max_sustainable_clock(smu,
880 &(max_sustainable_clocks->dcef_clock),
881 SMU_DCEFCLK);
882 if (ret) {
883 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
884 __func__);
885 return ret;
886 }
887
888 ret = smu_v13_0_get_max_sustainable_clock(smu,
889 &(max_sustainable_clocks->display_clock),
890 SMU_DISPCLK);
891 if (ret) {
892 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
893 __func__);
894 return ret;
895 }
896 ret = smu_v13_0_get_max_sustainable_clock(smu,
897 &(max_sustainable_clocks->phy_clock),
898 SMU_PHYCLK);
899 if (ret) {
900 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
901 __func__);
902 return ret;
903 }
904 ret = smu_v13_0_get_max_sustainable_clock(smu,
905 &(max_sustainable_clocks->pixel_clock),
906 SMU_PIXCLK);
907 if (ret) {
908 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
909 __func__);
910 return ret;
911 }
912 }
913
914 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
915 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
916
917 return 0;
918 }
919
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)920 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
921 uint32_t *power_limit)
922 {
923 int power_src;
924 int ret = 0;
925
926 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
927 return -EINVAL;
928
929 power_src = smu_cmn_to_asic_specific_index(smu,
930 CMN2ASIC_MAPPING_PWR,
931 smu->adev->pm.ac_power ?
932 SMU_POWER_SOURCE_AC :
933 SMU_POWER_SOURCE_DC);
934 if (power_src < 0)
935 return -EINVAL;
936
937 ret = smu_cmn_send_smc_msg_with_param(smu,
938 SMU_MSG_GetPptLimit,
939 power_src << 16,
940 power_limit);
941 if (ret)
942 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
943
944 return ret;
945 }
946
smu_v13_0_set_power_limit(struct smu_context * smu,uint32_t n)947 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
948 {
949 int ret = 0;
950
951 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
952 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
953 return -EOPNOTSUPP;
954 }
955
956 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
957 if (ret) {
958 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
959 return ret;
960 }
961
962 smu->current_power_limit = n;
963
964 return 0;
965 }
966
smu_v13_0_enable_thermal_alert(struct smu_context * smu)967 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
968 {
969 if (smu->smu_table.thermal_controller_type)
970 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
971
972 return 0;
973 }
974
smu_v13_0_disable_thermal_alert(struct smu_context * smu)975 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
976 {
977 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
978 }
979
convert_to_vddc(uint8_t vid)980 static uint16_t convert_to_vddc(uint8_t vid)
981 {
982 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
983 }
984
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)985 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
986 {
987 struct amdgpu_device *adev = smu->adev;
988 uint32_t vdd = 0, val_vid = 0;
989
990 if (!value)
991 return -EINVAL;
992 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
993 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
994 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
995
996 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
997
998 *value = vdd;
999
1000 return 0;
1001
1002 }
1003
1004 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1005 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1006 struct pp_display_clock_request
1007 *clock_req)
1008 {
1009 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1010 int ret = 0;
1011 enum smu_clk_type clk_select = 0;
1012 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1013
1014 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1015 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1016 switch (clk_type) {
1017 case amd_pp_dcef_clock:
1018 clk_select = SMU_DCEFCLK;
1019 break;
1020 case amd_pp_disp_clock:
1021 clk_select = SMU_DISPCLK;
1022 break;
1023 case amd_pp_pixel_clock:
1024 clk_select = SMU_PIXCLK;
1025 break;
1026 case amd_pp_phy_clock:
1027 clk_select = SMU_PHYCLK;
1028 break;
1029 case amd_pp_mem_clock:
1030 clk_select = SMU_UCLK;
1031 break;
1032 default:
1033 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1034 ret = -EINVAL;
1035 break;
1036 }
1037
1038 if (ret)
1039 goto failed;
1040
1041 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1042 return 0;
1043
1044 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1045
1046 if(clk_select == SMU_UCLK)
1047 smu->hard_min_uclk_req_from_dal = clk_freq;
1048 }
1049
1050 failed:
1051 return ret;
1052 }
1053
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1054 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1055 {
1056 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1057 return AMD_FAN_CTRL_MANUAL;
1058 else
1059 return AMD_FAN_CTRL_AUTO;
1060 }
1061
1062 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1063 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1064 {
1065 int ret = 0;
1066
1067 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1068 return 0;
1069
1070 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1071 if (ret)
1072 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1073 __func__, (auto_fan_control ? "Start" : "Stop"));
1074
1075 return ret;
1076 }
1077
1078 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1079 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1080 {
1081 struct amdgpu_device *adev = smu->adev;
1082
1083 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1084 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1085 CG_FDO_CTRL2, TMIN, 0));
1086 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1087 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1088 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1089
1090 return 0;
1091 }
1092
1093 int
smu_v13_0_set_fan_speed_percent(struct smu_context * smu,uint32_t speed)1094 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1095 {
1096 struct amdgpu_device *adev = smu->adev;
1097 uint32_t duty100, duty;
1098 uint64_t tmp64;
1099
1100 if (speed > 100)
1101 speed = 100;
1102
1103 if (smu_v13_0_auto_fan_control(smu, 0))
1104 return -EINVAL;
1105
1106 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1107 CG_FDO_CTRL1, FMAX_DUTY100);
1108 if (!duty100)
1109 return -EINVAL;
1110
1111 tmp64 = (uint64_t)speed * duty100;
1112 do_div(tmp64, 100);
1113 duty = (uint32_t)tmp64;
1114
1115 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1116 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1117 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1118
1119 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1120 }
1121
1122 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1123 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1124 uint32_t mode)
1125 {
1126 int ret = 0;
1127
1128 switch (mode) {
1129 case AMD_FAN_CTRL_NONE:
1130 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1131 break;
1132 case AMD_FAN_CTRL_MANUAL:
1133 ret = smu_v13_0_auto_fan_control(smu, 0);
1134 break;
1135 case AMD_FAN_CTRL_AUTO:
1136 ret = smu_v13_0_auto_fan_control(smu, 1);
1137 break;
1138 default:
1139 break;
1140 }
1141
1142 if (ret) {
1143 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1144 return -EINVAL;
1145 }
1146
1147 return ret;
1148 }
1149
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1150 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1151 uint32_t speed)
1152 {
1153 struct amdgpu_device *adev = smu->adev;
1154 int ret;
1155 uint32_t tach_period, crystal_clock_freq;
1156
1157 if (!speed)
1158 return -EINVAL;
1159
1160 ret = smu_v13_0_auto_fan_control(smu, 0);
1161 if (ret)
1162 return ret;
1163
1164 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1165 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1166 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1167 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1168 CG_TACH_CTRL, TARGET_PERIOD,
1169 tach_period));
1170
1171 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1172
1173 return ret;
1174 }
1175
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1176 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1177 uint32_t pstate)
1178 {
1179 int ret = 0;
1180 ret = smu_cmn_send_smc_msg_with_param(smu,
1181 SMU_MSG_SetXgmiMode,
1182 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1183 NULL);
1184 return ret;
1185 }
1186
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1187 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1188 struct amdgpu_irq_src *source,
1189 unsigned tyep,
1190 enum amdgpu_interrupt_state state)
1191 {
1192 struct smu_context *smu = &adev->smu;
1193 uint32_t low, high;
1194 uint32_t val = 0;
1195
1196 switch (state) {
1197 case AMDGPU_IRQ_STATE_DISABLE:
1198 /* For THM irqs */
1199 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1200 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1201 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1202 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1203
1204 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1205
1206 /* For MP1 SW irqs */
1207 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1208 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1209 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1210
1211 break;
1212 case AMDGPU_IRQ_STATE_ENABLE:
1213 /* For THM irqs */
1214 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1215 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1216 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1217 smu->thermal_range.software_shutdown_temp);
1218
1219 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1220 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1221 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1222 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1223 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1224 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1225 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1226 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1227 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1228
1229 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1230 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1231 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1232 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1233
1234 /* For MP1 SW irqs */
1235 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1236 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1237 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1238 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1239
1240 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1241 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1242 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1243
1244 break;
1245 default:
1246 break;
1247 }
1248
1249 return 0;
1250 }
1251
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1252 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1253 {
1254 return smu_cmn_send_smc_msg(smu,
1255 SMU_MSG_ReenableAcDcInterrupt,
1256 NULL);
1257 }
1258
1259 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1260 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1261 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1262
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1263 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1264 struct amdgpu_irq_src *source,
1265 struct amdgpu_iv_entry *entry)
1266 {
1267 struct smu_context *smu = &adev->smu;
1268 uint32_t client_id = entry->client_id;
1269 uint32_t src_id = entry->src_id;
1270 /*
1271 * ctxid is used to distinguish different
1272 * events for SMCToHost interrupt.
1273 */
1274 uint32_t ctxid = entry->src_data[0];
1275 uint32_t data;
1276
1277 if (client_id == SOC15_IH_CLIENTID_THM) {
1278 switch (src_id) {
1279 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1280 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1281 /*
1282 * SW CTF just occurred.
1283 * Try to do a graceful shutdown to prevent further damage.
1284 */
1285 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1286 orderly_poweroff(true);
1287 break;
1288 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1289 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1290 break;
1291 default:
1292 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1293 src_id);
1294 break;
1295 }
1296 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1297 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1298 /*
1299 * HW CTF just occurred. Shutdown to prevent further damage.
1300 */
1301 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1302 orderly_poweroff(true);
1303 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1304 if (src_id == 0xfe) {
1305 /* ACK SMUToHost interrupt */
1306 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1307 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1308 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1309
1310 switch (ctxid) {
1311 case 0x3:
1312 dev_dbg(adev->dev, "Switched to AC mode!\n");
1313 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1314 break;
1315 case 0x4:
1316 dev_dbg(adev->dev, "Switched to DC mode!\n");
1317 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1318 break;
1319 case 0x7:
1320 /*
1321 * Increment the throttle interrupt counter
1322 */
1323 atomic64_inc(&smu->throttle_int_counter);
1324
1325 if (!atomic_read(&adev->throttling_logging_enabled))
1326 return 0;
1327
1328 if (__ratelimit(&adev->throttling_logging_rs))
1329 schedule_work(&smu->throttling_logging_work);
1330
1331 break;
1332 }
1333 }
1334 }
1335
1336 return 0;
1337 }
1338
1339 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1340 {
1341 .set = smu_v13_0_set_irq_state,
1342 .process = smu_v13_0_irq_process,
1343 };
1344
smu_v13_0_register_irq_handler(struct smu_context * smu)1345 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1346 {
1347 struct amdgpu_device *adev = smu->adev;
1348 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1349 int ret = 0;
1350
1351 irq_src->num_types = 1;
1352 irq_src->funcs = &smu_v13_0_irq_funcs;
1353
1354 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1355 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1356 irq_src);
1357 if (ret)
1358 return ret;
1359
1360 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1361 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1362 irq_src);
1363 if (ret)
1364 return ret;
1365
1366 /* Register CTF(GPIO_19) interrupt */
1367 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1368 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1369 irq_src);
1370 if (ret)
1371 return ret;
1372
1373 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1374 0xfe,
1375 irq_src);
1376 if (ret)
1377 return ret;
1378
1379 return ret;
1380 }
1381
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1382 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1383 struct pp_smu_nv_clock_table *max_clocks)
1384 {
1385 struct smu_table_context *table_context = &smu->smu_table;
1386 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1387
1388 if (!max_clocks || !table_context->max_sustainable_clocks)
1389 return -EINVAL;
1390
1391 sustainable_clocks = table_context->max_sustainable_clocks;
1392
1393 max_clocks->dcfClockInKhz =
1394 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1395 max_clocks->displayClockInKhz =
1396 (unsigned int) sustainable_clocks->display_clock * 1000;
1397 max_clocks->phyClockInKhz =
1398 (unsigned int) sustainable_clocks->phy_clock * 1000;
1399 max_clocks->pixelClockInKhz =
1400 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1401 max_clocks->uClockInKhz =
1402 (unsigned int) sustainable_clocks->uclock * 1000;
1403 max_clocks->socClockInKhz =
1404 (unsigned int) sustainable_clocks->soc_clock * 1000;
1405 max_clocks->dscClockInKhz = 0;
1406 max_clocks->dppClockInKhz = 0;
1407 max_clocks->fabricClockInKhz = 0;
1408
1409 return 0;
1410 }
1411
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1412 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1413 {
1414 int ret = 0;
1415
1416 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1417
1418 return ret;
1419 }
1420
smu_v13_0_mode1_reset(struct smu_context * smu)1421 int smu_v13_0_mode1_reset(struct smu_context *smu)
1422 {
1423 u32 smu_version;
1424 int ret = 0;
1425 /*
1426 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1427 */
1428 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1429 if (smu_version < 0x00440700)
1430 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1431 else
1432 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1433
1434 if (!ret)
1435 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1436
1437 return ret;
1438 }
1439
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1440 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1441 uint64_t event_arg)
1442 {
1443 int ret = 0;
1444
1445 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1446 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1447
1448 return ret;
1449 }
1450
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1451 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1452 uint64_t event_arg)
1453 {
1454 int ret = -EINVAL;
1455
1456 switch (event) {
1457 case SMU_EVENT_RESET_COMPLETE:
1458 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1459 break;
1460 default:
1461 break;
1462 }
1463
1464 return ret;
1465 }
1466
smu_v13_0_mode2_reset(struct smu_context * smu)1467 int smu_v13_0_mode2_reset(struct smu_context *smu)
1468 {
1469 int ret;
1470
1471 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1472 SMU_RESET_MODE_2, NULL);
1473 /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1474 if (!ret)
1475 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1476
1477 return ret;
1478 }
1479
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1480 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1481 uint32_t *min, uint32_t *max)
1482 {
1483 int ret = 0, clk_id = 0;
1484 uint32_t param = 0;
1485 uint32_t clock_limit;
1486
1487 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1488 switch (clk_type) {
1489 case SMU_MCLK:
1490 case SMU_UCLK:
1491 clock_limit = smu->smu_table.boot_values.uclk;
1492 break;
1493 case SMU_GFXCLK:
1494 case SMU_SCLK:
1495 clock_limit = smu->smu_table.boot_values.gfxclk;
1496 break;
1497 case SMU_SOCCLK:
1498 clock_limit = smu->smu_table.boot_values.socclk;
1499 break;
1500 default:
1501 clock_limit = 0;
1502 break;
1503 }
1504
1505 /* clock in Mhz unit */
1506 if (min)
1507 *min = clock_limit / 100;
1508 if (max)
1509 *max = clock_limit / 100;
1510
1511 return 0;
1512 }
1513
1514 clk_id = smu_cmn_to_asic_specific_index(smu,
1515 CMN2ASIC_MAPPING_CLK,
1516 clk_type);
1517 if (clk_id < 0) {
1518 ret = -EINVAL;
1519 goto failed;
1520 }
1521 param = (clk_id & 0xffff) << 16;
1522
1523 if (max) {
1524 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1525 if (ret)
1526 goto failed;
1527 }
1528
1529 if (min) {
1530 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1531 if (ret)
1532 goto failed;
1533 }
1534
1535 failed:
1536 return ret;
1537 }
1538
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1539 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1540 enum smu_clk_type clk_type,
1541 uint32_t min,
1542 uint32_t max)
1543 {
1544 struct amdgpu_device *adev = smu->adev;
1545 int ret = 0, clk_id = 0;
1546 uint32_t param;
1547
1548 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1549 return 0;
1550
1551 clk_id = smu_cmn_to_asic_specific_index(smu,
1552 CMN2ASIC_MAPPING_CLK,
1553 clk_type);
1554 if (clk_id < 0)
1555 return clk_id;
1556
1557 if (clk_type == SMU_GFXCLK)
1558 amdgpu_gfx_off_ctrl(adev, false);
1559
1560 if (max > 0) {
1561 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1562 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1563 param, NULL);
1564 if (ret)
1565 goto out;
1566 }
1567
1568 if (min > 0) {
1569 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1570 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1571 param, NULL);
1572 if (ret)
1573 goto out;
1574 }
1575
1576 out:
1577 if (clk_type == SMU_GFXCLK)
1578 amdgpu_gfx_off_ctrl(adev, true);
1579
1580 return ret;
1581 }
1582
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1583 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1584 enum smu_clk_type clk_type,
1585 uint32_t min,
1586 uint32_t max)
1587 {
1588 int ret = 0, clk_id = 0;
1589 uint32_t param;
1590
1591 if (min <= 0 && max <= 0)
1592 return -EINVAL;
1593
1594 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1595 return 0;
1596
1597 clk_id = smu_cmn_to_asic_specific_index(smu,
1598 CMN2ASIC_MAPPING_CLK,
1599 clk_type);
1600 if (clk_id < 0)
1601 return clk_id;
1602
1603 if (max > 0) {
1604 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1605 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1606 param, NULL);
1607 if (ret)
1608 return ret;
1609 }
1610
1611 if (min > 0) {
1612 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1613 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1614 param, NULL);
1615 if (ret)
1616 return ret;
1617 }
1618
1619 return ret;
1620 }
1621
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1622 int smu_v13_0_set_performance_level(struct smu_context *smu,
1623 enum amd_dpm_forced_level level)
1624 {
1625 struct smu_13_0_dpm_context *dpm_context =
1626 smu->smu_dpm.dpm_context;
1627 struct smu_13_0_dpm_table *gfx_table =
1628 &dpm_context->dpm_tables.gfx_table;
1629 struct smu_13_0_dpm_table *mem_table =
1630 &dpm_context->dpm_tables.uclk_table;
1631 struct smu_13_0_dpm_table *soc_table =
1632 &dpm_context->dpm_tables.soc_table;
1633 struct smu_umd_pstate_table *pstate_table =
1634 &smu->pstate_table;
1635 struct amdgpu_device *adev = smu->adev;
1636 uint32_t sclk_min = 0, sclk_max = 0;
1637 uint32_t mclk_min = 0, mclk_max = 0;
1638 uint32_t socclk_min = 0, socclk_max = 0;
1639 int ret = 0;
1640
1641 switch (level) {
1642 case AMD_DPM_FORCED_LEVEL_HIGH:
1643 sclk_min = sclk_max = gfx_table->max;
1644 mclk_min = mclk_max = mem_table->max;
1645 socclk_min = socclk_max = soc_table->max;
1646 break;
1647 case AMD_DPM_FORCED_LEVEL_LOW:
1648 sclk_min = sclk_max = gfx_table->min;
1649 mclk_min = mclk_max = mem_table->min;
1650 socclk_min = socclk_max = soc_table->min;
1651 break;
1652 case AMD_DPM_FORCED_LEVEL_AUTO:
1653 sclk_min = gfx_table->min;
1654 sclk_max = gfx_table->max;
1655 mclk_min = mem_table->min;
1656 mclk_max = mem_table->max;
1657 socclk_min = soc_table->min;
1658 socclk_max = soc_table->max;
1659 break;
1660 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1661 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1662 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1663 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1664 break;
1665 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1666 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1667 break;
1668 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1669 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1670 break;
1671 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1672 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1673 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1674 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1675 break;
1676 case AMD_DPM_FORCED_LEVEL_MANUAL:
1677 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1678 return 0;
1679 default:
1680 dev_err(adev->dev, "Invalid performance level %d\n", level);
1681 return -EINVAL;
1682 }
1683
1684 mclk_min = mclk_max = 0;
1685 socclk_min = socclk_max = 0;
1686
1687 if (sclk_min && sclk_max) {
1688 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1689 SMU_GFXCLK,
1690 sclk_min,
1691 sclk_max);
1692 if (ret)
1693 return ret;
1694
1695 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1696 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1697 }
1698
1699 if (mclk_min && mclk_max) {
1700 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1701 SMU_MCLK,
1702 mclk_min,
1703 mclk_max);
1704 if (ret)
1705 return ret;
1706
1707 pstate_table->uclk_pstate.curr.min = mclk_min;
1708 pstate_table->uclk_pstate.curr.max = mclk_max;
1709 }
1710
1711 if (socclk_min && socclk_max) {
1712 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1713 SMU_SOCCLK,
1714 socclk_min,
1715 socclk_max);
1716 if (ret)
1717 return ret;
1718
1719 pstate_table->socclk_pstate.curr.min = socclk_min;
1720 pstate_table->socclk_pstate.curr.max = socclk_max;
1721 }
1722
1723 return ret;
1724 }
1725
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1726 int smu_v13_0_set_power_source(struct smu_context *smu,
1727 enum smu_power_src_type power_src)
1728 {
1729 int pwr_source;
1730
1731 pwr_source = smu_cmn_to_asic_specific_index(smu,
1732 CMN2ASIC_MAPPING_PWR,
1733 (uint32_t)power_src);
1734 if (pwr_source < 0)
1735 return -EINVAL;
1736
1737 return smu_cmn_send_smc_msg_with_param(smu,
1738 SMU_MSG_NotifyPowerSource,
1739 pwr_source,
1740 NULL);
1741 }
1742
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1743 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1744 enum smu_clk_type clk_type,
1745 uint16_t level,
1746 uint32_t *value)
1747 {
1748 int ret = 0, clk_id = 0;
1749 uint32_t param;
1750
1751 if (!value)
1752 return -EINVAL;
1753
1754 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1755 return 0;
1756
1757 clk_id = smu_cmn_to_asic_specific_index(smu,
1758 CMN2ASIC_MAPPING_CLK,
1759 clk_type);
1760 if (clk_id < 0)
1761 return clk_id;
1762
1763 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1764
1765 ret = smu_cmn_send_smc_msg_with_param(smu,
1766 SMU_MSG_GetDpmFreqByIndex,
1767 param,
1768 value);
1769 if (ret)
1770 return ret;
1771
1772 /*
1773 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1774 * now, we un-support it
1775 */
1776 *value = *value & 0x7fffffff;
1777
1778 return ret;
1779 }
1780
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1781 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1782 enum smu_clk_type clk_type,
1783 uint32_t *value)
1784 {
1785 int ret;
1786
1787 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1788 /* FW returns 0 based max level, increment by one */
1789 if (!ret && value)
1790 ++(*value);
1791
1792 return ret;
1793 }
1794
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)1795 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1796 enum smu_clk_type clk_type,
1797 struct smu_13_0_dpm_table *single_dpm_table)
1798 {
1799 int ret = 0;
1800 uint32_t clk;
1801 int i;
1802
1803 ret = smu_v13_0_get_dpm_level_count(smu,
1804 clk_type,
1805 &single_dpm_table->count);
1806 if (ret) {
1807 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1808 return ret;
1809 }
1810
1811 for (i = 0; i < single_dpm_table->count; i++) {
1812 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1813 clk_type,
1814 i,
1815 &clk);
1816 if (ret) {
1817 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1818 return ret;
1819 }
1820
1821 single_dpm_table->dpm_levels[i].value = clk;
1822 single_dpm_table->dpm_levels[i].enabled = true;
1823
1824 if (i == 0)
1825 single_dpm_table->min = clk;
1826 else if (i == single_dpm_table->count - 1)
1827 single_dpm_table->max = clk;
1828 }
1829
1830 return 0;
1831 }
1832
smu_v13_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)1833 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1834 enum smu_clk_type clk_type,
1835 uint32_t *min_value,
1836 uint32_t *max_value)
1837 {
1838 uint32_t level_count = 0;
1839 int ret = 0;
1840
1841 if (!min_value && !max_value)
1842 return -EINVAL;
1843
1844 if (min_value) {
1845 /* by default, level 0 clock value as min value */
1846 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1847 clk_type,
1848 0,
1849 min_value);
1850 if (ret)
1851 return ret;
1852 }
1853
1854 if (max_value) {
1855 ret = smu_v13_0_get_dpm_level_count(smu,
1856 clk_type,
1857 &level_count);
1858 if (ret)
1859 return ret;
1860
1861 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1862 clk_type,
1863 level_count - 1,
1864 max_value);
1865 if (ret)
1866 return ret;
1867 }
1868
1869 return ret;
1870 }
1871
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)1872 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1873 {
1874 struct amdgpu_device *adev = smu->adev;
1875
1876 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1877 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1878 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1879 }
1880
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)1881 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1882 {
1883 uint32_t width_level;
1884
1885 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1886 if (width_level > LINK_WIDTH_MAX)
1887 width_level = 0;
1888
1889 return link_width[width_level];
1890 }
1891
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)1892 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1893 {
1894 struct amdgpu_device *adev = smu->adev;
1895
1896 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1897 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1898 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1899 }
1900
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)1901 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1902 {
1903 uint32_t speed_level;
1904
1905 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1906 if (speed_level > LINK_SPEED_MAX)
1907 speed_level = 0;
1908
1909 return link_speed[speed_level];
1910 }
1911
1912