| /drivers/net/ethernet/mediatek/ |
| D | mtk_ppe.c | 12 static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_w32() argument
14 writel(val, ppe->base + reg); in ppe_w32()
17 static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg) in ppe_r32() argument
19 return readl(ppe->base + reg); in ppe_r32()
22 static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set) in ppe_m32() argument
26 val = ppe_r32(ppe, reg); in ppe_m32()
29 ppe_w32(ppe, reg, val); in ppe_m32()
34 static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_set() argument
36 return ppe_m32(ppe, reg, 0, val); in ppe_set()
39 static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_clear() argument
[all …]
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| D | mtk_ppe.h | 249 int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
251 int mtk_ppe_start(struct mtk_ppe *ppe);
252 int mtk_ppe_stop(struct mtk_ppe *ppe);
255 mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash) in mtk_foe_entry_clear() argument
257 ppe->foe_table[hash].ib1 = 0; in mtk_foe_entry_clear()
262 mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash) in mtk_foe_entry_timestamp() argument
264 u32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1); in mtk_foe_entry_timestamp()
284 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
286 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);
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| D | mtk_ppe_debugfs.c | 79 struct mtk_ppe *ppe = m->private; in mtk_ppe_debugfs_foe_show() local
83 struct mtk_foe_entry *entry = &ppe->foe_table[i]; in mtk_ppe_debugfs_foe_show()
191 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe) in mtk_ppe_debugfs_init() argument
213 debugfs_create_file("entries", S_IRUGO, root, ppe, &fops_all); in mtk_ppe_debugfs_init()
214 debugfs_create_file("bind", S_IRUGO, root, ppe, &fops_bind); in mtk_ppe_debugfs_init()
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| D | mtk_ppe_offload.c | 339 hash = mtk_foe_entry_commit(ð->ppe, &foe, timestamp); in mtk_flow_offload_replace()
353 mtk_foe_entry_clear(ð->ppe, hash); in mtk_flow_offload_replace()
369 mtk_foe_entry_clear(ð->ppe, entry->hash); in mtk_flow_offload_destroy()
389 timestamp = mtk_foe_entry_timestamp(ð->ppe, entry->hash); in mtk_flow_offload_stats()
445 if (!eth->ppe.foe_table) in mtk_eth_setup_tc_block()
495 if (!eth->ppe.foe_table) in mtk_eth_offload_init()
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| D | mtk_eth_soc.h | 975 struct mtk_ppe ppe; member
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| D | mtk_eth_soc.c | 2339 if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) in mtk_open()
2413 mtk_ppe_stop(ð->ppe); in mtk_stop()
3236 err = mtk_ppe_init(ð->ppe, eth->dev, in mtk_probe()
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| /drivers/staging/media/tegra-vde/ |
| D | vde.h | 31 void __iomem *ppe; member
86 if (vde->ppe == base) in tegra_vde_reg_base_name()
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| D | vde.c | 313 tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); in tegra_vde_setup_hw_context()
314 tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); in tegra_vde_setup_hw_context()
973 vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe"); in tegra_vde_probe()
974 if (IS_ERR(vde->ppe)) in tegra_vde_probe()
975 return PTR_ERR(vde->ppe); in tegra_vde_probe()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 696 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
700 vp_width = pipe_src_param.viewport_width_c / ppe; in get_surf_rq_param()
705 vp_width = pipe_src_param.viewport_width / ppe; in get_surf_rq_param()
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| D | display_rq_dlg_calc_20.c | 696 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
700 vp_width = pipe_src_param.viewport_width_c / ppe; in get_surf_rq_param()
705 vp_width = pipe_src_param.viewport_width / ppe; in get_surf_rq_param()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 567 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
625 vp_width = pipe_src_param.viewport_width_c / ppe; in get_surf_rq_param()
630 vp_width = pipe_src_param.viewport_width / ppe; in get_surf_rq_param()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 705 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
709 vp_width = pipe_param->src.viewport_width_c / ppe; in get_surf_rq_param()
714 vp_width = pipe_param->src.viewport_width / ppe; in get_surf_rq_param()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 751 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
755 vp_width = pipe_param->src.viewport_width_c / ppe; in get_surf_rq_param()
761 vp_width = pipe_param->src.viewport_width / ppe; in get_surf_rq_param()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 760 unsigned int ppe = mode_422 ? 2 : 1; in get_surf_rq_param() local
764 vp_width = pipe_param->src.viewport_width_c / ppe; in get_surf_rq_param()
770 vp_width = pipe_param->src.viewport_width / ppe; in get_surf_rq_param()
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| /drivers/net/wireless/intel/iwlwifi/mvm/ |
| D | mac80211.c | 2007 static u8 iwl_mvm_he_get_ppe_val(u8 *ppe, u8 ppe_pos_bit) in iwl_mvm_he_get_ppe_val() argument
2015 return (ppe[byte_num] >> bit_num) & in iwl_mvm_he_get_ppe_val()
2026 res = (ppe[byte_num + 1] & in iwl_mvm_he_get_ppe_val()
2029 res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); in iwl_mvm_he_get_ppe_val()
2130 u8 *ppe = &sta->deflink.he_cap.ppe_thres[0]; in iwl_mvm_cfg_he_sta() local
2155 iwl_mvm_he_get_ppe_val(ppe, in iwl_mvm_cfg_he_sta()
2160 iwl_mvm_he_get_ppe_val(ppe, in iwl_mvm_cfg_he_sta()
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