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Searched refs:reg_index (Results 1 – 25 of 35) sorted by relevance

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/drivers/pinctrl/nomadik/
Dpinctrl-nomadik.h31 .reg_index = altc1_ri,\
36 .reg_index = altc2_ri,\
41 .reg_index = altc3_ri,\
46 .reg_index = altc4_ri,\
80 u8 reg_index:2; member
Dpinctrl-nomadik.c482 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; in nmk_prcm_altcx_set_mode()
511 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; in nmk_prcm_altcx_set_mode()
522 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; in nmk_prcm_altcx_set_mode()
598 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; in nmk_prcm_gpiocr_get_mode()
/drivers/media/tuners/
Dqm1d1c0042.c42 static int reg_index; variable
341 for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS; in qm1d1c0042_init()
342 reg_index++) { in qm1d1c0042_init()
343 if (val == reg_initval[reg_index][0x00]) in qm1d1c0042_init()
346 if (reg_index >= QM1D1C0042_NUM_REG_ROWS) { in qm1d1c0042_init()
350 memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS); in qm1d1c0042_init()
/drivers/power/supply/
Dbq27xxx_battery.c1107 static inline int bq27xxx_read(struct bq27xxx_device_info *di, int reg_index, in bq27xxx_read() argument
1112 if (!di || di->regs[reg_index] == INVALID_REG_ADDR) in bq27xxx_read()
1115 ret = di->bus.read(di, di->regs[reg_index], single); in bq27xxx_read()
1118 di->regs[reg_index], reg_index); in bq27xxx_read()
1123 static inline int bq27xxx_write(struct bq27xxx_device_info *di, int reg_index, in bq27xxx_write() argument
1128 if (!di || di->regs[reg_index] == INVALID_REG_ADDR) in bq27xxx_write()
1134 ret = di->bus.write(di, di->regs[reg_index], value, single); in bq27xxx_write()
1137 di->regs[reg_index], reg_index); in bq27xxx_write()
1142 static inline int bq27xxx_read_block(struct bq27xxx_device_info *di, int reg_index, in bq27xxx_read_block() argument
1147 if (!di || di->regs[reg_index] == INVALID_REG_ADDR) in bq27xxx_read_block()
[all …]
/drivers/irqchip/
Dirq-mtk-sysirq.c32 u32 offset, reg_index, value; in mtk_sysirq_set_type() local
37 reg_index = chip_data->which_word[hwirq]; in mtk_sysirq_set_type()
41 value = readl_relaxed(base + reg_index * 4); in mtk_sysirq_set_type()
52 writel_relaxed(value, base + reg_index * 4); in mtk_sysirq_set_type()
Dqcom-pdc.c321 u32 irq_index, reg_index, val; in pdc_setup_pin_mapping() local
352 reg_index = (i + pdc_region[n].pin_base) >> 5; in pdc_setup_pin_mapping()
354 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index); in pdc_setup_pin_mapping()
356 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); in pdc_setup_pin_mapping()
/drivers/media/dvb-frontends/
Dstv0900_core.c882 reg_index, in stv0900_activate_s2_modcod() local
894 reg_index = MODCODLSTF - mod_code / 2; in stv0900_activate_s2_modcod()
916 stv0900_write_reg(intp, reg_index, in stv0900_activate_s2_modcod()
919 stv0900_write_reg(intp, reg_index, in stv0900_activate_s2_modcod()
924 for (reg_index = 0; reg_index < 7; reg_index++) in stv0900_activate_s2_modcod()
925 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff); in stv0900_activate_s2_modcod()
929 for (reg_index = 0; reg_index < 8; reg_index++) in stv0900_activate_s2_modcod()
930 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc); in stv0900_activate_s2_modcod()
939 u32 reg_index; in stv0900_activate_s2_modcod_single() local
946 for (reg_index = 0; reg_index < 13; reg_index++) in stv0900_activate_s2_modcod_single()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_audio.c58 uint32_t reg_index, in write_indirect_azalia_reg() argument
65 AZALIA_ENDPOINT_REG_INDEX, reg_index); in write_indirect_azalia_reg()
72 reg_index, reg_data); in write_indirect_azalia_reg()
75 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) in read_indirect_azalia_reg() argument
83 AZALIA_ENDPOINT_REG_INDEX, reg_index); in read_indirect_azalia_reg()
89 reg_index, value); in read_indirect_azalia_reg()
/drivers/gpu/drm/radeon/
Dclearstate_defs.h35 const unsigned int reg_index; member
Dsumo_dpm.c476 u32 reg_index = index / 4; in sumo_set_divider_value() local
480 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
582 u32 reg_index = index / 4; in sumo_power_level_enable() local
586 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
589 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
592 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
595 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
/drivers/gpu/drm/amd/amdgpu/
Dclearstate_defs.h35 const unsigned int reg_index; member
Damdgpu_psp.h402 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
/drivers/scsi/libsas/
Dsas_host_smp.c114 u8 reg_type, u8 reg_index, u8 reg_count, in sas_host_smp_write_gpio() argument
125 written = i->dft->lldd_write_gpio(sas_ha, reg_type, reg_index, in sas_host_smp_write_gpio()
/drivers/platform/x86/
Dpmc_atom.c268 static void pmc_dev_state_print(struct seq_file *s, int reg_index, in pmc_dev_state_print() argument
272 int offset = PMC_REG_BIT_WIDTH * reg_index; in pmc_dev_state_print()
/drivers/scsi/mvsas/
Dmv_sas.h158 u8 reg_index, u8 reg_count, u8 *write_data);
462 int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
Dmv_94xx.c1042 u8 reg_type, u8 reg_index, in mvs_94xx_gpio_write() argument
1050 if (reg_index == 0) in mvs_94xx_gpio_write()
1113 if (reg_index + reg_count > mvs_prv->n_host) in mvs_94xx_gpio_write()
1117 struct mvs_info *mvi = mvs_prv->mvi[i+reg_index]; in mvs_94xx_gpio_write()
Dmv_sas.c2091 int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index, in mvs_gpio_write() argument
2099 reg_index, reg_count, write_data); in mvs_gpio_write()
/drivers/regulator/
Dda9121-regulator.c119 int reg_index; /* index for status/event/mask register selection */ member
574 int reg_idx = item->reg_index; in da9121_status_poll_on()
645 int reg_idx = item->reg_index; in da9121_irq_handler()
/drivers/scsi/isci/
Dhost.c2753 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data) in sci_write_gpio_tx_gp() argument
2758 if (reg_index == 0) in sci_write_gpio_tx_gp()
2769 write_data, reg_index, in sci_write_gpio_tx_gp()
2789 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index, in isci_gpio_write() argument
2797 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data); in isci_gpio_write()
Dhost.h514 int isci_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
/drivers/scsi/hisi_sas/
Dhisi_sas.h349 u8 reg_index, u8 reg_count, u8 *write_data);
Dhisi_sas_v3_hw.c2622 u8 reg_index, u8 reg_count, u8 *write_data) in write_gpio_v3_hw() argument
2630 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { in write_gpio_v3_hw()
2632 reg_index, reg_index + reg_count - 1); in write_gpio_v3_hw()
2638 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, in write_gpio_v3_hw()
Dhisi_sas_main.c2213 u8 reg_index, u8 reg_count, u8 *write_data) in hisi_sas_write_gpio() argument
2221 reg_index, reg_count, write_data); in hisi_sas_write_gpio()
/drivers/net/ethernet/intel/igb/
Digb_ethtool.c2795 u16 reg_index) in igb_clear_etype_filter_regs() argument
2798 u32 etqf = rd32(E1000_ETQF(reg_index)); in igb_clear_etype_filter_regs()
2804 wr32(E1000_ETQF(reg_index), etqf); in igb_clear_etype_filter_regs()
2806 adapter->etype_bitmap[reg_index] = false; in igb_clear_etype_filter_regs()
/drivers/net/ethernet/intel/igc/
Digc_main.c3545 u16 reg_index) in igc_del_flex_filter() argument
3554 if (reg_index > 8) { in igc_del_flex_filter()
3557 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8)); in igc_del_flex_filter()
3562 wufc &= ~(IGC_WUFC_FLX0 << reg_index); in igc_del_flex_filter()

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