1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 /* ethtool support for igb */
5
6 #include <linux/vmalloc.h>
7 #include <linux/netdevice.h>
8 #include <linux/pci.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/if_ether.h>
12 #include <linux/ethtool.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/highmem.h>
17 #include <linux/mdio.h>
18
19 #include "igb.h"
20
21 struct igb_stats {
22 char stat_string[ETH_GSTRING_LEN];
23 int sizeof_stat;
24 int stat_offset;
25 };
26
27 #define IGB_STAT(_name, _stat) { \
28 .stat_string = _name, \
29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \
30 .stat_offset = offsetof(struct igb_adapter, _stat) \
31 }
32 static const struct igb_stats igb_gstrings_stats[] = {
33 IGB_STAT("rx_packets", stats.gprc),
34 IGB_STAT("tx_packets", stats.gptc),
35 IGB_STAT("rx_bytes", stats.gorc),
36 IGB_STAT("tx_bytes", stats.gotc),
37 IGB_STAT("rx_broadcast", stats.bprc),
38 IGB_STAT("tx_broadcast", stats.bptc),
39 IGB_STAT("rx_multicast", stats.mprc),
40 IGB_STAT("tx_multicast", stats.mptc),
41 IGB_STAT("multicast", stats.mprc),
42 IGB_STAT("collisions", stats.colc),
43 IGB_STAT("rx_crc_errors", stats.crcerrs),
44 IGB_STAT("rx_no_buffer_count", stats.rnbc),
45 IGB_STAT("rx_missed_errors", stats.mpc),
46 IGB_STAT("tx_aborted_errors", stats.ecol),
47 IGB_STAT("tx_carrier_errors", stats.tncrs),
48 IGB_STAT("tx_window_errors", stats.latecol),
49 IGB_STAT("tx_abort_late_coll", stats.latecol),
50 IGB_STAT("tx_deferred_ok", stats.dc),
51 IGB_STAT("tx_single_coll_ok", stats.scc),
52 IGB_STAT("tx_multi_coll_ok", stats.mcc),
53 IGB_STAT("tx_timeout_count", tx_timeout_count),
54 IGB_STAT("rx_long_length_errors", stats.roc),
55 IGB_STAT("rx_short_length_errors", stats.ruc),
56 IGB_STAT("rx_align_errors", stats.algnerrc),
57 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
59 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
61 IGB_STAT("tx_flow_control_xon", stats.xontxc),
62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
63 IGB_STAT("rx_long_byte_count", stats.gorc),
64 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
65 IGB_STAT("tx_smbus", stats.mgptc),
66 IGB_STAT("rx_smbus", stats.mgprc),
67 IGB_STAT("dropped_smbus", stats.mgpdc),
68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
75 };
76
77 #define IGB_NETDEV_STAT(_net_stat) { \
78 .stat_string = __stringify(_net_stat), \
79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \
80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
81 }
82 static const struct igb_stats igb_gstrings_net_stats[] = {
83 IGB_NETDEV_STAT(rx_errors),
84 IGB_NETDEV_STAT(tx_errors),
85 IGB_NETDEV_STAT(tx_dropped),
86 IGB_NETDEV_STAT(rx_length_errors),
87 IGB_NETDEV_STAT(rx_over_errors),
88 IGB_NETDEV_STAT(rx_frame_errors),
89 IGB_NETDEV_STAT(rx_fifo_errors),
90 IGB_NETDEV_STAT(tx_fifo_errors),
91 IGB_NETDEV_STAT(tx_heartbeat_errors)
92 };
93
94 #define IGB_GLOBAL_STATS_LEN \
95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
96 #define IGB_NETDEV_STATS_LEN \
97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
98 #define IGB_RX_QUEUE_STATS_LEN \
99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
100
101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
102
103 #define IGB_QUEUE_STATS_LEN \
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
105 IGB_RX_QUEUE_STATS_LEN) + \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
107 IGB_TX_QUEUE_STATS_LEN))
108 #define IGB_STATS_LEN \
109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
110
111 enum igb_diagnostics_results {
112 TEST_REG = 0,
113 TEST_EEP,
114 TEST_IRQ,
115 TEST_LOOP,
116 TEST_LINK
117 };
118
119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
120 [TEST_REG] = "Register test (offline)",
121 [TEST_EEP] = "Eeprom test (offline)",
122 [TEST_IRQ] = "Interrupt test (offline)",
123 [TEST_LOOP] = "Loopback test (offline)",
124 [TEST_LINK] = "Link test (on/offline)"
125 };
126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
127
128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
130 "legacy-rx",
131 };
132
133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)
134
igb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)135 static int igb_get_link_ksettings(struct net_device *netdev,
136 struct ethtool_link_ksettings *cmd)
137 {
138 struct igb_adapter *adapter = netdev_priv(netdev);
139 struct e1000_hw *hw = &adapter->hw;
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
142 u32 status;
143 u32 speed;
144 u32 supported, advertising;
145
146 status = pm_runtime_suspended(&adapter->pdev->dev) ?
147 0 : rd32(E1000_STATUS);
148 if (hw->phy.media_type == e1000_media_type_copper) {
149
150 supported = (SUPPORTED_10baseT_Half |
151 SUPPORTED_10baseT_Full |
152 SUPPORTED_100baseT_Half |
153 SUPPORTED_100baseT_Full |
154 SUPPORTED_1000baseT_Full|
155 SUPPORTED_Autoneg |
156 SUPPORTED_TP |
157 SUPPORTED_Pause);
158 advertising = ADVERTISED_TP;
159
160 if (hw->mac.autoneg == 1) {
161 advertising |= ADVERTISED_Autoneg;
162 /* the e1000 autoneg seems to match ethtool nicely */
163 advertising |= hw->phy.autoneg_advertised;
164 }
165
166 cmd->base.port = PORT_TP;
167 cmd->base.phy_address = hw->phy.addr;
168 } else {
169 supported = (SUPPORTED_FIBRE |
170 SUPPORTED_1000baseKX_Full |
171 SUPPORTED_Autoneg |
172 SUPPORTED_Pause);
173 advertising = (ADVERTISED_FIBRE |
174 ADVERTISED_1000baseKX_Full);
175 if (hw->mac.type == e1000_i354) {
176 if ((hw->device_id ==
177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
178 !(status & E1000_STATUS_2P5_SKU_OVER)) {
179 supported |= SUPPORTED_2500baseX_Full;
180 supported &= ~SUPPORTED_1000baseKX_Full;
181 advertising |= ADVERTISED_2500baseX_Full;
182 advertising &= ~ADVERTISED_1000baseKX_Full;
183 }
184 }
185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
186 supported |= SUPPORTED_100baseT_Full;
187 advertising |= ADVERTISED_100baseT_Full;
188 }
189 if (hw->mac.autoneg == 1)
190 advertising |= ADVERTISED_Autoneg;
191
192 cmd->base.port = PORT_FIBRE;
193 }
194 if (hw->mac.autoneg != 1)
195 advertising &= ~(ADVERTISED_Pause |
196 ADVERTISED_Asym_Pause);
197
198 switch (hw->fc.requested_mode) {
199 case e1000_fc_full:
200 advertising |= ADVERTISED_Pause;
201 break;
202 case e1000_fc_rx_pause:
203 advertising |= (ADVERTISED_Pause |
204 ADVERTISED_Asym_Pause);
205 break;
206 case e1000_fc_tx_pause:
207 advertising |= ADVERTISED_Asym_Pause;
208 break;
209 default:
210 advertising &= ~(ADVERTISED_Pause |
211 ADVERTISED_Asym_Pause);
212 }
213 if (status & E1000_STATUS_LU) {
214 if ((status & E1000_STATUS_2P5_SKU) &&
215 !(status & E1000_STATUS_2P5_SKU_OVER)) {
216 speed = SPEED_2500;
217 } else if (status & E1000_STATUS_SPEED_1000) {
218 speed = SPEED_1000;
219 } else if (status & E1000_STATUS_SPEED_100) {
220 speed = SPEED_100;
221 } else {
222 speed = SPEED_10;
223 }
224 if ((status & E1000_STATUS_FD) ||
225 hw->phy.media_type != e1000_media_type_copper)
226 cmd->base.duplex = DUPLEX_FULL;
227 else
228 cmd->base.duplex = DUPLEX_HALF;
229 } else {
230 speed = SPEED_UNKNOWN;
231 cmd->base.duplex = DUPLEX_UNKNOWN;
232 }
233 cmd->base.speed = speed;
234 if ((hw->phy.media_type == e1000_media_type_fiber) ||
235 hw->mac.autoneg)
236 cmd->base.autoneg = AUTONEG_ENABLE;
237 else
238 cmd->base.autoneg = AUTONEG_DISABLE;
239
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */
241 if (hw->phy.media_type == e1000_media_type_copper)
242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
243 ETH_TP_MDI;
244 else
245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
246
247 if (hw->phy.mdix == AUTO_ALL_MODES)
248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
249 else
250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;
251
252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
253 supported);
254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
255 advertising);
256
257 return 0;
258 }
259
igb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)260 static int igb_set_link_ksettings(struct net_device *netdev,
261 const struct ethtool_link_ksettings *cmd)
262 {
263 struct igb_adapter *adapter = netdev_priv(netdev);
264 struct e1000_hw *hw = &adapter->hw;
265 u32 advertising;
266
267 /* When SoL/IDER sessions are active, autoneg/speed/duplex
268 * cannot be changed
269 */
270 if (igb_check_reset_block(hw)) {
271 dev_err(&adapter->pdev->dev,
272 "Cannot change link characteristics when SoL/IDER is active.\n");
273 return -EINVAL;
274 }
275
276 /* MDI setting is only allowed when autoneg enabled because
277 * some hardware doesn't allow MDI setting when speed or
278 * duplex is forced.
279 */
280 if (cmd->base.eth_tp_mdix_ctrl) {
281 if (hw->phy.media_type != e1000_media_type_copper)
282 return -EOPNOTSUPP;
283
284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
285 (cmd->base.autoneg != AUTONEG_ENABLE)) {
286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
287 return -EINVAL;
288 }
289 }
290
291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
292 usleep_range(1000, 2000);
293
294 ethtool_convert_link_mode_to_legacy_u32(&advertising,
295 cmd->link_modes.advertising);
296
297 if (cmd->base.autoneg == AUTONEG_ENABLE) {
298 hw->mac.autoneg = 1;
299 if (hw->phy.media_type == e1000_media_type_fiber) {
300 hw->phy.autoneg_advertised = advertising |
301 ADVERTISED_FIBRE |
302 ADVERTISED_Autoneg;
303 switch (adapter->link_speed) {
304 case SPEED_2500:
305 hw->phy.autoneg_advertised =
306 ADVERTISED_2500baseX_Full;
307 break;
308 case SPEED_1000:
309 hw->phy.autoneg_advertised =
310 ADVERTISED_1000baseT_Full;
311 break;
312 case SPEED_100:
313 hw->phy.autoneg_advertised =
314 ADVERTISED_100baseT_Full;
315 break;
316 default:
317 break;
318 }
319 } else {
320 hw->phy.autoneg_advertised = advertising |
321 ADVERTISED_TP |
322 ADVERTISED_Autoneg;
323 }
324 advertising = hw->phy.autoneg_advertised;
325 if (adapter->fc_autoneg)
326 hw->fc.requested_mode = e1000_fc_default;
327 } else {
328 u32 speed = cmd->base.speed;
329 /* calling this overrides forced MDI setting */
330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {
331 clear_bit(__IGB_RESETTING, &adapter->state);
332 return -EINVAL;
333 }
334 }
335
336 /* MDI-X => 2; MDI => 1; Auto => 3 */
337 if (cmd->base.eth_tp_mdix_ctrl) {
338 /* fix up the value for auto (3 => 0) as zero is mapped
339 * internally to auto
340 */
341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
342 hw->phy.mdix = AUTO_ALL_MODES;
343 else
344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;
345 }
346
347 /* reset the link */
348 if (netif_running(adapter->netdev)) {
349 igb_down(adapter);
350 igb_up(adapter);
351 } else
352 igb_reset(adapter);
353
354 clear_bit(__IGB_RESETTING, &adapter->state);
355 return 0;
356 }
357
igb_get_link(struct net_device * netdev)358 static u32 igb_get_link(struct net_device *netdev)
359 {
360 struct igb_adapter *adapter = netdev_priv(netdev);
361 struct e1000_mac_info *mac = &adapter->hw.mac;
362
363 /* If the link is not reported up to netdev, interrupts are disabled,
364 * and so the physical link state may have changed since we last
365 * looked. Set get_link_status to make sure that the true link
366 * state is interrogated, rather than pulling a cached and possibly
367 * stale link state from the driver.
368 */
369 if (!netif_carrier_ok(netdev))
370 mac->get_link_status = 1;
371
372 return igb_has_link(adapter);
373 }
374
igb_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)375 static void igb_get_pauseparam(struct net_device *netdev,
376 struct ethtool_pauseparam *pause)
377 {
378 struct igb_adapter *adapter = netdev_priv(netdev);
379 struct e1000_hw *hw = &adapter->hw;
380
381 pause->autoneg =
382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
383
384 if (hw->fc.current_mode == e1000_fc_rx_pause)
385 pause->rx_pause = 1;
386 else if (hw->fc.current_mode == e1000_fc_tx_pause)
387 pause->tx_pause = 1;
388 else if (hw->fc.current_mode == e1000_fc_full) {
389 pause->rx_pause = 1;
390 pause->tx_pause = 1;
391 }
392 }
393
igb_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)394 static int igb_set_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *pause)
396 {
397 struct igb_adapter *adapter = netdev_priv(netdev);
398 struct e1000_hw *hw = &adapter->hw;
399 int retval = 0;
400 int i;
401
402 /* 100basefx does not support setting link flow control */
403 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
404 return -EINVAL;
405
406 adapter->fc_autoneg = pause->autoneg;
407
408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
409 usleep_range(1000, 2000);
410
411 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
412 hw->fc.requested_mode = e1000_fc_default;
413 if (netif_running(adapter->netdev)) {
414 igb_down(adapter);
415 igb_up(adapter);
416 } else {
417 igb_reset(adapter);
418 }
419 } else {
420 if (pause->rx_pause && pause->tx_pause)
421 hw->fc.requested_mode = e1000_fc_full;
422 else if (pause->rx_pause && !pause->tx_pause)
423 hw->fc.requested_mode = e1000_fc_rx_pause;
424 else if (!pause->rx_pause && pause->tx_pause)
425 hw->fc.requested_mode = e1000_fc_tx_pause;
426 else if (!pause->rx_pause && !pause->tx_pause)
427 hw->fc.requested_mode = e1000_fc_none;
428
429 hw->fc.current_mode = hw->fc.requested_mode;
430
431 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
432 igb_force_mac_fc(hw) : igb_setup_link(hw));
433
434 /* Make sure SRRCTL considers new fc settings for each ring */
435 for (i = 0; i < adapter->num_rx_queues; i++) {
436 struct igb_ring *ring = adapter->rx_ring[i];
437
438 igb_setup_srrctl(adapter, ring);
439 }
440 }
441
442 clear_bit(__IGB_RESETTING, &adapter->state);
443 return retval;
444 }
445
igb_get_msglevel(struct net_device * netdev)446 static u32 igb_get_msglevel(struct net_device *netdev)
447 {
448 struct igb_adapter *adapter = netdev_priv(netdev);
449 return adapter->msg_enable;
450 }
451
igb_set_msglevel(struct net_device * netdev,u32 data)452 static void igb_set_msglevel(struct net_device *netdev, u32 data)
453 {
454 struct igb_adapter *adapter = netdev_priv(netdev);
455 adapter->msg_enable = data;
456 }
457
igb_get_regs_len(struct net_device * netdev)458 static int igb_get_regs_len(struct net_device *netdev)
459 {
460 #define IGB_REGS_LEN 740
461 return IGB_REGS_LEN * sizeof(u32);
462 }
463
igb_get_regs(struct net_device * netdev,struct ethtool_regs * regs,void * p)464 static void igb_get_regs(struct net_device *netdev,
465 struct ethtool_regs *regs, void *p)
466 {
467 struct igb_adapter *adapter = netdev_priv(netdev);
468 struct e1000_hw *hw = &adapter->hw;
469 u32 *regs_buff = p;
470 u8 i;
471
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
473
474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
475
476 /* General Registers */
477 regs_buff[0] = rd32(E1000_CTRL);
478 regs_buff[1] = rd32(E1000_STATUS);
479 regs_buff[2] = rd32(E1000_CTRL_EXT);
480 regs_buff[3] = rd32(E1000_MDIC);
481 regs_buff[4] = rd32(E1000_SCTL);
482 regs_buff[5] = rd32(E1000_CONNSW);
483 regs_buff[6] = rd32(E1000_VET);
484 regs_buff[7] = rd32(E1000_LEDCTL);
485 regs_buff[8] = rd32(E1000_PBA);
486 regs_buff[9] = rd32(E1000_PBS);
487 regs_buff[10] = rd32(E1000_FRTIMER);
488 regs_buff[11] = rd32(E1000_TCPTIMER);
489
490 /* NVM Register */
491 regs_buff[12] = rd32(E1000_EECD);
492
493 /* Interrupt */
494 /* Reading EICS for EICR because they read the
495 * same but EICS does not clear on read
496 */
497 regs_buff[13] = rd32(E1000_EICS);
498 regs_buff[14] = rd32(E1000_EICS);
499 regs_buff[15] = rd32(E1000_EIMS);
500 regs_buff[16] = rd32(E1000_EIMC);
501 regs_buff[17] = rd32(E1000_EIAC);
502 regs_buff[18] = rd32(E1000_EIAM);
503 /* Reading ICS for ICR because they read the
504 * same but ICS does not clear on read
505 */
506 regs_buff[19] = rd32(E1000_ICS);
507 regs_buff[20] = rd32(E1000_ICS);
508 regs_buff[21] = rd32(E1000_IMS);
509 regs_buff[22] = rd32(E1000_IMC);
510 regs_buff[23] = rd32(E1000_IAC);
511 regs_buff[24] = rd32(E1000_IAM);
512 regs_buff[25] = rd32(E1000_IMIRVP);
513
514 /* Flow Control */
515 regs_buff[26] = rd32(E1000_FCAL);
516 regs_buff[27] = rd32(E1000_FCAH);
517 regs_buff[28] = rd32(E1000_FCTTV);
518 regs_buff[29] = rd32(E1000_FCRTL);
519 regs_buff[30] = rd32(E1000_FCRTH);
520 regs_buff[31] = rd32(E1000_FCRTV);
521
522 /* Receive */
523 regs_buff[32] = rd32(E1000_RCTL);
524 regs_buff[33] = rd32(E1000_RXCSUM);
525 regs_buff[34] = rd32(E1000_RLPML);
526 regs_buff[35] = rd32(E1000_RFCTL);
527 regs_buff[36] = rd32(E1000_MRQC);
528 regs_buff[37] = rd32(E1000_VT_CTL);
529
530 /* Transmit */
531 regs_buff[38] = rd32(E1000_TCTL);
532 regs_buff[39] = rd32(E1000_TCTL_EXT);
533 regs_buff[40] = rd32(E1000_TIPG);
534 regs_buff[41] = rd32(E1000_DTXCTL);
535
536 /* Wake Up */
537 regs_buff[42] = rd32(E1000_WUC);
538 regs_buff[43] = rd32(E1000_WUFC);
539 regs_buff[44] = rd32(E1000_WUS);
540 regs_buff[45] = rd32(E1000_IPAV);
541 regs_buff[46] = rd32(E1000_WUPL);
542
543 /* MAC */
544 regs_buff[47] = rd32(E1000_PCS_CFG0);
545 regs_buff[48] = rd32(E1000_PCS_LCTL);
546 regs_buff[49] = rd32(E1000_PCS_LSTAT);
547 regs_buff[50] = rd32(E1000_PCS_ANADV);
548 regs_buff[51] = rd32(E1000_PCS_LPAB);
549 regs_buff[52] = rd32(E1000_PCS_NPTX);
550 regs_buff[53] = rd32(E1000_PCS_LPABNP);
551
552 /* Statistics */
553 regs_buff[54] = adapter->stats.crcerrs;
554 regs_buff[55] = adapter->stats.algnerrc;
555 regs_buff[56] = adapter->stats.symerrs;
556 regs_buff[57] = adapter->stats.rxerrc;
557 regs_buff[58] = adapter->stats.mpc;
558 regs_buff[59] = adapter->stats.scc;
559 regs_buff[60] = adapter->stats.ecol;
560 regs_buff[61] = adapter->stats.mcc;
561 regs_buff[62] = adapter->stats.latecol;
562 regs_buff[63] = adapter->stats.colc;
563 regs_buff[64] = adapter->stats.dc;
564 regs_buff[65] = adapter->stats.tncrs;
565 regs_buff[66] = adapter->stats.sec;
566 regs_buff[67] = adapter->stats.htdpmc;
567 regs_buff[68] = adapter->stats.rlec;
568 regs_buff[69] = adapter->stats.xonrxc;
569 regs_buff[70] = adapter->stats.xontxc;
570 regs_buff[71] = adapter->stats.xoffrxc;
571 regs_buff[72] = adapter->stats.xofftxc;
572 regs_buff[73] = adapter->stats.fcruc;
573 regs_buff[74] = adapter->stats.prc64;
574 regs_buff[75] = adapter->stats.prc127;
575 regs_buff[76] = adapter->stats.prc255;
576 regs_buff[77] = adapter->stats.prc511;
577 regs_buff[78] = adapter->stats.prc1023;
578 regs_buff[79] = adapter->stats.prc1522;
579 regs_buff[80] = adapter->stats.gprc;
580 regs_buff[81] = adapter->stats.bprc;
581 regs_buff[82] = adapter->stats.mprc;
582 regs_buff[83] = adapter->stats.gptc;
583 regs_buff[84] = adapter->stats.gorc;
584 regs_buff[86] = adapter->stats.gotc;
585 regs_buff[88] = adapter->stats.rnbc;
586 regs_buff[89] = adapter->stats.ruc;
587 regs_buff[90] = adapter->stats.rfc;
588 regs_buff[91] = adapter->stats.roc;
589 regs_buff[92] = adapter->stats.rjc;
590 regs_buff[93] = adapter->stats.mgprc;
591 regs_buff[94] = adapter->stats.mgpdc;
592 regs_buff[95] = adapter->stats.mgptc;
593 regs_buff[96] = adapter->stats.tor;
594 regs_buff[98] = adapter->stats.tot;
595 regs_buff[100] = adapter->stats.tpr;
596 regs_buff[101] = adapter->stats.tpt;
597 regs_buff[102] = adapter->stats.ptc64;
598 regs_buff[103] = adapter->stats.ptc127;
599 regs_buff[104] = adapter->stats.ptc255;
600 regs_buff[105] = adapter->stats.ptc511;
601 regs_buff[106] = adapter->stats.ptc1023;
602 regs_buff[107] = adapter->stats.ptc1522;
603 regs_buff[108] = adapter->stats.mptc;
604 regs_buff[109] = adapter->stats.bptc;
605 regs_buff[110] = adapter->stats.tsctc;
606 regs_buff[111] = adapter->stats.iac;
607 regs_buff[112] = adapter->stats.rpthc;
608 regs_buff[113] = adapter->stats.hgptc;
609 regs_buff[114] = adapter->stats.hgorc;
610 regs_buff[116] = adapter->stats.hgotc;
611 regs_buff[118] = adapter->stats.lenerrs;
612 regs_buff[119] = adapter->stats.scvpc;
613 regs_buff[120] = adapter->stats.hrmpc;
614
615 for (i = 0; i < 4; i++)
616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
617 for (i = 0; i < 4; i++)
618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
619 for (i = 0; i < 4; i++)
620 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
621 for (i = 0; i < 4; i++)
622 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
623 for (i = 0; i < 4; i++)
624 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
625 for (i = 0; i < 4; i++)
626 regs_buff[141 + i] = rd32(E1000_RDH(i));
627 for (i = 0; i < 4; i++)
628 regs_buff[145 + i] = rd32(E1000_RDT(i));
629 for (i = 0; i < 4; i++)
630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
631
632 for (i = 0; i < 10; i++)
633 regs_buff[153 + i] = rd32(E1000_EITR(i));
634 for (i = 0; i < 8; i++)
635 regs_buff[163 + i] = rd32(E1000_IMIR(i));
636 for (i = 0; i < 8; i++)
637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
638 for (i = 0; i < 16; i++)
639 regs_buff[179 + i] = rd32(E1000_RAL(i));
640 for (i = 0; i < 16; i++)
641 regs_buff[195 + i] = rd32(E1000_RAH(i));
642
643 for (i = 0; i < 4; i++)
644 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
645 for (i = 0; i < 4; i++)
646 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
647 for (i = 0; i < 4; i++)
648 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
649 for (i = 0; i < 4; i++)
650 regs_buff[223 + i] = rd32(E1000_TDH(i));
651 for (i = 0; i < 4; i++)
652 regs_buff[227 + i] = rd32(E1000_TDT(i));
653 for (i = 0; i < 4; i++)
654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
655 for (i = 0; i < 4; i++)
656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
657 for (i = 0; i < 4; i++)
658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
659 for (i = 0; i < 4; i++)
660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
661
662 for (i = 0; i < 4; i++)
663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
664 for (i = 0; i < 4; i++)
665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
666 for (i = 0; i < 32; i++)
667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
668 for (i = 0; i < 128; i++)
669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
670 for (i = 0; i < 128; i++)
671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
672 for (i = 0; i < 4; i++)
673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
674
675 regs_buff[547] = rd32(E1000_TDFH);
676 regs_buff[548] = rd32(E1000_TDFT);
677 regs_buff[549] = rd32(E1000_TDFHS);
678 regs_buff[550] = rd32(E1000_TDFPC);
679
680 if (hw->mac.type > e1000_82580) {
681 regs_buff[551] = adapter->stats.o2bgptc;
682 regs_buff[552] = adapter->stats.b2ospc;
683 regs_buff[553] = adapter->stats.o2bspc;
684 regs_buff[554] = adapter->stats.b2ogprc;
685 }
686
687 if (hw->mac.type == e1000_82576) {
688 for (i = 0; i < 12; i++)
689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
690 for (i = 0; i < 4; i++)
691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
692 for (i = 0; i < 12; i++)
693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
694 for (i = 0; i < 12; i++)
695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
700 for (i = 0; i < 12; i++)
701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
702 for (i = 0; i < 12; i++)
703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
704
705 for (i = 0; i < 12; i++)
706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
707 for (i = 0; i < 12; i++)
708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
709 for (i = 0; i < 12; i++)
710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
711 for (i = 0; i < 12; i++)
712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
713 for (i = 0; i < 12; i++)
714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
715 for (i = 0; i < 12; i++)
716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
717 for (i = 0; i < 12; i++)
718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
719 for (i = 0; i < 12; i++)
720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
721 }
722
723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY);
725 }
726
igb_get_eeprom_len(struct net_device * netdev)727 static int igb_get_eeprom_len(struct net_device *netdev)
728 {
729 struct igb_adapter *adapter = netdev_priv(netdev);
730 return adapter->hw.nvm.word_size * 2;
731 }
732
igb_get_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)733 static int igb_get_eeprom(struct net_device *netdev,
734 struct ethtool_eeprom *eeprom, u8 *bytes)
735 {
736 struct igb_adapter *adapter = netdev_priv(netdev);
737 struct e1000_hw *hw = &adapter->hw;
738 u16 *eeprom_buff;
739 int first_word, last_word;
740 int ret_val = 0;
741 u16 i;
742
743 if (eeprom->len == 0)
744 return -EINVAL;
745
746 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
747
748 first_word = eeprom->offset >> 1;
749 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
750
751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16),
752 GFP_KERNEL);
753 if (!eeprom_buff)
754 return -ENOMEM;
755
756 if (hw->nvm.type == e1000_nvm_eeprom_spi)
757 ret_val = hw->nvm.ops.read(hw, first_word,
758 last_word - first_word + 1,
759 eeprom_buff);
760 else {
761 for (i = 0; i < last_word - first_word + 1; i++) {
762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
763 &eeprom_buff[i]);
764 if (ret_val)
765 break;
766 }
767 }
768
769 /* Device's eeprom is always little-endian, word addressable */
770 for (i = 0; i < last_word - first_word + 1; i++)
771 le16_to_cpus(&eeprom_buff[i]);
772
773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
774 eeprom->len);
775 kfree(eeprom_buff);
776
777 return ret_val;
778 }
779
igb_set_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)780 static int igb_set_eeprom(struct net_device *netdev,
781 struct ethtool_eeprom *eeprom, u8 *bytes)
782 {
783 struct igb_adapter *adapter = netdev_priv(netdev);
784 struct e1000_hw *hw = &adapter->hw;
785 u16 *eeprom_buff;
786 void *ptr;
787 int max_len, first_word, last_word, ret_val = 0;
788 u16 i;
789
790 if (eeprom->len == 0)
791 return -EOPNOTSUPP;
792
793 if ((hw->mac.type >= e1000_i210) &&
794 !igb_get_flash_presence_i210(hw)) {
795 return -EOPNOTSUPP;
796 }
797
798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
799 return -EFAULT;
800
801 max_len = hw->nvm.word_size * 2;
802
803 first_word = eeprom->offset >> 1;
804 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
805 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
806 if (!eeprom_buff)
807 return -ENOMEM;
808
809 ptr = (void *)eeprom_buff;
810
811 if (eeprom->offset & 1) {
812 /* need read/modify/write of first changed EEPROM word
813 * only the second byte of the word is being modified
814 */
815 ret_val = hw->nvm.ops.read(hw, first_word, 1,
816 &eeprom_buff[0]);
817 ptr++;
818 }
819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
820 /* need read/modify/write of last changed EEPROM word
821 * only the first byte of the word is being modified
822 */
823 ret_val = hw->nvm.ops.read(hw, last_word, 1,
824 &eeprom_buff[last_word - first_word]);
825 if (ret_val)
826 goto out;
827 }
828
829 /* Device's eeprom is always little-endian, word addressable */
830 for (i = 0; i < last_word - first_word + 1; i++)
831 le16_to_cpus(&eeprom_buff[i]);
832
833 memcpy(ptr, bytes, eeprom->len);
834
835 for (i = 0; i < last_word - first_word + 1; i++)
836 cpu_to_le16s(&eeprom_buff[i]);
837
838 ret_val = hw->nvm.ops.write(hw, first_word,
839 last_word - first_word + 1, eeprom_buff);
840
841 /* Update the checksum if nvm write succeeded */
842 if (ret_val == 0)
843 hw->nvm.ops.update(hw);
844
845 igb_set_fw_version(adapter);
846 out:
847 kfree(eeprom_buff);
848 return ret_val;
849 }
850
igb_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * drvinfo)851 static void igb_get_drvinfo(struct net_device *netdev,
852 struct ethtool_drvinfo *drvinfo)
853 {
854 struct igb_adapter *adapter = netdev_priv(netdev);
855
856 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
857
858 /* EEPROM image version # is reported as firmware version # for
859 * 82575 controllers
860 */
861 strlcpy(drvinfo->fw_version, adapter->fw_version,
862 sizeof(drvinfo->fw_version));
863 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
864 sizeof(drvinfo->bus_info));
865
866 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;
867 }
868
igb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)869 static void igb_get_ringparam(struct net_device *netdev,
870 struct ethtool_ringparam *ring)
871 {
872 struct igb_adapter *adapter = netdev_priv(netdev);
873
874 ring->rx_max_pending = IGB_MAX_RXD;
875 ring->tx_max_pending = IGB_MAX_TXD;
876 ring->rx_pending = adapter->rx_ring_count;
877 ring->tx_pending = adapter->tx_ring_count;
878 }
879
igb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)880 static int igb_set_ringparam(struct net_device *netdev,
881 struct ethtool_ringparam *ring)
882 {
883 struct igb_adapter *adapter = netdev_priv(netdev);
884 struct igb_ring *temp_ring;
885 int i, err = 0;
886 u16 new_rx_count, new_tx_count;
887
888 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
889 return -EINVAL;
890
891 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
892 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
893 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
894
895 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
896 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
897 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
898
899 if ((new_tx_count == adapter->tx_ring_count) &&
900 (new_rx_count == adapter->rx_ring_count)) {
901 /* nothing to do */
902 return 0;
903 }
904
905 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
906 usleep_range(1000, 2000);
907
908 if (!netif_running(adapter->netdev)) {
909 for (i = 0; i < adapter->num_tx_queues; i++)
910 adapter->tx_ring[i]->count = new_tx_count;
911 for (i = 0; i < adapter->num_rx_queues; i++)
912 adapter->rx_ring[i]->count = new_rx_count;
913 adapter->tx_ring_count = new_tx_count;
914 adapter->rx_ring_count = new_rx_count;
915 goto clear_reset;
916 }
917
918 if (adapter->num_tx_queues > adapter->num_rx_queues)
919 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
920 adapter->num_tx_queues));
921 else
922 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
923 adapter->num_rx_queues));
924
925 if (!temp_ring) {
926 err = -ENOMEM;
927 goto clear_reset;
928 }
929
930 igb_down(adapter);
931
932 /* We can't just free everything and then setup again,
933 * because the ISRs in MSI-X mode get passed pointers
934 * to the Tx and Rx ring structs.
935 */
936 if (new_tx_count != adapter->tx_ring_count) {
937 for (i = 0; i < adapter->num_tx_queues; i++) {
938 memcpy(&temp_ring[i], adapter->tx_ring[i],
939 sizeof(struct igb_ring));
940
941 temp_ring[i].count = new_tx_count;
942 err = igb_setup_tx_resources(&temp_ring[i]);
943 if (err) {
944 while (i) {
945 i--;
946 igb_free_tx_resources(&temp_ring[i]);
947 }
948 goto err_setup;
949 }
950 }
951
952 for (i = 0; i < adapter->num_tx_queues; i++) {
953 igb_free_tx_resources(adapter->tx_ring[i]);
954
955 memcpy(adapter->tx_ring[i], &temp_ring[i],
956 sizeof(struct igb_ring));
957 }
958
959 adapter->tx_ring_count = new_tx_count;
960 }
961
962 if (new_rx_count != adapter->rx_ring_count) {
963 for (i = 0; i < adapter->num_rx_queues; i++) {
964 memcpy(&temp_ring[i], adapter->rx_ring[i],
965 sizeof(struct igb_ring));
966
967 temp_ring[i].count = new_rx_count;
968 err = igb_setup_rx_resources(&temp_ring[i]);
969 if (err) {
970 while (i) {
971 i--;
972 igb_free_rx_resources(&temp_ring[i]);
973 }
974 goto err_setup;
975 }
976
977 }
978
979 for (i = 0; i < adapter->num_rx_queues; i++) {
980 igb_free_rx_resources(adapter->rx_ring[i]);
981
982 memcpy(adapter->rx_ring[i], &temp_ring[i],
983 sizeof(struct igb_ring));
984 }
985
986 adapter->rx_ring_count = new_rx_count;
987 }
988 err_setup:
989 igb_up(adapter);
990 vfree(temp_ring);
991 clear_reset:
992 clear_bit(__IGB_RESETTING, &adapter->state);
993 return err;
994 }
995
996 /* ethtool register test data */
997 struct igb_reg_test {
998 u16 reg;
999 u16 reg_offset;
1000 u16 array_len;
1001 u16 test_type;
1002 u32 mask;
1003 u32 write;
1004 };
1005
1006 /* In the hardware, registers are laid out either singly, in arrays
1007 * spaced 0x100 bytes apart, or in contiguous tables. We assume
1008 * most tests take place on arrays or single registers (handled
1009 * as a single-element array) and special-case the tables.
1010 * Table tests are always pattern tests.
1011 *
1012 * We also make provision for some required setup steps by specifying
1013 * registers to be written without any read-back testing.
1014 */
1015
1016 #define PATTERN_TEST 1
1017 #define SET_READ_TEST 2
1018 #define WRITE_NO_TEST 3
1019 #define TABLE32_TEST 4
1020 #define TABLE64_TEST_LO 5
1021 #define TABLE64_TEST_HI 6
1022
1023 /* i210 reg test */
1024 static struct igb_reg_test reg_test_i210[] = {
1025 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1026 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1027 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1028 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1029 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1030 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1031 /* RDH is read-only for i210, only test RDT. */
1032 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1033 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1034 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1035 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1036 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1037 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1038 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1039 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1040 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1041 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1042 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1043 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1044 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1045 0xFFFFFFFF, 0xFFFFFFFF },
1046 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1047 0x900FFFFF, 0xFFFFFFFF },
1048 { E1000_MTA, 0, 128, TABLE32_TEST,
1049 0xFFFFFFFF, 0xFFFFFFFF },
1050 { 0, 0, 0, 0, 0 }
1051 };
1052
1053 /* i350 reg test */
1054 static struct igb_reg_test reg_test_i350[] = {
1055 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1056 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1057 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1058 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1059 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1060 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1061 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1062 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1063 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1064 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1065 /* RDH is read-only for i350, only test RDT. */
1066 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1067 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1069 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1070 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1071 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1072 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1073 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1074 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1075 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1076 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1077 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1078 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1079 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1080 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1081 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1082 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1083 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1084 0xFFFFFFFF, 0xFFFFFFFF },
1085 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1086 0xC3FFFFFF, 0xFFFFFFFF },
1087 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1088 0xFFFFFFFF, 0xFFFFFFFF },
1089 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1090 0xC3FFFFFF, 0xFFFFFFFF },
1091 { E1000_MTA, 0, 128, TABLE32_TEST,
1092 0xFFFFFFFF, 0xFFFFFFFF },
1093 { 0, 0, 0, 0 }
1094 };
1095
1096 /* 82580 reg test */
1097 static struct igb_reg_test reg_test_82580[] = {
1098 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1099 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1100 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1101 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1102 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1103 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1104 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1105 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1106 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1107 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1108 /* RDH is read-only for 82580, only test RDT. */
1109 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1110 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1111 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1112 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1113 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1114 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1115 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1117 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1118 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1119 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1120 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1121 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1122 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1123 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1124 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1125 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1126 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1127 0xFFFFFFFF, 0xFFFFFFFF },
1128 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1129 0x83FFFFFF, 0xFFFFFFFF },
1130 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1131 0xFFFFFFFF, 0xFFFFFFFF },
1132 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1133 0x83FFFFFF, 0xFFFFFFFF },
1134 { E1000_MTA, 0, 128, TABLE32_TEST,
1135 0xFFFFFFFF, 0xFFFFFFFF },
1136 { 0, 0, 0, 0 }
1137 };
1138
1139 /* 82576 reg test */
1140 static struct igb_reg_test reg_test_82576[] = {
1141 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1142 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1143 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1144 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1145 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1146 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1147 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1148 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1149 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1150 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1151 /* Enable all RX queues before testing. */
1152 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1153 E1000_RXDCTL_QUEUE_ENABLE },
1154 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1155 E1000_RXDCTL_QUEUE_ENABLE },
1156 /* RDH is read-only for 82576, only test RDT. */
1157 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1158 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1159 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1160 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1161 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1162 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1163 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1164 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1165 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1166 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1167 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1168 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1169 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1170 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1171 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1172 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1173 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1174 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1175 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1176 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1177 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1178 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { 0, 0, 0, 0 }
1180 };
1181
1182 /* 82575 register test */
1183 static struct igb_reg_test reg_test_82575[] = {
1184 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1185 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1186 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1187 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1189 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1191 /* Enable all four RX queues before testing. */
1192 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1193 E1000_RXDCTL_QUEUE_ENABLE },
1194 /* RDH is read-only for 82575, only test RDT. */
1195 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1196 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1197 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1198 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1199 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1200 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1201 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1202 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1203 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1204 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1205 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1206 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1207 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1208 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1209 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1210 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1211 { 0, 0, 0, 0 }
1212 };
1213
reg_pattern_test(struct igb_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1214 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1215 int reg, u32 mask, u32 write)
1216 {
1217 struct e1000_hw *hw = &adapter->hw;
1218 u32 pat, val;
1219 static const u32 _test[] = {
1220 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1221 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1222 wr32(reg, (_test[pat] & write));
1223 val = rd32(reg) & mask;
1224 if (val != (_test[pat] & write & mask)) {
1225 dev_err(&adapter->pdev->dev,
1226 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1227 reg, val, (_test[pat] & write & mask));
1228 *data = reg;
1229 return true;
1230 }
1231 }
1232
1233 return false;
1234 }
1235
reg_set_and_check(struct igb_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1236 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1237 int reg, u32 mask, u32 write)
1238 {
1239 struct e1000_hw *hw = &adapter->hw;
1240 u32 val;
1241
1242 wr32(reg, write & mask);
1243 val = rd32(reg);
1244 if ((write & mask) != (val & mask)) {
1245 dev_err(&adapter->pdev->dev,
1246 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1247 reg, (val & mask), (write & mask));
1248 *data = reg;
1249 return true;
1250 }
1251
1252 return false;
1253 }
1254
1255 #define REG_PATTERN_TEST(reg, mask, write) \
1256 do { \
1257 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1258 return 1; \
1259 } while (0)
1260
1261 #define REG_SET_AND_CHECK(reg, mask, write) \
1262 do { \
1263 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1264 return 1; \
1265 } while (0)
1266
igb_reg_test(struct igb_adapter * adapter,u64 * data)1267 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1268 {
1269 struct e1000_hw *hw = &adapter->hw;
1270 struct igb_reg_test *test;
1271 u32 value, before, after;
1272 u32 i, toggle;
1273
1274 switch (adapter->hw.mac.type) {
1275 case e1000_i350:
1276 case e1000_i354:
1277 test = reg_test_i350;
1278 toggle = 0x7FEFF3FF;
1279 break;
1280 case e1000_i210:
1281 case e1000_i211:
1282 test = reg_test_i210;
1283 toggle = 0x7FEFF3FF;
1284 break;
1285 case e1000_82580:
1286 test = reg_test_82580;
1287 toggle = 0x7FEFF3FF;
1288 break;
1289 case e1000_82576:
1290 test = reg_test_82576;
1291 toggle = 0x7FFFF3FF;
1292 break;
1293 default:
1294 test = reg_test_82575;
1295 toggle = 0x7FFFF3FF;
1296 break;
1297 }
1298
1299 /* Because the status register is such a special case,
1300 * we handle it separately from the rest of the register
1301 * tests. Some bits are read-only, some toggle, and some
1302 * are writable on newer MACs.
1303 */
1304 before = rd32(E1000_STATUS);
1305 value = (rd32(E1000_STATUS) & toggle);
1306 wr32(E1000_STATUS, toggle);
1307 after = rd32(E1000_STATUS) & toggle;
1308 if (value != after) {
1309 dev_err(&adapter->pdev->dev,
1310 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1311 after, value);
1312 *data = 1;
1313 return 1;
1314 }
1315 /* restore previous status */
1316 wr32(E1000_STATUS, before);
1317
1318 /* Perform the remainder of the register test, looping through
1319 * the test table until we either fail or reach the null entry.
1320 */
1321 while (test->reg) {
1322 for (i = 0; i < test->array_len; i++) {
1323 switch (test->test_type) {
1324 case PATTERN_TEST:
1325 REG_PATTERN_TEST(test->reg +
1326 (i * test->reg_offset),
1327 test->mask,
1328 test->write);
1329 break;
1330 case SET_READ_TEST:
1331 REG_SET_AND_CHECK(test->reg +
1332 (i * test->reg_offset),
1333 test->mask,
1334 test->write);
1335 break;
1336 case WRITE_NO_TEST:
1337 writel(test->write,
1338 (adapter->hw.hw_addr + test->reg)
1339 + (i * test->reg_offset));
1340 break;
1341 case TABLE32_TEST:
1342 REG_PATTERN_TEST(test->reg + (i * 4),
1343 test->mask,
1344 test->write);
1345 break;
1346 case TABLE64_TEST_LO:
1347 REG_PATTERN_TEST(test->reg + (i * 8),
1348 test->mask,
1349 test->write);
1350 break;
1351 case TABLE64_TEST_HI:
1352 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1353 test->mask,
1354 test->write);
1355 break;
1356 }
1357 }
1358 test++;
1359 }
1360
1361 *data = 0;
1362 return 0;
1363 }
1364
igb_eeprom_test(struct igb_adapter * adapter,u64 * data)1365 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1366 {
1367 struct e1000_hw *hw = &adapter->hw;
1368
1369 *data = 0;
1370
1371 /* Validate eeprom on all parts but flashless */
1372 switch (hw->mac.type) {
1373 case e1000_i210:
1374 case e1000_i211:
1375 if (igb_get_flash_presence_i210(hw)) {
1376 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1377 *data = 2;
1378 }
1379 break;
1380 default:
1381 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1382 *data = 2;
1383 break;
1384 }
1385
1386 return *data;
1387 }
1388
igb_test_intr(int irq,void * data)1389 static irqreturn_t igb_test_intr(int irq, void *data)
1390 {
1391 struct igb_adapter *adapter = (struct igb_adapter *) data;
1392 struct e1000_hw *hw = &adapter->hw;
1393
1394 adapter->test_icr |= rd32(E1000_ICR);
1395
1396 return IRQ_HANDLED;
1397 }
1398
igb_intr_test(struct igb_adapter * adapter,u64 * data)1399 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1400 {
1401 struct e1000_hw *hw = &adapter->hw;
1402 struct net_device *netdev = adapter->netdev;
1403 u32 mask, ics_mask, i = 0, shared_int = true;
1404 u32 irq = adapter->pdev->irq;
1405
1406 *data = 0;
1407
1408 /* Hook up test interrupt handler just for this test */
1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1410 if (request_irq(adapter->msix_entries[0].vector,
1411 igb_test_intr, 0, netdev->name, adapter)) {
1412 *data = 1;
1413 return -1;
1414 }
1415 wr32(E1000_IVAR_MISC, E1000_IVAR_VALID << 8);
1416 wr32(E1000_EIMS, BIT(0));
1417 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1418 shared_int = false;
1419 if (request_irq(irq,
1420 igb_test_intr, 0, netdev->name, adapter)) {
1421 *data = 1;
1422 return -1;
1423 }
1424 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1425 netdev->name, adapter)) {
1426 shared_int = false;
1427 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1428 netdev->name, adapter)) {
1429 *data = 1;
1430 return -1;
1431 }
1432 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1433 (shared_int ? "shared" : "unshared"));
1434
1435 /* Disable all the interrupts */
1436 wr32(E1000_IMC, ~0);
1437 wrfl();
1438 usleep_range(10000, 11000);
1439
1440 /* Define all writable bits for ICS */
1441 switch (hw->mac.type) {
1442 case e1000_82575:
1443 ics_mask = 0x37F47EDD;
1444 break;
1445 case e1000_82576:
1446 ics_mask = 0x77D4FBFD;
1447 break;
1448 case e1000_82580:
1449 ics_mask = 0x77DCFED5;
1450 break;
1451 case e1000_i350:
1452 case e1000_i354:
1453 case e1000_i210:
1454 case e1000_i211:
1455 ics_mask = 0x77DCFED5;
1456 break;
1457 default:
1458 ics_mask = 0x7FFFFFFF;
1459 break;
1460 }
1461
1462 /* Test each interrupt */
1463 for (; i < 31; i++) {
1464 /* Interrupt to test */
1465 mask = BIT(i);
1466
1467 if (!(mask & ics_mask))
1468 continue;
1469
1470 if (!shared_int) {
1471 /* Disable the interrupt to be reported in
1472 * the cause register and then force the same
1473 * interrupt and see if one gets posted. If
1474 * an interrupt was posted to the bus, the
1475 * test failed.
1476 */
1477 adapter->test_icr = 0;
1478
1479 /* Flush any pending interrupts */
1480 wr32(E1000_ICR, ~0);
1481
1482 wr32(E1000_IMC, mask);
1483 wr32(E1000_ICS, mask);
1484 wrfl();
1485 usleep_range(10000, 11000);
1486
1487 if (adapter->test_icr & mask) {
1488 *data = 3;
1489 break;
1490 }
1491 }
1492
1493 /* Enable the interrupt to be reported in
1494 * the cause register and then force the same
1495 * interrupt and see if one gets posted. If
1496 * an interrupt was not posted to the bus, the
1497 * test failed.
1498 */
1499 adapter->test_icr = 0;
1500
1501 /* Flush any pending interrupts */
1502 wr32(E1000_ICR, ~0);
1503
1504 wr32(E1000_IMS, mask);
1505 wr32(E1000_ICS, mask);
1506 wrfl();
1507 usleep_range(10000, 11000);
1508
1509 if (!(adapter->test_icr & mask)) {
1510 *data = 4;
1511 break;
1512 }
1513
1514 if (!shared_int) {
1515 /* Disable the other interrupts to be reported in
1516 * the cause register and then force the other
1517 * interrupts and see if any get posted. If
1518 * an interrupt was posted to the bus, the
1519 * test failed.
1520 */
1521 adapter->test_icr = 0;
1522
1523 /* Flush any pending interrupts */
1524 wr32(E1000_ICR, ~0);
1525
1526 wr32(E1000_IMC, ~mask);
1527 wr32(E1000_ICS, ~mask);
1528 wrfl();
1529 usleep_range(10000, 11000);
1530
1531 if (adapter->test_icr & mask) {
1532 *data = 5;
1533 break;
1534 }
1535 }
1536 }
1537
1538 /* Disable all the interrupts */
1539 wr32(E1000_IMC, ~0);
1540 wrfl();
1541 usleep_range(10000, 11000);
1542
1543 /* Unhook test interrupt handler */
1544 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1545 free_irq(adapter->msix_entries[0].vector, adapter);
1546 else
1547 free_irq(irq, adapter);
1548
1549 return *data;
1550 }
1551
igb_free_desc_rings(struct igb_adapter * adapter)1552 static void igb_free_desc_rings(struct igb_adapter *adapter)
1553 {
1554 igb_free_tx_resources(&adapter->test_tx_ring);
1555 igb_free_rx_resources(&adapter->test_rx_ring);
1556 }
1557
igb_setup_desc_rings(struct igb_adapter * adapter)1558 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1559 {
1560 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1561 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1562 struct e1000_hw *hw = &adapter->hw;
1563 int ret_val;
1564
1565 /* Setup Tx descriptor ring and Tx buffers */
1566 tx_ring->count = IGB_DEFAULT_TXD;
1567 tx_ring->dev = &adapter->pdev->dev;
1568 tx_ring->netdev = adapter->netdev;
1569 tx_ring->reg_idx = adapter->vfs_allocated_count;
1570
1571 if (igb_setup_tx_resources(tx_ring)) {
1572 ret_val = 1;
1573 goto err_nomem;
1574 }
1575
1576 igb_setup_tctl(adapter);
1577 igb_configure_tx_ring(adapter, tx_ring);
1578
1579 /* Setup Rx descriptor ring and Rx buffers */
1580 rx_ring->count = IGB_DEFAULT_RXD;
1581 rx_ring->dev = &adapter->pdev->dev;
1582 rx_ring->netdev = adapter->netdev;
1583 rx_ring->reg_idx = adapter->vfs_allocated_count;
1584
1585 if (igb_setup_rx_resources(rx_ring)) {
1586 ret_val = 3;
1587 goto err_nomem;
1588 }
1589
1590 /* set the default queue to queue 0 of PF */
1591 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1592
1593 /* enable receive ring */
1594 igb_setup_rctl(adapter);
1595 igb_configure_rx_ring(adapter, rx_ring);
1596
1597 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1598
1599 return 0;
1600
1601 err_nomem:
1602 igb_free_desc_rings(adapter);
1603 return ret_val;
1604 }
1605
igb_phy_disable_receiver(struct igb_adapter * adapter)1606 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1607 {
1608 struct e1000_hw *hw = &adapter->hw;
1609
1610 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1611 igb_write_phy_reg(hw, 29, 0x001F);
1612 igb_write_phy_reg(hw, 30, 0x8FFC);
1613 igb_write_phy_reg(hw, 29, 0x001A);
1614 igb_write_phy_reg(hw, 30, 0x8FF0);
1615 }
1616
igb_integrated_phy_loopback(struct igb_adapter * adapter)1617 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1618 {
1619 struct e1000_hw *hw = &adapter->hw;
1620 u32 ctrl_reg = 0;
1621
1622 hw->mac.autoneg = false;
1623
1624 if (hw->phy.type == e1000_phy_m88) {
1625 if (hw->phy.id != I210_I_PHY_ID) {
1626 /* Auto-MDI/MDIX Off */
1627 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1628 /* reset to update Auto-MDI/MDIX */
1629 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1630 /* autoneg off */
1631 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1632 } else {
1633 /* force 1000, set loopback */
1634 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1635 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1636 }
1637 } else if (hw->phy.type == e1000_phy_82580) {
1638 /* enable MII loopback */
1639 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1640 }
1641
1642 /* add small delay to avoid loopback test failure */
1643 msleep(50);
1644
1645 /* force 1000, set loopback */
1646 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1647
1648 /* Now set up the MAC to the same speed/duplex as the PHY. */
1649 ctrl_reg = rd32(E1000_CTRL);
1650 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1651 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1652 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1653 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1654 E1000_CTRL_FD | /* Force Duplex to FULL */
1655 E1000_CTRL_SLU); /* Set link up enable bit */
1656
1657 if (hw->phy.type == e1000_phy_m88)
1658 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1659
1660 wr32(E1000_CTRL, ctrl_reg);
1661
1662 /* Disable the receiver on the PHY so when a cable is plugged in, the
1663 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1664 */
1665 if (hw->phy.type == e1000_phy_m88)
1666 igb_phy_disable_receiver(adapter);
1667
1668 msleep(500);
1669 return 0;
1670 }
1671
igb_set_phy_loopback(struct igb_adapter * adapter)1672 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1673 {
1674 return igb_integrated_phy_loopback(adapter);
1675 }
1676
igb_setup_loopback_test(struct igb_adapter * adapter)1677 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1678 {
1679 struct e1000_hw *hw = &adapter->hw;
1680 u32 reg;
1681
1682 reg = rd32(E1000_CTRL_EXT);
1683
1684 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1685 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1686 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1687 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1688 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1689 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1690 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1691 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1692 /* Enable DH89xxCC MPHY for near end loopback */
1693 reg = rd32(E1000_MPHY_ADDR_CTL);
1694 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1695 E1000_MPHY_PCS_CLK_REG_OFFSET;
1696 wr32(E1000_MPHY_ADDR_CTL, reg);
1697
1698 reg = rd32(E1000_MPHY_DATA);
1699 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1700 wr32(E1000_MPHY_DATA, reg);
1701 }
1702
1703 reg = rd32(E1000_RCTL);
1704 reg |= E1000_RCTL_LBM_TCVR;
1705 wr32(E1000_RCTL, reg);
1706
1707 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1708
1709 reg = rd32(E1000_CTRL);
1710 reg &= ~(E1000_CTRL_RFCE |
1711 E1000_CTRL_TFCE |
1712 E1000_CTRL_LRST);
1713 reg |= E1000_CTRL_SLU |
1714 E1000_CTRL_FD;
1715 wr32(E1000_CTRL, reg);
1716
1717 /* Unset switch control to serdes energy detect */
1718 reg = rd32(E1000_CONNSW);
1719 reg &= ~E1000_CONNSW_ENRGSRC;
1720 wr32(E1000_CONNSW, reg);
1721
1722 /* Unset sigdetect for SERDES loopback on
1723 * 82580 and newer devices.
1724 */
1725 if (hw->mac.type >= e1000_82580) {
1726 reg = rd32(E1000_PCS_CFG0);
1727 reg |= E1000_PCS_CFG_IGN_SD;
1728 wr32(E1000_PCS_CFG0, reg);
1729 }
1730
1731 /* Set PCS register for forced speed */
1732 reg = rd32(E1000_PCS_LCTL);
1733 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1734 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1735 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1736 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1737 E1000_PCS_LCTL_FSD | /* Force Speed */
1738 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1739 wr32(E1000_PCS_LCTL, reg);
1740
1741 return 0;
1742 }
1743
1744 return igb_set_phy_loopback(adapter);
1745 }
1746
igb_loopback_cleanup(struct igb_adapter * adapter)1747 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1748 {
1749 struct e1000_hw *hw = &adapter->hw;
1750 u32 rctl;
1751 u16 phy_reg;
1752
1753 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1754 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1755 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1756 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1757 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1758 u32 reg;
1759
1760 /* Disable near end loopback on DH89xxCC */
1761 reg = rd32(E1000_MPHY_ADDR_CTL);
1762 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1763 E1000_MPHY_PCS_CLK_REG_OFFSET;
1764 wr32(E1000_MPHY_ADDR_CTL, reg);
1765
1766 reg = rd32(E1000_MPHY_DATA);
1767 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1768 wr32(E1000_MPHY_DATA, reg);
1769 }
1770
1771 rctl = rd32(E1000_RCTL);
1772 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1773 wr32(E1000_RCTL, rctl);
1774
1775 hw->mac.autoneg = true;
1776 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1777 if (phy_reg & MII_CR_LOOPBACK) {
1778 phy_reg &= ~MII_CR_LOOPBACK;
1779 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1780 igb_phy_sw_reset(hw);
1781 }
1782 }
1783
igb_create_lbtest_frame(struct sk_buff * skb,unsigned int frame_size)1784 static void igb_create_lbtest_frame(struct sk_buff *skb,
1785 unsigned int frame_size)
1786 {
1787 memset(skb->data, 0xFF, frame_size);
1788 frame_size /= 2;
1789 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1790 skb->data[frame_size + 10] = 0xBE;
1791 skb->data[frame_size + 12] = 0xAF;
1792 }
1793
igb_check_lbtest_frame(struct igb_rx_buffer * rx_buffer,unsigned int frame_size)1794 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1795 unsigned int frame_size)
1796 {
1797 unsigned char *data;
1798 bool match = true;
1799
1800 frame_size >>= 1;
1801
1802 data = kmap(rx_buffer->page);
1803
1804 if (data[3] != 0xFF ||
1805 data[frame_size + 10] != 0xBE ||
1806 data[frame_size + 12] != 0xAF)
1807 match = false;
1808
1809 kunmap(rx_buffer->page);
1810
1811 return match;
1812 }
1813
igb_clean_test_rings(struct igb_ring * rx_ring,struct igb_ring * tx_ring,unsigned int size)1814 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1815 struct igb_ring *tx_ring,
1816 unsigned int size)
1817 {
1818 union e1000_adv_rx_desc *rx_desc;
1819 struct igb_rx_buffer *rx_buffer_info;
1820 struct igb_tx_buffer *tx_buffer_info;
1821 u16 rx_ntc, tx_ntc, count = 0;
1822
1823 /* initialize next to clean and descriptor values */
1824 rx_ntc = rx_ring->next_to_clean;
1825 tx_ntc = tx_ring->next_to_clean;
1826 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1827
1828 while (rx_desc->wb.upper.length) {
1829 /* check Rx buffer */
1830 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1831
1832 /* sync Rx buffer for CPU read */
1833 dma_sync_single_for_cpu(rx_ring->dev,
1834 rx_buffer_info->dma,
1835 size,
1836 DMA_FROM_DEVICE);
1837
1838 /* verify contents of skb */
1839 if (igb_check_lbtest_frame(rx_buffer_info, size))
1840 count++;
1841
1842 /* sync Rx buffer for device write */
1843 dma_sync_single_for_device(rx_ring->dev,
1844 rx_buffer_info->dma,
1845 size,
1846 DMA_FROM_DEVICE);
1847
1848 /* unmap buffer on Tx side */
1849 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1850
1851 /* Free all the Tx ring sk_buffs */
1852 dev_kfree_skb_any(tx_buffer_info->skb);
1853
1854 /* unmap skb header data */
1855 dma_unmap_single(tx_ring->dev,
1856 dma_unmap_addr(tx_buffer_info, dma),
1857 dma_unmap_len(tx_buffer_info, len),
1858 DMA_TO_DEVICE);
1859 dma_unmap_len_set(tx_buffer_info, len, 0);
1860
1861 /* increment Rx/Tx next to clean counters */
1862 rx_ntc++;
1863 if (rx_ntc == rx_ring->count)
1864 rx_ntc = 0;
1865 tx_ntc++;
1866 if (tx_ntc == tx_ring->count)
1867 tx_ntc = 0;
1868
1869 /* fetch next descriptor */
1870 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1871 }
1872
1873 netdev_tx_reset_queue(txring_txq(tx_ring));
1874
1875 /* re-map buffers to ring, store next to clean values */
1876 igb_alloc_rx_buffers(rx_ring, count);
1877 rx_ring->next_to_clean = rx_ntc;
1878 tx_ring->next_to_clean = tx_ntc;
1879
1880 return count;
1881 }
1882
igb_run_loopback_test(struct igb_adapter * adapter)1883 static int igb_run_loopback_test(struct igb_adapter *adapter)
1884 {
1885 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1886 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1887 u16 i, j, lc, good_cnt;
1888 int ret_val = 0;
1889 unsigned int size = IGB_RX_HDR_LEN;
1890 netdev_tx_t tx_ret_val;
1891 struct sk_buff *skb;
1892
1893 /* allocate test skb */
1894 skb = alloc_skb(size, GFP_KERNEL);
1895 if (!skb)
1896 return 11;
1897
1898 /* place data into test skb */
1899 igb_create_lbtest_frame(skb, size);
1900 skb_put(skb, size);
1901
1902 /* Calculate the loop count based on the largest descriptor ring
1903 * The idea is to wrap the largest ring a number of times using 64
1904 * send/receive pairs during each loop
1905 */
1906
1907 if (rx_ring->count <= tx_ring->count)
1908 lc = ((tx_ring->count / 64) * 2) + 1;
1909 else
1910 lc = ((rx_ring->count / 64) * 2) + 1;
1911
1912 for (j = 0; j <= lc; j++) { /* loop count loop */
1913 /* reset count of good packets */
1914 good_cnt = 0;
1915
1916 /* place 64 packets on the transmit queue*/
1917 for (i = 0; i < 64; i++) {
1918 skb_get(skb);
1919 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1920 if (tx_ret_val == NETDEV_TX_OK)
1921 good_cnt++;
1922 }
1923
1924 if (good_cnt != 64) {
1925 ret_val = 12;
1926 break;
1927 }
1928
1929 /* allow 200 milliseconds for packets to go from Tx to Rx */
1930 msleep(200);
1931
1932 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1933 if (good_cnt != 64) {
1934 ret_val = 13;
1935 break;
1936 }
1937 } /* end loop count loop */
1938
1939 /* free the original skb */
1940 kfree_skb(skb);
1941
1942 return ret_val;
1943 }
1944
igb_loopback_test(struct igb_adapter * adapter,u64 * data)1945 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1946 {
1947 /* PHY loopback cannot be performed if SoL/IDER
1948 * sessions are active
1949 */
1950 if (igb_check_reset_block(&adapter->hw)) {
1951 dev_err(&adapter->pdev->dev,
1952 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1953 *data = 0;
1954 goto out;
1955 }
1956
1957 if (adapter->hw.mac.type == e1000_i354) {
1958 dev_info(&adapter->pdev->dev,
1959 "Loopback test not supported on i354.\n");
1960 *data = 0;
1961 goto out;
1962 }
1963 *data = igb_setup_desc_rings(adapter);
1964 if (*data)
1965 goto out;
1966 *data = igb_setup_loopback_test(adapter);
1967 if (*data)
1968 goto err_loopback;
1969 *data = igb_run_loopback_test(adapter);
1970 igb_loopback_cleanup(adapter);
1971
1972 err_loopback:
1973 igb_free_desc_rings(adapter);
1974 out:
1975 return *data;
1976 }
1977
igb_link_test(struct igb_adapter * adapter,u64 * data)1978 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1979 {
1980 struct e1000_hw *hw = &adapter->hw;
1981 *data = 0;
1982 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1983 int i = 0;
1984
1985 hw->mac.serdes_has_link = false;
1986
1987 /* On some blade server designs, link establishment
1988 * could take as long as 2-3 minutes
1989 */
1990 do {
1991 hw->mac.ops.check_for_link(&adapter->hw);
1992 if (hw->mac.serdes_has_link)
1993 return *data;
1994 msleep(20);
1995 } while (i++ < 3750);
1996
1997 *data = 1;
1998 } else {
1999 hw->mac.ops.check_for_link(&adapter->hw);
2000 if (hw->mac.autoneg)
2001 msleep(5000);
2002
2003 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
2004 *data = 1;
2005 }
2006 return *data;
2007 }
2008
igb_diag_test(struct net_device * netdev,struct ethtool_test * eth_test,u64 * data)2009 static void igb_diag_test(struct net_device *netdev,
2010 struct ethtool_test *eth_test, u64 *data)
2011 {
2012 struct igb_adapter *adapter = netdev_priv(netdev);
2013 u16 autoneg_advertised;
2014 u8 forced_speed_duplex, autoneg;
2015 bool if_running = netif_running(netdev);
2016
2017 set_bit(__IGB_TESTING, &adapter->state);
2018
2019 /* can't do offline tests on media switching devices */
2020 if (adapter->hw.dev_spec._82575.mas_capable)
2021 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
2022 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2023 /* Offline tests */
2024
2025 /* save speed, duplex, autoneg settings */
2026 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2027 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2028 autoneg = adapter->hw.mac.autoneg;
2029
2030 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2031
2032 /* power up link for link test */
2033 igb_power_up_link(adapter);
2034
2035 /* Link test performed before hardware reset so autoneg doesn't
2036 * interfere with test result
2037 */
2038 if (igb_link_test(adapter, &data[TEST_LINK]))
2039 eth_test->flags |= ETH_TEST_FL_FAILED;
2040
2041 if (if_running)
2042 /* indicate we're in test mode */
2043 igb_close(netdev);
2044 else
2045 igb_reset(adapter);
2046
2047 if (igb_reg_test(adapter, &data[TEST_REG]))
2048 eth_test->flags |= ETH_TEST_FL_FAILED;
2049
2050 igb_reset(adapter);
2051 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
2052 eth_test->flags |= ETH_TEST_FL_FAILED;
2053
2054 igb_reset(adapter);
2055 if (igb_intr_test(adapter, &data[TEST_IRQ]))
2056 eth_test->flags |= ETH_TEST_FL_FAILED;
2057
2058 igb_reset(adapter);
2059 /* power up link for loopback test */
2060 igb_power_up_link(adapter);
2061 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
2062 eth_test->flags |= ETH_TEST_FL_FAILED;
2063
2064 /* restore speed, duplex, autoneg settings */
2065 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2066 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2067 adapter->hw.mac.autoneg = autoneg;
2068
2069 /* force this routine to wait until autoneg complete/timeout */
2070 adapter->hw.phy.autoneg_wait_to_complete = true;
2071 igb_reset(adapter);
2072 adapter->hw.phy.autoneg_wait_to_complete = false;
2073
2074 clear_bit(__IGB_TESTING, &adapter->state);
2075 if (if_running)
2076 igb_open(netdev);
2077 } else {
2078 dev_info(&adapter->pdev->dev, "online testing starting\n");
2079
2080 /* PHY is powered down when interface is down */
2081 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
2082 eth_test->flags |= ETH_TEST_FL_FAILED;
2083 else
2084 data[TEST_LINK] = 0;
2085
2086 /* Online tests aren't run; pass by default */
2087 data[TEST_REG] = 0;
2088 data[TEST_EEP] = 0;
2089 data[TEST_IRQ] = 0;
2090 data[TEST_LOOP] = 0;
2091
2092 clear_bit(__IGB_TESTING, &adapter->state);
2093 }
2094 msleep_interruptible(4 * 1000);
2095 }
2096
igb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2097 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2098 {
2099 struct igb_adapter *adapter = netdev_priv(netdev);
2100
2101 wol->wolopts = 0;
2102
2103 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2104 return;
2105
2106 wol->supported = WAKE_UCAST | WAKE_MCAST |
2107 WAKE_BCAST | WAKE_MAGIC |
2108 WAKE_PHY;
2109
2110 /* apply any specific unsupported masks here */
2111 switch (adapter->hw.device_id) {
2112 default:
2113 break;
2114 }
2115
2116 if (adapter->wol & E1000_WUFC_EX)
2117 wol->wolopts |= WAKE_UCAST;
2118 if (adapter->wol & E1000_WUFC_MC)
2119 wol->wolopts |= WAKE_MCAST;
2120 if (adapter->wol & E1000_WUFC_BC)
2121 wol->wolopts |= WAKE_BCAST;
2122 if (adapter->wol & E1000_WUFC_MAG)
2123 wol->wolopts |= WAKE_MAGIC;
2124 if (adapter->wol & E1000_WUFC_LNKC)
2125 wol->wolopts |= WAKE_PHY;
2126 }
2127
igb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2128 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2129 {
2130 struct igb_adapter *adapter = netdev_priv(netdev);
2131
2132 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER))
2133 return -EOPNOTSUPP;
2134
2135 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2136 return wol->wolopts ? -EOPNOTSUPP : 0;
2137
2138 /* these settings will always override what we currently have */
2139 adapter->wol = 0;
2140
2141 if (wol->wolopts & WAKE_UCAST)
2142 adapter->wol |= E1000_WUFC_EX;
2143 if (wol->wolopts & WAKE_MCAST)
2144 adapter->wol |= E1000_WUFC_MC;
2145 if (wol->wolopts & WAKE_BCAST)
2146 adapter->wol |= E1000_WUFC_BC;
2147 if (wol->wolopts & WAKE_MAGIC)
2148 adapter->wol |= E1000_WUFC_MAG;
2149 if (wol->wolopts & WAKE_PHY)
2150 adapter->wol |= E1000_WUFC_LNKC;
2151 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2152
2153 return 0;
2154 }
2155
2156 /* bit defines for adapter->led_status */
2157 #define IGB_LED_ON 0
2158
igb_set_phys_id(struct net_device * netdev,enum ethtool_phys_id_state state)2159 static int igb_set_phys_id(struct net_device *netdev,
2160 enum ethtool_phys_id_state state)
2161 {
2162 struct igb_adapter *adapter = netdev_priv(netdev);
2163 struct e1000_hw *hw = &adapter->hw;
2164
2165 switch (state) {
2166 case ETHTOOL_ID_ACTIVE:
2167 igb_blink_led(hw);
2168 return 2;
2169 case ETHTOOL_ID_ON:
2170 igb_blink_led(hw);
2171 break;
2172 case ETHTOOL_ID_OFF:
2173 igb_led_off(hw);
2174 break;
2175 case ETHTOOL_ID_INACTIVE:
2176 igb_led_off(hw);
2177 clear_bit(IGB_LED_ON, &adapter->led_status);
2178 igb_cleanup_led(hw);
2179 break;
2180 }
2181
2182 return 0;
2183 }
2184
igb_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)2185 static int igb_set_coalesce(struct net_device *netdev,
2186 struct ethtool_coalesce *ec,
2187 struct kernel_ethtool_coalesce *kernel_coal,
2188 struct netlink_ext_ack *extack)
2189 {
2190 struct igb_adapter *adapter = netdev_priv(netdev);
2191 int i;
2192
2193 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2194 ((ec->rx_coalesce_usecs > 3) &&
2195 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2196 (ec->rx_coalesce_usecs == 2))
2197 return -EINVAL;
2198
2199 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2200 ((ec->tx_coalesce_usecs > 3) &&
2201 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2202 (ec->tx_coalesce_usecs == 2))
2203 return -EINVAL;
2204
2205 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2206 return -EINVAL;
2207
2208 /* If ITR is disabled, disable DMAC */
2209 if (ec->rx_coalesce_usecs == 0) {
2210 if (adapter->flags & IGB_FLAG_DMAC)
2211 adapter->flags &= ~IGB_FLAG_DMAC;
2212 }
2213
2214 /* convert to rate of irq's per second */
2215 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2216 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2217 else
2218 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2219
2220 /* convert to rate of irq's per second */
2221 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2222 adapter->tx_itr_setting = adapter->rx_itr_setting;
2223 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2224 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2225 else
2226 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2227
2228 for (i = 0; i < adapter->num_q_vectors; i++) {
2229 struct igb_q_vector *q_vector = adapter->q_vector[i];
2230 q_vector->tx.work_limit = adapter->tx_work_limit;
2231 if (q_vector->rx.ring)
2232 q_vector->itr_val = adapter->rx_itr_setting;
2233 else
2234 q_vector->itr_val = adapter->tx_itr_setting;
2235 if (q_vector->itr_val && q_vector->itr_val <= 3)
2236 q_vector->itr_val = IGB_START_ITR;
2237 q_vector->set_itr = 1;
2238 }
2239
2240 return 0;
2241 }
2242
igb_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)2243 static int igb_get_coalesce(struct net_device *netdev,
2244 struct ethtool_coalesce *ec,
2245 struct kernel_ethtool_coalesce *kernel_coal,
2246 struct netlink_ext_ack *extack)
2247 {
2248 struct igb_adapter *adapter = netdev_priv(netdev);
2249
2250 if (adapter->rx_itr_setting <= 3)
2251 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2252 else
2253 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2254
2255 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2256 if (adapter->tx_itr_setting <= 3)
2257 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2258 else
2259 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2260 }
2261
2262 return 0;
2263 }
2264
igb_nway_reset(struct net_device * netdev)2265 static int igb_nway_reset(struct net_device *netdev)
2266 {
2267 struct igb_adapter *adapter = netdev_priv(netdev);
2268 if (netif_running(netdev))
2269 igb_reinit_locked(adapter);
2270 return 0;
2271 }
2272
igb_get_sset_count(struct net_device * netdev,int sset)2273 static int igb_get_sset_count(struct net_device *netdev, int sset)
2274 {
2275 switch (sset) {
2276 case ETH_SS_STATS:
2277 return IGB_STATS_LEN;
2278 case ETH_SS_TEST:
2279 return IGB_TEST_LEN;
2280 case ETH_SS_PRIV_FLAGS:
2281 return IGB_PRIV_FLAGS_STR_LEN;
2282 default:
2283 return -ENOTSUPP;
2284 }
2285 }
2286
igb_get_ethtool_stats(struct net_device * netdev,struct ethtool_stats * stats,u64 * data)2287 static void igb_get_ethtool_stats(struct net_device *netdev,
2288 struct ethtool_stats *stats, u64 *data)
2289 {
2290 struct igb_adapter *adapter = netdev_priv(netdev);
2291 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2292 unsigned int start;
2293 struct igb_ring *ring;
2294 int i, j;
2295 char *p;
2296
2297 spin_lock(&adapter->stats64_lock);
2298 igb_update_stats(adapter);
2299
2300 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2301 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2302 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2303 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2304 }
2305 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2306 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2307 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2308 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2309 }
2310 for (j = 0; j < adapter->num_tx_queues; j++) {
2311 u64 restart2;
2312
2313 ring = adapter->tx_ring[j];
2314 do {
2315 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2316 data[i] = ring->tx_stats.packets;
2317 data[i+1] = ring->tx_stats.bytes;
2318 data[i+2] = ring->tx_stats.restart_queue;
2319 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2320 do {
2321 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2322 restart2 = ring->tx_stats.restart_queue2;
2323 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2324 data[i+2] += restart2;
2325
2326 i += IGB_TX_QUEUE_STATS_LEN;
2327 }
2328 for (j = 0; j < adapter->num_rx_queues; j++) {
2329 ring = adapter->rx_ring[j];
2330 do {
2331 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2332 data[i] = ring->rx_stats.packets;
2333 data[i+1] = ring->rx_stats.bytes;
2334 data[i+2] = ring->rx_stats.drops;
2335 data[i+3] = ring->rx_stats.csum_err;
2336 data[i+4] = ring->rx_stats.alloc_failed;
2337 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2338 i += IGB_RX_QUEUE_STATS_LEN;
2339 }
2340 spin_unlock(&adapter->stats64_lock);
2341 }
2342
igb_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2343 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2344 {
2345 struct igb_adapter *adapter = netdev_priv(netdev);
2346 u8 *p = data;
2347 int i;
2348
2349 switch (stringset) {
2350 case ETH_SS_TEST:
2351 memcpy(data, igb_gstrings_test, sizeof(igb_gstrings_test));
2352 break;
2353 case ETH_SS_STATS:
2354 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++)
2355 ethtool_sprintf(&p,
2356 igb_gstrings_stats[i].stat_string);
2357 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++)
2358 ethtool_sprintf(&p,
2359 igb_gstrings_net_stats[i].stat_string);
2360 for (i = 0; i < adapter->num_tx_queues; i++) {
2361 ethtool_sprintf(&p, "tx_queue_%u_packets", i);
2362 ethtool_sprintf(&p, "tx_queue_%u_bytes", i);
2363 ethtool_sprintf(&p, "tx_queue_%u_restart", i);
2364 }
2365 for (i = 0; i < adapter->num_rx_queues; i++) {
2366 ethtool_sprintf(&p, "rx_queue_%u_packets", i);
2367 ethtool_sprintf(&p, "rx_queue_%u_bytes", i);
2368 ethtool_sprintf(&p, "rx_queue_%u_drops", i);
2369 ethtool_sprintf(&p, "rx_queue_%u_csum_err", i);
2370 ethtool_sprintf(&p, "rx_queue_%u_alloc_failed", i);
2371 }
2372 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2373 break;
2374 case ETH_SS_PRIV_FLAGS:
2375 memcpy(data, igb_priv_flags_strings,
2376 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
2377 break;
2378 }
2379 }
2380
igb_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)2381 static int igb_get_ts_info(struct net_device *dev,
2382 struct ethtool_ts_info *info)
2383 {
2384 struct igb_adapter *adapter = netdev_priv(dev);
2385
2386 if (adapter->ptp_clock)
2387 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2388 else
2389 info->phc_index = -1;
2390
2391 switch (adapter->hw.mac.type) {
2392 case e1000_82575:
2393 info->so_timestamping =
2394 SOF_TIMESTAMPING_TX_SOFTWARE |
2395 SOF_TIMESTAMPING_RX_SOFTWARE |
2396 SOF_TIMESTAMPING_SOFTWARE;
2397 return 0;
2398 case e1000_82576:
2399 case e1000_82580:
2400 case e1000_i350:
2401 case e1000_i354:
2402 case e1000_i210:
2403 case e1000_i211:
2404 info->so_timestamping =
2405 SOF_TIMESTAMPING_TX_SOFTWARE |
2406 SOF_TIMESTAMPING_RX_SOFTWARE |
2407 SOF_TIMESTAMPING_SOFTWARE |
2408 SOF_TIMESTAMPING_TX_HARDWARE |
2409 SOF_TIMESTAMPING_RX_HARDWARE |
2410 SOF_TIMESTAMPING_RAW_HARDWARE;
2411
2412 info->tx_types =
2413 BIT(HWTSTAMP_TX_OFF) |
2414 BIT(HWTSTAMP_TX_ON);
2415
2416 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2417
2418 /* 82576 does not support timestamping all packets. */
2419 if (adapter->hw.mac.type >= e1000_82580)
2420 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2421 else
2422 info->rx_filters |=
2423 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2424 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2425 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2426
2427 return 0;
2428 default:
2429 return -EOPNOTSUPP;
2430 }
2431 }
2432
2433 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
igb_get_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2434 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2435 struct ethtool_rxnfc *cmd)
2436 {
2437 struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2438 struct igb_nfc_filter *rule = NULL;
2439
2440 /* report total rule count */
2441 cmd->data = IGB_MAX_RXNFC_FILTERS;
2442
2443 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2444 if (fsp->location <= rule->sw_idx)
2445 break;
2446 }
2447
2448 if (!rule || fsp->location != rule->sw_idx)
2449 return -EINVAL;
2450
2451 if (rule->filter.match_flags) {
2452 fsp->flow_type = ETHER_FLOW;
2453 fsp->ring_cookie = rule->action;
2454 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2455 fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2456 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2457 }
2458 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2459 fsp->flow_type |= FLOW_EXT;
2460 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2461 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2462 }
2463 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2464 ether_addr_copy(fsp->h_u.ether_spec.h_dest,
2465 rule->filter.dst_addr);
2466 /* As we only support matching by the full
2467 * mask, return the mask to userspace
2468 */
2469 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest);
2470 }
2471 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2472 ether_addr_copy(fsp->h_u.ether_spec.h_source,
2473 rule->filter.src_addr);
2474 /* As we only support matching by the full
2475 * mask, return the mask to userspace
2476 */
2477 eth_broadcast_addr(fsp->m_u.ether_spec.h_source);
2478 }
2479
2480 return 0;
2481 }
2482 return -EINVAL;
2483 }
2484
igb_get_ethtool_nfc_all(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd,u32 * rule_locs)2485 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2486 struct ethtool_rxnfc *cmd,
2487 u32 *rule_locs)
2488 {
2489 struct igb_nfc_filter *rule;
2490 int cnt = 0;
2491
2492 /* report total rule count */
2493 cmd->data = IGB_MAX_RXNFC_FILTERS;
2494
2495 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2496 if (cnt == cmd->rule_cnt)
2497 return -EMSGSIZE;
2498 rule_locs[cnt] = rule->sw_idx;
2499 cnt++;
2500 }
2501
2502 cmd->rule_cnt = cnt;
2503
2504 return 0;
2505 }
2506
igb_get_rss_hash_opts(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2507 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2508 struct ethtool_rxnfc *cmd)
2509 {
2510 cmd->data = 0;
2511
2512 /* Report default options for RSS on igb */
2513 switch (cmd->flow_type) {
2514 case TCP_V4_FLOW:
2515 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2516 fallthrough;
2517 case UDP_V4_FLOW:
2518 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2519 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2520 fallthrough;
2521 case SCTP_V4_FLOW:
2522 case AH_ESP_V4_FLOW:
2523 case AH_V4_FLOW:
2524 case ESP_V4_FLOW:
2525 case IPV4_FLOW:
2526 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2527 break;
2528 case TCP_V6_FLOW:
2529 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2530 fallthrough;
2531 case UDP_V6_FLOW:
2532 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2533 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2534 fallthrough;
2535 case SCTP_V6_FLOW:
2536 case AH_ESP_V6_FLOW:
2537 case AH_V6_FLOW:
2538 case ESP_V6_FLOW:
2539 case IPV6_FLOW:
2540 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2541 break;
2542 default:
2543 return -EINVAL;
2544 }
2545
2546 return 0;
2547 }
2548
igb_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2549 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2550 u32 *rule_locs)
2551 {
2552 struct igb_adapter *adapter = netdev_priv(dev);
2553 int ret = -EOPNOTSUPP;
2554
2555 switch (cmd->cmd) {
2556 case ETHTOOL_GRXRINGS:
2557 cmd->data = adapter->num_rx_queues;
2558 ret = 0;
2559 break;
2560 case ETHTOOL_GRXCLSRLCNT:
2561 cmd->rule_cnt = adapter->nfc_filter_count;
2562 ret = 0;
2563 break;
2564 case ETHTOOL_GRXCLSRULE:
2565 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2566 break;
2567 case ETHTOOL_GRXCLSRLALL:
2568 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2569 break;
2570 case ETHTOOL_GRXFH:
2571 ret = igb_get_rss_hash_opts(adapter, cmd);
2572 break;
2573 default:
2574 break;
2575 }
2576
2577 return ret;
2578 }
2579
2580 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2581 IGB_FLAG_RSS_FIELD_IPV6_UDP)
igb_set_rss_hash_opt(struct igb_adapter * adapter,struct ethtool_rxnfc * nfc)2582 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2583 struct ethtool_rxnfc *nfc)
2584 {
2585 u32 flags = adapter->flags;
2586
2587 /* RSS does not support anything other than hashing
2588 * to queues on src and dst IPs and ports
2589 */
2590 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2591 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2592 return -EINVAL;
2593
2594 switch (nfc->flow_type) {
2595 case TCP_V4_FLOW:
2596 case TCP_V6_FLOW:
2597 if (!(nfc->data & RXH_IP_SRC) ||
2598 !(nfc->data & RXH_IP_DST) ||
2599 !(nfc->data & RXH_L4_B_0_1) ||
2600 !(nfc->data & RXH_L4_B_2_3))
2601 return -EINVAL;
2602 break;
2603 case UDP_V4_FLOW:
2604 if (!(nfc->data & RXH_IP_SRC) ||
2605 !(nfc->data & RXH_IP_DST))
2606 return -EINVAL;
2607 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2608 case 0:
2609 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2610 break;
2611 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2612 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2613 break;
2614 default:
2615 return -EINVAL;
2616 }
2617 break;
2618 case UDP_V6_FLOW:
2619 if (!(nfc->data & RXH_IP_SRC) ||
2620 !(nfc->data & RXH_IP_DST))
2621 return -EINVAL;
2622 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2623 case 0:
2624 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2625 break;
2626 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2627 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2628 break;
2629 default:
2630 return -EINVAL;
2631 }
2632 break;
2633 case AH_ESP_V4_FLOW:
2634 case AH_V4_FLOW:
2635 case ESP_V4_FLOW:
2636 case SCTP_V4_FLOW:
2637 case AH_ESP_V6_FLOW:
2638 case AH_V6_FLOW:
2639 case ESP_V6_FLOW:
2640 case SCTP_V6_FLOW:
2641 if (!(nfc->data & RXH_IP_SRC) ||
2642 !(nfc->data & RXH_IP_DST) ||
2643 (nfc->data & RXH_L4_B_0_1) ||
2644 (nfc->data & RXH_L4_B_2_3))
2645 return -EINVAL;
2646 break;
2647 default:
2648 return -EINVAL;
2649 }
2650
2651 /* if we changed something we need to update flags */
2652 if (flags != adapter->flags) {
2653 struct e1000_hw *hw = &adapter->hw;
2654 u32 mrqc = rd32(E1000_MRQC);
2655
2656 if ((flags & UDP_RSS_FLAGS) &&
2657 !(adapter->flags & UDP_RSS_FLAGS))
2658 dev_err(&adapter->pdev->dev,
2659 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2660
2661 adapter->flags = flags;
2662
2663 /* Perform hash on these packet types */
2664 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2665 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2666 E1000_MRQC_RSS_FIELD_IPV6 |
2667 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2668
2669 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2670 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2671
2672 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2673 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2674
2675 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2676 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2677
2678 wr32(E1000_MRQC, mrqc);
2679 }
2680
2681 return 0;
2682 }
2683
igb_rxnfc_write_etype_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2684 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2685 struct igb_nfc_filter *input)
2686 {
2687 struct e1000_hw *hw = &adapter->hw;
2688 u8 i;
2689 u32 etqf;
2690 u16 etype;
2691
2692 /* find an empty etype filter register */
2693 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2694 if (!adapter->etype_bitmap[i])
2695 break;
2696 }
2697 if (i == MAX_ETYPE_FILTER) {
2698 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2699 return -EINVAL;
2700 }
2701
2702 adapter->etype_bitmap[i] = true;
2703
2704 etqf = rd32(E1000_ETQF(i));
2705 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2706
2707 etqf |= E1000_ETQF_FILTER_ENABLE;
2708 etqf &= ~E1000_ETQF_ETYPE_MASK;
2709 etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2710
2711 etqf &= ~E1000_ETQF_QUEUE_MASK;
2712 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2713 & E1000_ETQF_QUEUE_MASK);
2714 etqf |= E1000_ETQF_QUEUE_ENABLE;
2715
2716 wr32(E1000_ETQF(i), etqf);
2717
2718 input->etype_reg_index = i;
2719
2720 return 0;
2721 }
2722
igb_rxnfc_write_vlan_prio_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2723 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2724 struct igb_nfc_filter *input)
2725 {
2726 struct e1000_hw *hw = &adapter->hw;
2727 u8 vlan_priority;
2728 u16 queue_index;
2729 u32 vlapqf;
2730
2731 vlapqf = rd32(E1000_VLAPQF);
2732 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2733 >> VLAN_PRIO_SHIFT;
2734 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2735
2736 /* check whether this vlan prio is already set */
2737 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2738 (queue_index != input->action)) {
2739 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2740 return -EEXIST;
2741 }
2742
2743 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2744 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2745
2746 wr32(E1000_VLAPQF, vlapqf);
2747
2748 return 0;
2749 }
2750
igb_add_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2751 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2752 {
2753 struct e1000_hw *hw = &adapter->hw;
2754 int err = -EINVAL;
2755
2756 if (hw->mac.type == e1000_i210 &&
2757 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) {
2758 dev_err(&adapter->pdev->dev,
2759 "i210 doesn't support flow classification rules specifying only source addresses.\n");
2760 return -EOPNOTSUPP;
2761 }
2762
2763 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2764 err = igb_rxnfc_write_etype_filter(adapter, input);
2765 if (err)
2766 return err;
2767 }
2768
2769 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2770 err = igb_add_mac_steering_filter(adapter,
2771 input->filter.dst_addr,
2772 input->action, 0);
2773 err = min_t(int, err, 0);
2774 if (err)
2775 return err;
2776 }
2777
2778 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2779 err = igb_add_mac_steering_filter(adapter,
2780 input->filter.src_addr,
2781 input->action,
2782 IGB_MAC_STATE_SRC_ADDR);
2783 err = min_t(int, err, 0);
2784 if (err)
2785 return err;
2786 }
2787
2788 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2789 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
2790
2791 return err;
2792 }
2793
igb_clear_etype_filter_regs(struct igb_adapter * adapter,u16 reg_index)2794 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2795 u16 reg_index)
2796 {
2797 struct e1000_hw *hw = &adapter->hw;
2798 u32 etqf = rd32(E1000_ETQF(reg_index));
2799
2800 etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2801 etqf &= ~E1000_ETQF_QUEUE_MASK;
2802 etqf &= ~E1000_ETQF_FILTER_ENABLE;
2803
2804 wr32(E1000_ETQF(reg_index), etqf);
2805
2806 adapter->etype_bitmap[reg_index] = false;
2807 }
2808
igb_clear_vlan_prio_filter(struct igb_adapter * adapter,u16 vlan_tci)2809 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2810 u16 vlan_tci)
2811 {
2812 struct e1000_hw *hw = &adapter->hw;
2813 u8 vlan_priority;
2814 u32 vlapqf;
2815
2816 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2817
2818 vlapqf = rd32(E1000_VLAPQF);
2819 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2820 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2821 E1000_VLAPQF_QUEUE_MASK);
2822
2823 wr32(E1000_VLAPQF, vlapqf);
2824 }
2825
igb_erase_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2826 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2827 {
2828 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2829 igb_clear_etype_filter_regs(adapter,
2830 input->etype_reg_index);
2831
2832 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2833 igb_clear_vlan_prio_filter(adapter,
2834 ntohs(input->filter.vlan_tci));
2835
2836 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR)
2837 igb_del_mac_steering_filter(adapter, input->filter.src_addr,
2838 input->action,
2839 IGB_MAC_STATE_SRC_ADDR);
2840
2841 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR)
2842 igb_del_mac_steering_filter(adapter, input->filter.dst_addr,
2843 input->action, 0);
2844
2845 return 0;
2846 }
2847
igb_update_ethtool_nfc_entry(struct igb_adapter * adapter,struct igb_nfc_filter * input,u16 sw_idx)2848 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2849 struct igb_nfc_filter *input,
2850 u16 sw_idx)
2851 {
2852 struct igb_nfc_filter *rule, *parent;
2853 int err = -EINVAL;
2854
2855 parent = NULL;
2856 rule = NULL;
2857
2858 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2859 /* hash found, or no matching entry */
2860 if (rule->sw_idx >= sw_idx)
2861 break;
2862 parent = rule;
2863 }
2864
2865 /* if there is an old rule occupying our place remove it */
2866 if (rule && (rule->sw_idx == sw_idx)) {
2867 if (!input)
2868 err = igb_erase_filter(adapter, rule);
2869
2870 hlist_del(&rule->nfc_node);
2871 kfree(rule);
2872 adapter->nfc_filter_count--;
2873 }
2874
2875 /* If no input this was a delete, err should be 0 if a rule was
2876 * successfully found and removed from the list else -EINVAL
2877 */
2878 if (!input)
2879 return err;
2880
2881 /* initialize node */
2882 INIT_HLIST_NODE(&input->nfc_node);
2883
2884 /* add filter to the list */
2885 if (parent)
2886 hlist_add_behind(&input->nfc_node, &parent->nfc_node);
2887 else
2888 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2889
2890 /* update counts */
2891 adapter->nfc_filter_count++;
2892
2893 return 0;
2894 }
2895
igb_add_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2896 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2897 struct ethtool_rxnfc *cmd)
2898 {
2899 struct net_device *netdev = adapter->netdev;
2900 struct ethtool_rx_flow_spec *fsp =
2901 (struct ethtool_rx_flow_spec *)&cmd->fs;
2902 struct igb_nfc_filter *input, *rule;
2903 int err = 0;
2904
2905 if (!(netdev->hw_features & NETIF_F_NTUPLE))
2906 return -EOPNOTSUPP;
2907
2908 /* Don't allow programming if the action is a queue greater than
2909 * the number of online Rx queues.
2910 */
2911 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2912 (fsp->ring_cookie >= adapter->num_rx_queues)) {
2913 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2914 return -EINVAL;
2915 }
2916
2917 /* Don't allow indexes to exist outside of available space */
2918 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2919 dev_err(&adapter->pdev->dev, "Location out of range\n");
2920 return -EINVAL;
2921 }
2922
2923 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2924 return -EINVAL;
2925
2926 input = kzalloc(sizeof(*input), GFP_KERNEL);
2927 if (!input)
2928 return -ENOMEM;
2929
2930 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2931 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2932 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2933 }
2934
2935 /* Only support matching addresses by the full mask */
2936 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) {
2937 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR;
2938 ether_addr_copy(input->filter.src_addr,
2939 fsp->h_u.ether_spec.h_source);
2940 }
2941
2942 /* Only support matching addresses by the full mask */
2943 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) {
2944 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR;
2945 ether_addr_copy(input->filter.dst_addr,
2946 fsp->h_u.ether_spec.h_dest);
2947 }
2948
2949 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2950 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2951 err = -EINVAL;
2952 goto err_out;
2953 }
2954 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2955 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2956 }
2957
2958 input->action = fsp->ring_cookie;
2959 input->sw_idx = fsp->location;
2960
2961 spin_lock(&adapter->nfc_lock);
2962
2963 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2964 if (!memcmp(&input->filter, &rule->filter,
2965 sizeof(input->filter))) {
2966 err = -EEXIST;
2967 dev_err(&adapter->pdev->dev,
2968 "ethtool: this filter is already set\n");
2969 goto err_out_w_lock;
2970 }
2971 }
2972
2973 err = igb_add_filter(adapter, input);
2974 if (err)
2975 goto err_out_w_lock;
2976
2977 err = igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2978 if (err)
2979 goto err_out_input_filter;
2980
2981 spin_unlock(&adapter->nfc_lock);
2982 return 0;
2983
2984 err_out_input_filter:
2985 igb_erase_filter(adapter, input);
2986 err_out_w_lock:
2987 spin_unlock(&adapter->nfc_lock);
2988 err_out:
2989 kfree(input);
2990 return err;
2991 }
2992
igb_del_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2993 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
2994 struct ethtool_rxnfc *cmd)
2995 {
2996 struct ethtool_rx_flow_spec *fsp =
2997 (struct ethtool_rx_flow_spec *)&cmd->fs;
2998 int err;
2999
3000 spin_lock(&adapter->nfc_lock);
3001 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
3002 spin_unlock(&adapter->nfc_lock);
3003
3004 return err;
3005 }
3006
igb_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)3007 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3008 {
3009 struct igb_adapter *adapter = netdev_priv(dev);
3010 int ret = -EOPNOTSUPP;
3011
3012 switch (cmd->cmd) {
3013 case ETHTOOL_SRXFH:
3014 ret = igb_set_rss_hash_opt(adapter, cmd);
3015 break;
3016 case ETHTOOL_SRXCLSRLINS:
3017 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
3018 break;
3019 case ETHTOOL_SRXCLSRLDEL:
3020 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
3021 break;
3022 default:
3023 break;
3024 }
3025
3026 return ret;
3027 }
3028
igb_get_eee(struct net_device * netdev,struct ethtool_eee * edata)3029 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3030 {
3031 struct igb_adapter *adapter = netdev_priv(netdev);
3032 struct e1000_hw *hw = &adapter->hw;
3033 u32 ret_val;
3034 u16 phy_data;
3035
3036 if ((hw->mac.type < e1000_i350) ||
3037 (hw->phy.media_type != e1000_media_type_copper))
3038 return -EOPNOTSUPP;
3039
3040 edata->supported = (SUPPORTED_1000baseT_Full |
3041 SUPPORTED_100baseT_Full);
3042 if (!hw->dev_spec._82575.eee_disable)
3043 edata->advertised =
3044 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
3045
3046 /* The IPCNFG and EEER registers are not supported on I354. */
3047 if (hw->mac.type == e1000_i354) {
3048 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
3049 } else {
3050 u32 eeer;
3051
3052 eeer = rd32(E1000_EEER);
3053
3054 /* EEE status on negotiated link */
3055 if (eeer & E1000_EEER_EEE_NEG)
3056 edata->eee_active = true;
3057
3058 if (eeer & E1000_EEER_TX_LPI_EN)
3059 edata->tx_lpi_enabled = true;
3060 }
3061
3062 /* EEE Link Partner Advertised */
3063 switch (hw->mac.type) {
3064 case e1000_i350:
3065 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
3066 &phy_data);
3067 if (ret_val)
3068 return -ENODATA;
3069
3070 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3071 break;
3072 case e1000_i354:
3073 case e1000_i210:
3074 case e1000_i211:
3075 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3076 E1000_EEE_LP_ADV_DEV_I210,
3077 &phy_data);
3078 if (ret_val)
3079 return -ENODATA;
3080
3081 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3082
3083 break;
3084 default:
3085 break;
3086 }
3087
3088 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3089
3090 if ((hw->mac.type == e1000_i354) &&
3091 (edata->eee_enabled))
3092 edata->tx_lpi_enabled = true;
3093
3094 /* Report correct negotiated EEE status for devices that
3095 * wrongly report EEE at half-duplex
3096 */
3097 if (adapter->link_duplex == HALF_DUPLEX) {
3098 edata->eee_enabled = false;
3099 edata->eee_active = false;
3100 edata->tx_lpi_enabled = false;
3101 edata->advertised &= ~edata->advertised;
3102 }
3103
3104 return 0;
3105 }
3106
igb_set_eee(struct net_device * netdev,struct ethtool_eee * edata)3107 static int igb_set_eee(struct net_device *netdev,
3108 struct ethtool_eee *edata)
3109 {
3110 struct igb_adapter *adapter = netdev_priv(netdev);
3111 struct e1000_hw *hw = &adapter->hw;
3112 struct ethtool_eee eee_curr;
3113 bool adv1g_eee = true, adv100m_eee = true;
3114 s32 ret_val;
3115
3116 if ((hw->mac.type < e1000_i350) ||
3117 (hw->phy.media_type != e1000_media_type_copper))
3118 return -EOPNOTSUPP;
3119
3120 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3121
3122 ret_val = igb_get_eee(netdev, &eee_curr);
3123 if (ret_val)
3124 return ret_val;
3125
3126 if (eee_curr.eee_enabled) {
3127 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3128 dev_err(&adapter->pdev->dev,
3129 "Setting EEE tx-lpi is not supported\n");
3130 return -EINVAL;
3131 }
3132
3133 /* Tx LPI timer is not implemented currently */
3134 if (edata->tx_lpi_timer) {
3135 dev_err(&adapter->pdev->dev,
3136 "Setting EEE Tx LPI timer is not supported\n");
3137 return -EINVAL;
3138 }
3139
3140 if (!edata->advertised || (edata->advertised &
3141 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
3142 dev_err(&adapter->pdev->dev,
3143 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
3144 return -EINVAL;
3145 }
3146 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3147 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
3148
3149 } else if (!edata->eee_enabled) {
3150 dev_err(&adapter->pdev->dev,
3151 "Setting EEE options are not supported with EEE disabled\n");
3152 return -EINVAL;
3153 }
3154
3155 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
3156 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3157 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
3158 adapter->flags |= IGB_FLAG_EEE;
3159
3160 /* reset link */
3161 if (netif_running(netdev))
3162 igb_reinit_locked(adapter);
3163 else
3164 igb_reset(adapter);
3165 }
3166
3167 if (hw->mac.type == e1000_i354)
3168 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3169 else
3170 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3171
3172 if (ret_val) {
3173 dev_err(&adapter->pdev->dev,
3174 "Problem setting EEE advertisement options\n");
3175 return -EINVAL;
3176 }
3177
3178 return 0;
3179 }
3180
igb_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)3181 static int igb_get_module_info(struct net_device *netdev,
3182 struct ethtool_modinfo *modinfo)
3183 {
3184 struct igb_adapter *adapter = netdev_priv(netdev);
3185 struct e1000_hw *hw = &adapter->hw;
3186 u32 status = 0;
3187 u16 sff8472_rev, addr_mode;
3188 bool page_swap = false;
3189
3190 if ((hw->phy.media_type == e1000_media_type_copper) ||
3191 (hw->phy.media_type == e1000_media_type_unknown))
3192 return -EOPNOTSUPP;
3193
3194 /* Check whether we support SFF-8472 or not */
3195 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
3196 if (status)
3197 return -EIO;
3198
3199 /* addressing mode is not supported */
3200 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
3201 if (status)
3202 return -EIO;
3203
3204 /* addressing mode is not supported */
3205 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3206 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3207 page_swap = true;
3208 }
3209
3210 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3211 /* We have an SFP, but it does not support SFF-8472 */
3212 modinfo->type = ETH_MODULE_SFF_8079;
3213 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3214 } else {
3215 /* We have an SFP which supports a revision of SFF-8472 */
3216 modinfo->type = ETH_MODULE_SFF_8472;
3217 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3218 }
3219
3220 return 0;
3221 }
3222
igb_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)3223 static int igb_get_module_eeprom(struct net_device *netdev,
3224 struct ethtool_eeprom *ee, u8 *data)
3225 {
3226 struct igb_adapter *adapter = netdev_priv(netdev);
3227 struct e1000_hw *hw = &adapter->hw;
3228 u32 status = 0;
3229 u16 *dataword;
3230 u16 first_word, last_word;
3231 int i = 0;
3232
3233 if (ee->len == 0)
3234 return -EINVAL;
3235
3236 first_word = ee->offset >> 1;
3237 last_word = (ee->offset + ee->len - 1) >> 1;
3238
3239 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16),
3240 GFP_KERNEL);
3241 if (!dataword)
3242 return -ENOMEM;
3243
3244 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3245 for (i = 0; i < last_word - first_word + 1; i++) {
3246 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3247 &dataword[i]);
3248 if (status) {
3249 /* Error occurred while reading module */
3250 kfree(dataword);
3251 return -EIO;
3252 }
3253
3254 be16_to_cpus(&dataword[i]);
3255 }
3256
3257 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3258 kfree(dataword);
3259
3260 return 0;
3261 }
3262
igb_ethtool_begin(struct net_device * netdev)3263 static int igb_ethtool_begin(struct net_device *netdev)
3264 {
3265 struct igb_adapter *adapter = netdev_priv(netdev);
3266 pm_runtime_get_sync(&adapter->pdev->dev);
3267 return 0;
3268 }
3269
igb_ethtool_complete(struct net_device * netdev)3270 static void igb_ethtool_complete(struct net_device *netdev)
3271 {
3272 struct igb_adapter *adapter = netdev_priv(netdev);
3273 pm_runtime_put(&adapter->pdev->dev);
3274 }
3275
igb_get_rxfh_indir_size(struct net_device * netdev)3276 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3277 {
3278 return IGB_RETA_SIZE;
3279 }
3280
igb_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)3281 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3282 u8 *hfunc)
3283 {
3284 struct igb_adapter *adapter = netdev_priv(netdev);
3285 int i;
3286
3287 if (hfunc)
3288 *hfunc = ETH_RSS_HASH_TOP;
3289 if (!indir)
3290 return 0;
3291 for (i = 0; i < IGB_RETA_SIZE; i++)
3292 indir[i] = adapter->rss_indir_tbl[i];
3293
3294 return 0;
3295 }
3296
igb_write_rss_indir_tbl(struct igb_adapter * adapter)3297 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3298 {
3299 struct e1000_hw *hw = &adapter->hw;
3300 u32 reg = E1000_RETA(0);
3301 u32 shift = 0;
3302 int i = 0;
3303
3304 switch (hw->mac.type) {
3305 case e1000_82575:
3306 shift = 6;
3307 break;
3308 case e1000_82576:
3309 /* 82576 supports 2 RSS queues for SR-IOV */
3310 if (adapter->vfs_allocated_count)
3311 shift = 3;
3312 break;
3313 default:
3314 break;
3315 }
3316
3317 while (i < IGB_RETA_SIZE) {
3318 u32 val = 0;
3319 int j;
3320
3321 for (j = 3; j >= 0; j--) {
3322 val <<= 8;
3323 val |= adapter->rss_indir_tbl[i + j];
3324 }
3325
3326 wr32(reg, val << shift);
3327 reg += 4;
3328 i += 4;
3329 }
3330 }
3331
igb_set_rxfh(struct net_device * netdev,const u32 * indir,const u8 * key,const u8 hfunc)3332 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
3333 const u8 *key, const u8 hfunc)
3334 {
3335 struct igb_adapter *adapter = netdev_priv(netdev);
3336 struct e1000_hw *hw = &adapter->hw;
3337 int i;
3338 u32 num_queues;
3339
3340 /* We do not allow change in unsupported parameters */
3341 if (key ||
3342 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3343 return -EOPNOTSUPP;
3344 if (!indir)
3345 return 0;
3346
3347 num_queues = adapter->rss_queues;
3348
3349 switch (hw->mac.type) {
3350 case e1000_82576:
3351 /* 82576 supports 2 RSS queues for SR-IOV */
3352 if (adapter->vfs_allocated_count)
3353 num_queues = 2;
3354 break;
3355 default:
3356 break;
3357 }
3358
3359 /* Verify user input. */
3360 for (i = 0; i < IGB_RETA_SIZE; i++)
3361 if (indir[i] >= num_queues)
3362 return -EINVAL;
3363
3364
3365 for (i = 0; i < IGB_RETA_SIZE; i++)
3366 adapter->rss_indir_tbl[i] = indir[i];
3367
3368 igb_write_rss_indir_tbl(adapter);
3369
3370 return 0;
3371 }
3372
igb_max_channels(struct igb_adapter * adapter)3373 static unsigned int igb_max_channels(struct igb_adapter *adapter)
3374 {
3375 return igb_get_max_rss_queues(adapter);
3376 }
3377
igb_get_channels(struct net_device * netdev,struct ethtool_channels * ch)3378 static void igb_get_channels(struct net_device *netdev,
3379 struct ethtool_channels *ch)
3380 {
3381 struct igb_adapter *adapter = netdev_priv(netdev);
3382
3383 /* Report maximum channels */
3384 ch->max_combined = igb_max_channels(adapter);
3385
3386 /* Report info for other vector */
3387 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
3388 ch->max_other = NON_Q_VECTORS;
3389 ch->other_count = NON_Q_VECTORS;
3390 }
3391
3392 ch->combined_count = adapter->rss_queues;
3393 }
3394
igb_set_channels(struct net_device * netdev,struct ethtool_channels * ch)3395 static int igb_set_channels(struct net_device *netdev,
3396 struct ethtool_channels *ch)
3397 {
3398 struct igb_adapter *adapter = netdev_priv(netdev);
3399 unsigned int count = ch->combined_count;
3400 unsigned int max_combined = 0;
3401
3402 /* Verify they are not requesting separate vectors */
3403 if (!count || ch->rx_count || ch->tx_count)
3404 return -EINVAL;
3405
3406 /* Verify other_count is valid and has not been changed */
3407 if (ch->other_count != NON_Q_VECTORS)
3408 return -EINVAL;
3409
3410 /* Verify the number of channels doesn't exceed hw limits */
3411 max_combined = igb_max_channels(adapter);
3412 if (count > max_combined)
3413 return -EINVAL;
3414
3415 if (count != adapter->rss_queues) {
3416 adapter->rss_queues = count;
3417 igb_set_flag_queue_pairs(adapter, max_combined);
3418
3419 /* Hardware has to reinitialize queues and interrupts to
3420 * match the new configuration.
3421 */
3422 return igb_reinit_queues(adapter);
3423 }
3424
3425 return 0;
3426 }
3427
igb_get_priv_flags(struct net_device * netdev)3428 static u32 igb_get_priv_flags(struct net_device *netdev)
3429 {
3430 struct igb_adapter *adapter = netdev_priv(netdev);
3431 u32 priv_flags = 0;
3432
3433 if (adapter->flags & IGB_FLAG_RX_LEGACY)
3434 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;
3435
3436 return priv_flags;
3437 }
3438
igb_set_priv_flags(struct net_device * netdev,u32 priv_flags)3439 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3440 {
3441 struct igb_adapter *adapter = netdev_priv(netdev);
3442 unsigned int flags = adapter->flags;
3443
3444 flags &= ~IGB_FLAG_RX_LEGACY;
3445 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)
3446 flags |= IGB_FLAG_RX_LEGACY;
3447
3448 if (flags != adapter->flags) {
3449 adapter->flags = flags;
3450
3451 /* reset interface to repopulate queues */
3452 if (netif_running(netdev))
3453 igb_reinit_locked(adapter);
3454 }
3455
3456 return 0;
3457 }
3458
3459 static const struct ethtool_ops igb_ethtool_ops = {
3460 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3461 .get_drvinfo = igb_get_drvinfo,
3462 .get_regs_len = igb_get_regs_len,
3463 .get_regs = igb_get_regs,
3464 .get_wol = igb_get_wol,
3465 .set_wol = igb_set_wol,
3466 .get_msglevel = igb_get_msglevel,
3467 .set_msglevel = igb_set_msglevel,
3468 .nway_reset = igb_nway_reset,
3469 .get_link = igb_get_link,
3470 .get_eeprom_len = igb_get_eeprom_len,
3471 .get_eeprom = igb_get_eeprom,
3472 .set_eeprom = igb_set_eeprom,
3473 .get_ringparam = igb_get_ringparam,
3474 .set_ringparam = igb_set_ringparam,
3475 .get_pauseparam = igb_get_pauseparam,
3476 .set_pauseparam = igb_set_pauseparam,
3477 .self_test = igb_diag_test,
3478 .get_strings = igb_get_strings,
3479 .set_phys_id = igb_set_phys_id,
3480 .get_sset_count = igb_get_sset_count,
3481 .get_ethtool_stats = igb_get_ethtool_stats,
3482 .get_coalesce = igb_get_coalesce,
3483 .set_coalesce = igb_set_coalesce,
3484 .get_ts_info = igb_get_ts_info,
3485 .get_rxnfc = igb_get_rxnfc,
3486 .set_rxnfc = igb_set_rxnfc,
3487 .get_eee = igb_get_eee,
3488 .set_eee = igb_set_eee,
3489 .get_module_info = igb_get_module_info,
3490 .get_module_eeprom = igb_get_module_eeprom,
3491 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3492 .get_rxfh = igb_get_rxfh,
3493 .set_rxfh = igb_set_rxfh,
3494 .get_channels = igb_get_channels,
3495 .set_channels = igb_set_channels,
3496 .get_priv_flags = igb_get_priv_flags,
3497 .set_priv_flags = igb_set_priv_flags,
3498 .begin = igb_ethtool_begin,
3499 .complete = igb_ethtool_complete,
3500 .get_link_ksettings = igb_get_link_ksettings,
3501 .set_link_ksettings = igb_set_link_ksettings,
3502 };
3503
igb_set_ethtool_ops(struct net_device * netdev)3504 void igb_set_ethtool_ops(struct net_device *netdev)
3505 {
3506 netdev->ethtool_ops = &igb_ethtool_ops;
3507 }
3508