| /drivers/clocksource/ |
| D | acpi_pm.c | 147 u64 value1, value2; in verify_pmtmr_rate() local
153 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm); in verify_pmtmr_rate()
154 delta = (value2 - value1) & ACPI_PM_MASK; in verify_pmtmr_rate()
177 u64 value1, value2; in init_acpi_pm_clocksource() local
188 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm); in init_acpi_pm_clocksource()
189 if (value2 == value1) in init_acpi_pm_clocksource()
191 if (value2 > value1) in init_acpi_pm_clocksource()
193 if ((value2 < value1) && ((value2) < 0xFFF)) in init_acpi_pm_clocksource()
196 value1, value2); in init_acpi_pm_clocksource()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_timing_generator.c | 133 uint32_t value2 = dm_read_reg(tg->ctx, addr2); in dce60_timing_generator_enable_advanced_request() local
145 value2, in dce60_timing_generator_enable_advanced_request()
156 value2, in dce60_timing_generator_enable_advanced_request()
175 dm_write_reg(tg->ctx, addr2, value2); in dce60_timing_generator_enable_advanced_request()
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| /drivers/iio/pressure/ |
| D | dlhl60d.c | 141 int *value2, long mask) in dlh_read_raw() argument
179 *value2 = rem; in dlh_read_raw()
184 *value2 = DLH_NUM_TEMP_BITS; in dlh_read_raw()
194 *value2 = 100 * st->info.osdig * 100000; in dlh_read_raw()
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| /drivers/iio/adc/ |
| D | cpcap-adc.c | 539 unsigned short value2 = 0; in cpcap_adc_setup_bank() local
547 value2 |= CPCAP_BIT_THERMBIAS_EN; in cpcap_adc_setup_bank()
550 value2); in cpcap_adc_setup_bank()
569 value2 |= ato->adc_ps_factor_in; in cpcap_adc_setup_bank()
570 value2 |= ato->atox_ps_factor_in; in cpcap_adc_setup_bank()
575 value2 |= ato->adc_ps_factor_out; in cpcap_adc_setup_bank()
576 value2 |= ato->atox_ps_factor_out; in cpcap_adc_setup_bank()
600 value2); in cpcap_adc_setup_bank()
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| D | ti-ads131e08.c | 501 int *value2, long mask) in ads131e08_read_raw() argument
531 *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1; in ads131e08_read_raw()
547 int value2, long mask) in ads131e08_write_raw() argument
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| /drivers/net/wireless/ath/ath9k/ |
| D | ar9003_phy.c | 1085 s32 value, value2; in ar9003_hw_ani_control() local
1204 value2 = firstep_table[level] - in ar9003_hw_ani_control()
1207 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) in ar9003_hw_ani_control()
1208 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; in ar9003_hw_ani_control()
1209 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) in ar9003_hw_ani_control()
1210 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; in ar9003_hw_ani_control()
1213 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); in ar9003_hw_ani_control()
1230 value2, in ar9003_hw_ani_control()
1269 value2 = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1272 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) in ar9003_hw_ani_control()
[all …]
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| /drivers/media/usb/gspca/ |
| D | sn9c20x.c | 1365 u16 value2; in set_hvflip() local
1402 i2c_r2(gspca_dev, 0x20, &value2); in set_hvflip()
1403 value2 &= ~0xc0a0; in set_hvflip()
1405 value2 |= 0x8080; in set_hvflip()
1407 value2 |= 0x4020; in set_hvflip()
1408 i2c_w2(gspca_dev, 0x20, value2); in set_hvflip()
1413 i2c_r2(gspca_dev, 0x20, &value2); in set_hvflip()
1414 value2 &= ~0x0003; in set_hvflip()
1416 value2 |= 0x0002; in set_hvflip()
1418 value2 |= 0x0001; in set_hvflip()
[all …]
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| /drivers/ata/ |
| D | pata_pdc2027x.c | 80 u8 value0, value1, value2; member
98 u8 value0, value1, value2; member
315 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); in pdc2027x_set_piomode()
359 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); in pdc2027x_set_dmamode()
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| D | pata_macio.c | 445 unsigned int value, value2 = 0; in pata_macio_default_timings() local
450 value2 = 0x00033031; in pata_macio_default_timings()
455 value2 = 0x00002921; in pata_macio_default_timings()
470 priv->treg[0][1] = priv->treg[1][1] = value2; in pata_macio_default_timings()
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| /drivers/media/platform/qcom/camss/ |
| D | camss-ispif.c | 165 u32 value0, value1, value2, value3, value4, value5; in ispif_isr_8x96() local
169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); in ispif_isr_8x96()
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); in ispif_isr_8x96()
201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) in ispif_isr_8x96()
233 u32 value0, value1, value2; in ispif_isr_8x16() local
237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); in ispif_isr_8x16()
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); in ispif_isr_8x16()
260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) in ispif_isr_8x16()
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| /drivers/pinctrl/intel/ |
| D | pinctrl-intel.c | 618 u32 value2; in intel_config_get_debounce() local
625 value2 = readl(padcfg2); in intel_config_get_debounce()
627 if (!(value2 & PADCFG2_DEBEN)) in intel_config_get_debounce()
630 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; in intel_config_get_debounce()
769 u32 value0, value2; in intel_config_set_debounce() local
780 value2 = readl(padcfg2); in intel_config_set_debounce()
784 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); in intel_config_set_debounce()
797 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; in intel_config_set_debounce()
798 value2 |= PADCFG2_DEBEN; in intel_config_set_debounce()
802 writel(value2, padcfg2); in intel_config_set_debounce()
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| /drivers/acpi/ |
| D | acpi_lpss.c | 939 u32 value2 = LPSS_PMCSR_D3hot; in lpss_iosf_enter_d3_state() local
969 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
972 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
988 u32 value2 = LPSS_PMCSR_D0; in lpss_iosf_exit_d3_state() local
1002 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
1005 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
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| D | acpi_processor.c | 35 u8 value2 = 0; in acpi_processor_errata_piix4() local
115 pci_read_config_byte(dev, 0x77, &value2); in acpi_processor_errata_piix4()
116 if ((value1 & 0x80) || (value2 & 0x80)) in acpi_processor_errata_piix4()
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| /drivers/firmware/ |
| D | stratix10-rsu.c | 205 unsigned long long *value2 = (unsigned long long *)data->kaddr2; in rsu_dcmf_version_callback() local
210 priv->dcmf_version.dcmf2 = FIELD_GET(RSU_DCMF2_MASK, *value2); in rsu_dcmf_version_callback()
211 priv->dcmf_version.dcmf3 = FIELD_GET(RSU_DCMF3_MASK, *value2); in rsu_dcmf_version_callback()
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| /drivers/staging/media/tegra-vde/ |
| D | vde.c | 191 u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0; in tegra_vde_setup_frameid() local
197 tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); in tegra_vde_setup_frameid()
218 u32 value1, u32 value2) in tegra_vde_setup_iram_entry() argument
222 trace_vde_setup_iram_entry(table, row, value1, value2); in tegra_vde_setup_iram_entry()
225 iram_tables[0x20 * table + row * 2 + 1] = value2; in tegra_vde_setup_iram_entry()
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| /drivers/md/persistent-data/ |
| D | dm-btree.h | 75 int (*equal)(void *context, const void *value1, const void *value2);
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| D | dm-array.c | 628 static int block_equal(void *context, const void *value1, const void *value2) in block_equal() argument
630 return !memcmp(value1, value2, sizeof(__le64)); in block_equal()
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| /drivers/gpu/drm/radeon/ |
| D | radeon_dp_mst.c | 94 unsigned value1, value2; in radeon_dp_mst_set_stream_attrib() local
99 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; in radeon_dp_mst_set_stream_attrib()
101 if (!value1 && !value2) in radeon_dp_mst_set_stream_attrib()
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| /drivers/video/fbdev/ |
| D | ffb.c | 334 u32 value2; member
448 upa_writel(0, &dac->value2); in ffb_switch_from_graph()
451 FFB_DAC_CUR_CTRL_P1), &dac->value2); in ffb_switch_from_graph()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_link_encoder.c | 1227 uint32_t value2 = 0; in dcn10_link_encoder_update_mst_stream_allocation_table() local
1333 DP_MSE_16_MTP_KEEPOUT, &value2); in dcn10_link_encoder_update_mst_stream_allocation_table()
1336 if (!value1 && !value2) in dcn10_link_encoder_update_mst_stream_allocation_table()
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| /drivers/net/ethernet/sfc/falcon/ |
| D | bitfield.h | 277 field2, value2, \ argument
287 EF4_INSERT_FIELD_NATIVE((min), (max), field2, (value2)) | \
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 1507 uint32_t value2 = 0; in dce110_link_encoder_update_mst_stream_allocation_table() local
1612 DP_MSE_16_MTP_KEEPOUT, &value2); in dce110_link_encoder_update_mst_stream_allocation_table()
1615 if (!value1 && !value2) in dce110_link_encoder_update_mst_stream_allocation_table()
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| /drivers/net/ethernet/sfc/ |
| D | bitfield.h | 277 field2, value2, \ argument
296 EFX_INSERT_FIELD_NATIVE((min), (max), field2, (value2)) | \
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| /drivers/scsi/qla2xxx/ |
| D | qla_nx2.c | 3092 uint32_t addr1, addr2, value1, value2, data, selVal; in qla8044_minidump_process_rdmdio() local
3111 value2 = rdmdio->value_2; in qla8044_minidump_process_rdmdio()
3123 value2); in qla8044_minidump_process_rdmdio()
3149 selVal = (value2 << 18) | (value1 << 2) | 2; in qla8044_minidump_process_rdmdio()
3168 uint32_t addr1, addr2, value1, value2, poll, r_value; in qla8044_minidump_process_pollwr() local
3176 value2 = pollwr_hdr->value_2; in qla8044_minidump_process_pollwr()
3193 qla8044_wr_reg_indirect(vha, addr2, value2); in qla8044_minidump_process_pollwr()
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| /drivers/scsi/qla4xxx/ |
| D | ql4_nx.c | 2726 uint32_t addr1, addr2, value1, value2, data, selval; in qla4_84xx_minidump_process_rdmdio() local
2743 value2 = le32_to_cpu(rdmdio->value_2); in qla4_84xx_minidump_process_rdmdio()
2755 value2); in qla4_84xx_minidump_process_rdmdio()
2782 selval = (value2 << 18) | (value1 << 2) | 2; in qla4_84xx_minidump_process_rdmdio()
2800 uint32_t addr1, addr2, value1, value2, poll, r_value; in qla4_84xx_minidump_process_pollwr() local
2809 value2 = le32_to_cpu(pollwr_hdr->value_2); in qla4_84xx_minidump_process_pollwr()
2828 ha->isp_ops->wr_reg_indirect(ha, addr2, value2); in qla4_84xx_minidump_process_pollwr()
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