Searched refs:vgpu_vreg (Results 1 – 9 of 9) sorted by relevance
/drivers/gpu/drm/i915/gvt/ |
D | edid.c | 141 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in gmbus0_mmio_write() 143 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK; in gmbus0_mmio_write() 182 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { in gmbus1_mmio_write() 184 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; in gmbus1_mmio_write() 237 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) in gmbus1_mmio_write() 271 vgpu_vreg(vgpu, offset) = wvalue; in gmbus1_mmio_write() 299 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read() 310 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count); in gmbus3_mmio_read() 311 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read() 332 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read() [all …]
|
D | interrupt.c | 182 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler() 183 (vgpu_vreg(vgpu, reg) ^ imr)); in intel_vgpu_reg_imr_handler() 185 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler() 211 u32 virtual_ier = vgpu_vreg(vgpu, reg); in intel_vgpu_reg_master_irq_handler() 223 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; in intel_vgpu_reg_master_irq_handler() 224 vgpu_vreg(vgpu, reg) |= ier; in intel_vgpu_reg_master_irq_handler() 253 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler() 254 (vgpu_vreg(vgpu, reg) ^ ier)); in intel_vgpu_reg_ier_handler() 256 vgpu_vreg(vgpu, reg) = ier; in intel_vgpu_reg_ier_handler() 291 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler() [all …]
|
D | handlers.c | 78 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg() 84 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg() 286 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write() 309 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write() 310 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write() 321 data = vgpu_vreg(vgpu, offset); in gdrst_mmio_write() 358 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write() 380 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { in pch_pp_control_mmio_write() 398 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) in transconf_mmio_write() 399 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; in transconf_mmio_write() [all …]
|
D | execlist.c | 98 status.ldw = vgpu_vreg(vgpu, status_reg); in emulate_execlist_status() 99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status() 117 vgpu_vreg(vgpu, status_reg) = status.ldw; in emulate_execlist_status() 118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status() 139 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); in emulate_csb_update() 152 vgpu_vreg(vgpu, offset) = status->ldw; in emulate_csb_update() 153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update() 156 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; in emulate_csb_update() 262 status.ldw = vgpu_vreg(vgpu, status_reg); in get_next_execlist_slot() 263 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot() [all …]
|
D | debugfs.c | 66 vreg = vgpu_vreg(param->vgpu, offset); in mmio_diff_handler()
|
D | display.c | 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe() 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
|
D | scheduler.c | 272 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state() 276 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state() 280 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
|
D | gvt.h | 453 #define vgpu_vreg(vgpu, offset) \ macro
|
D | cmd_parser.c | 950 vreg = &vgpu_vreg(s->vgpu, offset); in cmd_reg_handler() 1022 vgpu_vreg(vgpu, offset) = data; in cmd_reg_handler()
|