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Searched refs:mask2 (Results 1 – 25 of 28) sorted by relevance

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/drivers/soc/fsl/qe/
Dgpio.c249 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
256 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
257 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
258 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
259 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
261 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
262 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
263 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
264 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c310 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2() argument
314 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
320 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3() argument
325 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
332 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4() argument
338 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
346 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5() argument
353 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
362 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6() argument
370 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get6()
[all …]
/drivers/net/wireless/ath/ath9k/
Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
Dar9003_mac.c186 u32 mask2 = 0; in ar9003_hw_get_isr() local
216 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
218 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
220 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
222 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
224 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
226 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
228 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
230 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
302 *masked |= mask2; in ar9003_hw_get_isr()
Dmac.c911 u32 mask, mask2; in ath9k_hw_set_interrupts() local
928 mask2 = 0; in ath9k_hw_set_interrupts()
972 mask2 |= AR_IMR_S2_TIM; in ath9k_hw_set_interrupts()
974 mask2 |= AR_IMR_S2_DTIM; in ath9k_hw_set_interrupts()
976 mask2 |= AR_IMR_S2_DTIMSYNC; in ath9k_hw_set_interrupts()
978 mask2 |= AR_IMR_S2_CABEND; in ath9k_hw_set_interrupts()
980 mask2 |= AR_IMR_S2_TSFOOR; in ath9k_hw_set_interrupts()
986 mask2 |= AR_IMR_S2_GTT; in ath9k_hw_set_interrupts()
988 mask2 |= AR_IMR_S2_CST; in ath9k_hw_set_interrupts()
994 mask2 |= AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c216 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
226 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
228 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
230 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
240 reg2 ## __ ## mask2 ## _MASK,\
242 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
234 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
246 reg2 ## __ ## mask2 ## _MASK,\
248 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
223 reg2 ## __ ## mask2 ## _MASK,\
225 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
233 reg2 ## __ ## mask2 ## _MASK,\
235 reg2 ## __ ## mask2 ## _MASK \
/drivers/net/hamradio/
Dbaycom_par.c206 unsigned int data, mask, mask2, descx; in par96_rx() local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; in par96_rx()
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2) in par96_rx()
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; in par96_rx()
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) && in par96_rx()
Dhdlcdrv.c158 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
176 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
179 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
183 else if ((s->hdlcrx.bitstream & mask2) == mask3) { in hdlcdrv_receiver()
254 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
330 mask2 = 0x10000; in hdlcdrv_transmitter()
333 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
337 s->hdlctx.bitstream &= ~mask2; in hdlcdrv_transmitter()
/drivers/media/test-drivers/vidtv/
Dvidtv_pes.c89 u64 mask2; in vidtv_pes_write_pts_dts() local
96 mask2 = GENMASK_ULL(29, 15); in vidtv_pes_write_pts_dts()
102 pts_dts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
106 pts_dts.dts2 = cpu_to_be16(((args->dts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
114 pts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
/drivers/power/supply/
Drt9455_charger.c854 unsigned int irq1, mask1, mask2; in rt9455_irq_handler_check_irq1_register() local
896 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq1_register()
902 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq1_register()
911 if (mask2 & GET_MASK(F_CHRCHGIM)) { in rt9455_irq_handler_check_irq1_register()
948 unsigned int irq2, mask2; in rt9455_irq_handler_check_irq2_register() local
959 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq2_register()
989 if ((mask2 & GET_MASK(F_CHTERMIM)) == 0) { in rt9455_irq_handler_check_irq2_register()
1000 mask2 = mask2 | GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
1014 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq2_register()
1022 mask2 = mask2 & ~GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
117 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
118 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
119 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/mfd/
Dmenelaus.c163 u8 mask1, mask2; member
197 the_menelaus->mask2 &= ~(1 << irq); in menelaus_enable_irq()
199 the_menelaus->mask2); in menelaus_enable_irq()
211 the_menelaus->mask2 |= (1 << irq); in menelaus_disable_irq()
213 the_menelaus->mask2); in menelaus_disable_irq()
770 & ~menelaus->mask2) << 8; in menelaus_work()
1182 menelaus->mask2 = 0xff; in menelaus_probe()
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h396 uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
400 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
405 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
411 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
418 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
426 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
435 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
/drivers/acpi/
Dacpi_lpss.c940 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_enter_d3_state() local
969 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
972 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_enter_d3_state()
989 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_exit_d3_state() local
1002 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
1005 LPSS_IOSF_PMCSR, value2, mask2); in lpss_iosf_exit_d3_state()
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c1064 u32 isr1, isr2, mask1, mask2; in msm_edp_ctrl_irq() local
1073 mask2 = isr2 & EDP_INTR_MASK2; in msm_edp_ctrl_irq()
1076 isr2 &= ~mask2; in msm_edp_ctrl_irq()
1079 isr1, mask1, isr2, mask2); in msm_edp_ctrl_irq()
1088 ack |= mask2; in msm_edp_ctrl_irq()
/drivers/net/can/
Dpch_can.c126 u32 mask2; member
334 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); in pch_can_clear_if_buffers()
372 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, in pch_can_config_rx_tx_buffers()
395 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); in pch_can_config_rx_tx_buffers()
/drivers/net/ethernet/freescale/fman/
Dfman_memac.c494 u64 mask1, mask2; in get_mac_addr_hash_code() local
503 mask2 = eth_addr & (u64)0x01; in get_mac_addr_hash_code()
504 mask1 ^= mask2; in get_mac_addr_hash_code()
/drivers/tty/
Dnozomi.c1016 u16 read_iir, u16 mask1, u16 mask2) in handle_data_dl() argument
1024 if (read_iir & mask2) { in handle_data_dl()
1026 writew(mask2, dc->reg_fcr); in handle_data_dl()
1030 } else if (*toggle == 1 && read_iir & mask2) { in handle_data_dl()
1032 writew(mask2, dc->reg_fcr); in handle_data_dl()
/drivers/usb/host/
Dr8a66597-hcd.c1605 u16 mask0, mask1, mask2; in r8a66597_irq() local
1617 mask2 = intsts2 & intenb2; in r8a66597_irq()
1620 if (mask2) { in r8a66597_irq()
1621 if (mask2 & ATTCH) { in r8a66597_irq()
1628 if (mask2 & DTCH) { in r8a66597_irq()
1633 if (mask2 & BCHG) { in r8a66597_irq()

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