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Searched refs:regval (Results 1 – 16 of 16) sorted by relevance

/sound/x86/
Dintel_hdmi_lpe_audio.h124 u32 regval; member
148 u32 regval; member
167 u32 regval; member
182 u32 regval; member
192 u32 regval; member
204 u32 regval; member
223 u32 regval; member
236 u32 regval; member
248 u32 regval; member
265 u32 regval; member
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Dintel_hdmi_audio.c253 intelhaddata->aud_config.regval); in had_enable_audio()
284 union aud_ch_status_0 ch_stat0 = {.regval = 0}; in had_prog_status_reg()
285 union aud_ch_status_1 ch_stat1 = {.regval = 0}; in had_prog_status_reg()
322 AUD_CH_STATUS_0, ch_stat0.regval); in had_prog_status_reg()
339 AUD_CH_STATUS_1, ch_stat1.regval); in had_prog_status_reg()
351 union aud_cfg cfg_val = {.regval = 0}; in had_init_audio_ctrl()
352 union aud_buf_config buf_cfg = {.regval = 0}; in had_init_audio_ctrl()
360 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); in had_init_audio_ctrl()
383 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); in had_init_audio_ctrl()
593 union aud_ctrl_st ctrl_state = {.regval = 0}; in had_prog_dip()
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/sound/soc/codecs/
Dadau7118.c150 u32 regval; in adau7118_set_fmt() local
181 regval = ADAU7118_LRCLK_BCLK_POL(0); in adau7118_set_fmt()
184 regval = ADAU7118_LRCLK_BCLK_POL(2); in adau7118_set_fmt()
187 regval = ADAU7118_LRCLK_BCLK_POL(1); in adau7118_set_fmt()
190 regval = ADAU7118_LRCLK_BCLK_POL(3); in adau7118_set_fmt()
201 regval); in adau7118_set_fmt()
233 u32 regval; in adau7118_set_tdm_slot() local
239 regval = ADAU7118_SLOT_WIDTH(0); in adau7118_set_tdm_slot()
242 regval = ADAU7118_SLOT_WIDTH(2); in adau7118_set_tdm_slot()
245 regval = ADAU7118_SLOT_WIDTH(1); in adau7118_set_tdm_slot()
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Dmax98095.c947 u8 regval; in max98095_dai1_hw_params() local
966 if (rate_value(rate, &regval)) in max98095_dai1_hw_params()
970 M98095_CLKMODE_MASK, regval); in max98095_dai1_hw_params()
1008 u8 regval; in max98095_dai2_hw_params() local
1027 if (rate_value(rate, &regval)) in max98095_dai2_hw_params()
1031 M98095_CLKMODE_MASK, regval); in max98095_dai2_hw_params()
1069 u8 regval; in max98095_dai3_hw_params() local
1088 if (rate_value(rate, &regval)) in max98095_dai3_hw_params()
1092 M98095_CLKMODE_MASK, regval); in max98095_dai3_hw_params()
1164 u8 regval = 0; in max98095_dai1_set_fmt() local
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Dcpcap.c459 int regval, mask; in cpcap_input_right_mux_get_enum() local
462 err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval); in cpcap_input_right_mux_get_enum()
472 switch (regval & mask) { in cpcap_input_right_mux_get_enum()
502 int regval = 0, mask; in cpcap_input_right_mux_put_enum() local
513 regval = BIT(CPCAP_BIT_MIC1_MUX); in cpcap_input_right_mux_put_enum()
516 regval = BIT(CPCAP_BIT_HS_MIC_MUX); in cpcap_input_right_mux_put_enum()
519 regval = BIT(CPCAP_BIT_EMU_MIC_MUX); in cpcap_input_right_mux_put_enum()
522 regval = BIT(CPCAP_BIT_RX_R_ENCODE); in cpcap_input_right_mux_put_enum()
529 mask, regval); in cpcap_input_right_mux_put_enum()
543 int regval, mask; in cpcap_input_left_mux_get_enum() local
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Dmax98088.c971 u8 regval; in max98088_dai1_hw_params() local
992 if (rate_value(rate, &regval)) in max98088_dai1_hw_params()
996 M98088_CLKMODE_MASK, regval); in max98088_dai1_hw_params()
1041 u8 regval; in max98088_dai2_hw_params() local
1062 if (rate_value(rate, &regval)) in max98088_dai2_hw_params()
1066 M98088_CLKMODE_MASK, regval); in max98088_dai2_hw_params()
1631 u8 regval = 0; in max98088_handle_pdata() local
1640 regval |= M98088_DIGMIC_L; in max98088_handle_pdata()
1643 regval |= M98088_DIGMIC_R; in max98088_handle_pdata()
1645 max98088->digmic = (regval ? 1 : 0); in max98088_handle_pdata()
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Dmax98090.c1583 u8 regval; in max98090_dai_set_fmt() local
1591 regval = 0; in max98090_dai_set_fmt()
1607 regval |= M98090_MAS_MASK | in max98090_dai_set_fmt()
1611 regval |= M98090_MAS_MASK | in max98090_dai_set_fmt()
1615 regval |= M98090_MAS_MASK | in max98090_dai_set_fmt()
1626 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); in max98090_dai_set_fmt()
1628 regval = 0; in max98090_dai_set_fmt()
1631 regval |= M98090_DLY_MASK; in max98090_dai_set_fmt()
1636 regval |= M98090_RJ_MASK; in max98090_dai_set_fmt()
1649 regval |= M98090_WCI_MASK; in max98090_dai_set_fmt()
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Dinno_rk3036.c51 int val, regval; in rk3036_codec_antipop_get() local
53 regval = snd_soc_component_read(component, INNO_R09); in rk3036_codec_antipop_get()
54 val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) & in rk3036_codec_antipop_get()
58 val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) & in rk3036_codec_antipop_get()
Dcs42l42.c923 unsigned int regval; in cs42l42_mute_stream() local
973 regval, in cs42l42_mute_stream()
974 (regval & 1), in cs42l42_mute_stream()
/sound/sh/
Daica.c129 u32 regval; in spu_disable() local
131 regval = readl(ARM_RESET_REGISTER); in spu_disable()
132 regval |= 1; in spu_disable()
135 writel(regval, ARM_RESET_REGISTER); in spu_disable()
139 regval = readl(SPU_REGISTER_BASE + (i * 0x80)); in spu_disable()
140 regval = (regval & ~0x4000) | 0x8000; in spu_disable()
143 writel(regval, SPU_REGISTER_BASE + (i * 0x80)); in spu_disable()
152 u32 regval = readl(ARM_RESET_REGISTER); in spu_enable() local
153 regval &= ~1; in spu_enable()
156 writel(regval, ARM_RESET_REGISTER); in spu_enable()
/sound/soc/qcom/
Dlpass-platform.c197 unsigned int regval; in lpass_platform_pcmops_hw_params() local
279 regval = LPAIF_DMACTL_WPSCNT_ONE; in lpass_platform_pcmops_hw_params()
282 regval = LPAIF_DMACTL_WPSCNT_TWO; in lpass_platform_pcmops_hw_params()
285 regval = LPAIF_DMACTL_WPSCNT_THREE; in lpass_platform_pcmops_hw_params()
288 regval = LPAIF_DMACTL_WPSCNT_FOUR; in lpass_platform_pcmops_hw_params()
300 regval = LPAIF_DMACTL_WPSCNT_ONE; in lpass_platform_pcmops_hw_params()
303 regval = (dai_id == LPASS_DP_RX ? in lpass_platform_pcmops_hw_params()
308 regval = (dai_id == LPASS_DP_RX ? in lpass_platform_pcmops_hw_params()
313 regval = (dai_id == LPASS_DP_RX ? in lpass_platform_pcmops_hw_params()
318 regval = (dai_id == LPASS_DP_RX ? in lpass_platform_pcmops_hw_params()
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Dlpass-cpu.c142 unsigned int regval; in lpass_cpu_daiops_hw_params() local
167 regval = LPAIF_I2SCTL_BITWIDTH_16; in lpass_cpu_daiops_hw_params()
170 regval = LPAIF_I2SCTL_BITWIDTH_24; in lpass_cpu_daiops_hw_params()
173 regval = LPAIF_I2SCTL_BITWIDTH_32; in lpass_cpu_daiops_hw_params()
180 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); in lpass_cpu_daiops_hw_params()
/sound/soc/bcm/
Dcygnus-pcm.c405 u32 regval; in cygnus_pcm_period_elapsed() local
419 regval = readl(aio->cygaud->audio + p_rbuf->rdaddr); in cygnus_pcm_period_elapsed()
420 regval = regval ^ BIT(31); in cygnus_pcm_period_elapsed()
421 writel(regval, aio->cygaud->audio + p_rbuf->wraddr); in cygnus_pcm_period_elapsed()
424 regval = readl(aio->cygaud->audio + p_rbuf->wraddr); in cygnus_pcm_period_elapsed()
425 writel(regval, aio->cygaud->audio + p_rbuf->rdaddr); in cygnus_pcm_period_elapsed()
/sound/soc/
Dsoc-ops.c878 unsigned int regval = snd_soc_component_read(component, regbase+i); in snd_soc_get_xr_sx() local
879 val |= (regval & regwmask) << (regwshift*(regcount-i-1)); in snd_soc_get_xr_sx()
928 unsigned int regval = (val >> (regwshift*(regcount-i-1))) & regwmask; in snd_soc_put_xr_sx() local
931 regmask, regval); in snd_soc_put_xr_sx()
/sound/soc/fsl/
Dfsl_easrc.c54 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_iec958_put_bits() local
56 easrc_priv->bps_iec958[mc->regbase] = regval; in fsl_easrc_iec958_put_bits()
81 unsigned int regval; in fsl_easrc_get_reg() local
83 regval = snd_soc_component_read(component, mc->regbase); in fsl_easrc_get_reg()
85 ucontrol->value.integer.value[0] = regval; in fsl_easrc_get_reg()
96 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_set_reg() local
99 ret = snd_soc_component_write(component, mc->regbase, regval); in fsl_easrc_set_reg()
/sound/isa/opti9xx/
Dmiro.c1205 unsigned char regval; in snd_card_miro_aci_detect() local
1215 regval=inb(miro->mc_base + 4); in snd_card_miro_aci_detect()
1216 aci->aci_port = (regval & 0x10) ? 0x344 : 0x354; in snd_card_miro_aci_detect()