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1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    items:
18      - const: qcom,mdss-dsi-ctrl
19
20  reg:
21    maxItems: 1
22
23  reg-names:
24    const: dsi_ctrl
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    items:
31      - description: Display byte clock
32      - description: Display byte interface clock
33      - description: Display pixel clock
34      - description: Display core clock
35      - description: Display AHB clock
36      - description: Display AXI clock
37
38  clock-names:
39    items:
40      - const: byte
41      - const: byte_intf
42      - const: pixel
43      - const: core
44      - const: iface
45      - const: bus
46
47  phys:
48    maxItems: 1
49
50  phy-names:
51    const: dsi
52
53  "#address-cells": true
54
55  "#size-cells": true
56
57  syscon-sfpb:
58    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
59    $ref: "/schemas/types.yaml#/definitions/phandle"
60
61  qcom,dual-dsi-mode:
62    type: boolean
63    description: |
64      Indicates if the DSI controller is driving a panel which needs
65      2 DSI links.
66
67  qcom,master-dsi:
68    type: boolean
69    description: |
70      Indicates if the DSI controller is the master DSI controller when
71      qcom,dual-dsi-mode enabled.
72
73  qcom,sync-dual-dsi:
74    type: boolean
75    description: |
76      Indicates if the DSI controller needs to sync the other DSI controller
77      with MIPI DCS commands when qcom,dual-dsi-mode enabled.
78
79  assigned-clocks:
80    minItems: 2
81    maxItems: 2
82    description: |
83      Parents of "byte" and "pixel" for the given platform.
84
85  assigned-clock-parents:
86    minItems: 2
87    maxItems: 2
88    description: |
89      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
90
91  power-domains:
92    maxItems: 1
93
94  operating-points-v2: true
95
96  ports:
97    $ref: "/schemas/graph.yaml#/properties/ports"
98    description: |
99      Contains DSI controller input and output ports as children, each
100      containing one endpoint subnode.
101
102    properties:
103      port@0:
104        $ref: "/schemas/graph.yaml#/$defs/port-base"
105        unevaluatedProperties: false
106        description: |
107          Input endpoints of the controller.
108        properties:
109          endpoint:
110            $ref: /schemas/media/video-interfaces.yaml#
111            unevaluatedProperties: false
112            properties:
113              data-lanes:
114                maxItems: 4
115                minItems: 4
116                items:
117                  enum: [ 0, 1, 2, 3 ]
118
119      port@1:
120        $ref: "/schemas/graph.yaml#/$defs/port-base"
121        unevaluatedProperties: false
122        description: |
123          Output endpoints of the controller.
124        properties:
125          endpoint:
126            $ref: /schemas/media/video-interfaces.yaml#
127            unevaluatedProperties: false
128            properties:
129              data-lanes:
130                maxItems: 4
131                minItems: 4
132                items:
133                  enum: [ 0, 1, 2, 3 ]
134
135    required:
136      - port@0
137      - port@1
138
139required:
140  - compatible
141  - reg
142  - reg-names
143  - interrupts
144  - clocks
145  - clock-names
146  - phys
147  - phy-names
148  - assigned-clocks
149  - assigned-clock-parents
150  - ports
151
152additionalProperties: false
153
154examples:
155  - |
156     #include <dt-bindings/interrupt-controller/arm-gic.h>
157     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
158     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
159     #include <dt-bindings/power/qcom-rpmpd.h>
160
161     dsi@ae94000 {
162           compatible = "qcom,mdss-dsi-ctrl";
163           reg = <0x0ae94000 0x400>;
164           reg-names = "dsi_ctrl";
165
166           #address-cells = <1>;
167           #size-cells = <0>;
168
169           interrupt-parent = <&mdss>;
170           interrupts = <4>;
171
172           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
173                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
174                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
175                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
176                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
177                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
178           clock-names = "byte",
179                         "byte_intf",
180                         "pixel",
181                         "core",
182                         "iface",
183                         "bus";
184
185           phys = <&dsi0_phy>;
186           phy-names = "dsi";
187
188           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
189           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
190
191           power-domains = <&rpmhpd SC7180_CX>;
192           operating-points-v2 = <&dsi_opp_table>;
193
194           ports {
195                  #address-cells = <1>;
196                  #size-cells = <0>;
197
198                  port@0 {
199                          reg = <0>;
200                          dsi0_in: endpoint {
201                                   remote-endpoint = <&dpu_intf1_out>;
202                          };
203                  };
204
205                  port@1 {
206                          reg = <1>;
207                          dsi0_out: endpoint {
208                                   remote-endpoint = <&sn65dsi86_in>;
209                                   data-lanes = <0 1 2 3>;
210                          };
211                  };
212           };
213     };
214...
215