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1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 10nm PHY
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-10nm
19      - qcom,dsi-phy-10nm-8998
20
21  reg:
22    items:
23      - description: dsi phy register set
24      - description: dsi phy lane register set
25      - description: dsi pll register set
26
27  reg-names:
28    items:
29      - const: dsi_phy
30      - const: dsi_phy_lane
31      - const: dsi_pll
32
33  vdds-supply:
34    description: |
35      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
36      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
37
38required:
39  - compatible
40  - reg
41  - reg-names
42
43unevaluatedProperties: false
44
45examples:
46  - |
47     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
48     #include <dt-bindings/clock/qcom,rpmh.h>
49
50     dsi-phy@ae94400 {
51         compatible = "qcom,dsi-phy-10nm";
52         reg = <0x0ae94400 0x200>,
53               <0x0ae94600 0x280>,
54               <0x0ae94a00 0x1e0>;
55         reg-names = "dsi_phy",
56                     "dsi_phy_lane",
57                     "dsi_pll";
58
59         #clock-cells = <1>;
60         #phy-cells = <0>;
61
62         vdds-supply = <&vdda_mipi_dsi0_pll>;
63         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
64                  <&rpmhcc RPMH_CXO_CLK>;
65         clock-names = "iface", "ref";
66     };
67...
68