1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI 14nm PHY 8 9maintainers: 10 - Krishna Manikandan <mkrishn@codeaurora.org> 11 12allOf: 13 - $ref: dsi-phy-common.yaml# 14 15properties: 16 compatible: 17 enum: 18 - qcom,dsi-phy-14nm 19 - qcom,dsi-phy-14nm-660 20 21 reg: 22 items: 23 - description: dsi phy register set 24 - description: dsi phy lane register set 25 - description: dsi pll register set 26 27 reg-names: 28 items: 29 - const: dsi_phy 30 - const: dsi_phy_lane 31 - const: dsi_pll 32 33 vcca-supply: 34 description: Phandle to vcca regulator device node. 35 36required: 37 - compatible 38 - reg 39 - reg-names 40 41unevaluatedProperties: false 42 43examples: 44 - | 45 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 46 #include <dt-bindings/clock/qcom,rpmh.h> 47 48 dsi-phy@ae94400 { 49 compatible = "qcom,dsi-phy-14nm"; 50 reg = <0x0ae94400 0x200>, 51 <0x0ae94600 0x280>, 52 <0x0ae94a00 0x1e0>; 53 reg-names = "dsi_phy", 54 "dsi_phy_lane", 55 "dsi_pll"; 56 57 #clock-cells = <1>; 58 #phy-cells = <0>; 59 60 vcca-supply = <&vcca_reg>; 61 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 62 <&rpmhcc RPMH_CXO_CLK>; 63 clock-names = "iface", "ref"; 64 }; 65... 66