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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx6q-pcie
21      - fsl,imx6sx-pcie
22      - fsl,imx6qp-pcie
23      - fsl,imx7d-pcie
24      - fsl,imx8mq-pcie
25
26  reg:
27    items:
28      - description: Data Bus Interface (DBI) registers.
29      - description: PCIe configuration space region.
30
31  reg-names:
32    items:
33      - const: dbi
34      - const: config
35
36  interrupts:
37    items:
38      - description: builtin MSI controller.
39
40  interrupt-names:
41    items:
42      - const: msi
43
44  clocks:
45    minItems: 3
46    items:
47      - description: PCIe bridge clock.
48      - description: PCIe bus clock.
49      - description: PCIe PHY clock.
50      - description: Additional required clock entry for imx6sx-pcie,
51          imx8mq-pcie.
52
53  clock-names:
54    minItems: 3
55    items:
56      - const: pcie
57      - const: pcie_bus
58      - const: pcie_phy
59      - enum: [ pcie_inbound_axi, pcie_aux ]
60
61  num-lanes:
62    const: 1
63
64  fsl,imx7d-pcie-phy:
65    $ref: /schemas/types.yaml#/definitions/phandle
66    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
67      required properties for imx7d-pcie and imx8mq-pcie.
68
69  power-domains:
70    items:
71      - description: The phandle pointing to the DISPLAY domain for
72          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
73          imx8mq-pcie.
74      - description: The phandle pointing to the PCIE_PHY power domains
75          for imx6sx-pcie.
76
77  power-domain-names:
78    items:
79      - const: pcie
80      - const: pcie_phy
81
82  resets:
83    maxItems: 3
84    description: Phandles to PCIe-related reset lines exposed by SRC
85      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
86
87  reset-names:
88    items:
89      - const: pciephy
90      - const: apps
91      - const: turnoff
92
93  fsl,tx-deemph-gen1:
94    description: Gen1 De-emphasis value (optional required).
95    $ref: /schemas/types.yaml#/definitions/uint32
96    default: 0
97
98  fsl,tx-deemph-gen2-3p5db:
99    description: Gen2 (3.5db) De-emphasis value (optional required).
100    $ref: /schemas/types.yaml#/definitions/uint32
101    default: 0
102
103  fsl,tx-deemph-gen2-6db:
104    description: Gen2 (6db) De-emphasis value (optional required).
105    $ref: /schemas/types.yaml#/definitions/uint32
106    default: 20
107
108  fsl,tx-swing-full:
109    description: Gen2 TX SWING FULL value (optional required).
110    $ref: /schemas/types.yaml#/definitions/uint32
111    default: 127
112
113  fsl,tx-swing-low:
114    description: TX launch amplitude swing_low value (optional required).
115    $ref: /schemas/types.yaml#/definitions/uint32
116    default: 127
117
118  fsl,max-link-speed:
119    description: Specify PCI Gen for link capability (optional required).
120      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
121      requirements and thus for gen2 capability a gen2 compliant clock
122      generator should be used and configured.
123    $ref: /schemas/types.yaml#/definitions/uint32
124    enum: [1, 2, 3, 4]
125    default: 1
126
127  reset-gpio:
128    description: Should specify the GPIO for controlling the PCI bus device
129      reset signal. It's not polarity aware and defaults to active-low reset
130      sequence (L=reset state, H=operation state) (optional required).
131
132  reset-gpio-active-high:
133    description: If present then the reset sequence using the GPIO
134      specified in the "reset-gpio" property is reversed (H=reset state,
135      L=operation state) (optional required).
136
137  vpcie-supply:
138    description: Should specify the regulator in charge of PCIe port power.
139      The regulator will be enabled when initializing the PCIe host and
140      disabled either as part of the init process or when shutting down
141      the host (optional required).
142
143  vph-supply:
144    description: Should specify the regulator in charge of VPH one of
145      the three PCIe PHY powers. This regulator can be supplied by both
146      1.8v and 3.3v voltage supplies (optional required).
147
148required:
149  - compatible
150  - reg
151  - reg-names
152  - "#address-cells"
153  - "#size-cells"
154  - device_type
155  - bus-range
156  - ranges
157  - num-lanes
158  - interrupts
159  - interrupt-names
160  - "#interrupt-cells"
161  - interrupt-map-mask
162  - interrupt-map
163  - clocks
164  - clock-names
165
166allOf:
167  - $ref: /schemas/pci/snps,dw-pcie.yaml#
168  - if:
169      properties:
170        compatible:
171          contains:
172            const: fsl,imx6sx-pcie
173    then:
174      properties:
175        clock-names:
176          items:
177            - {}
178            - {}
179            - {}
180            - const: pcie_inbound_axi
181  - if:
182      properties:
183        compatible:
184          contains:
185            const: fsl,imx8mq-pcie
186    then:
187      properties:
188        clock-names:
189          items:
190            - {}
191            - {}
192            - {}
193            - const: pcie_aux
194  - if:
195      properties:
196        compatible:
197          not:
198            contains:
199              enum:
200                - fsl,imx6sx-pcie
201                - fsl,imx8mq-pcie
202    then:
203      properties:
204        clock-names:
205          maxItems: 3
206
207unevaluatedProperties: false
208
209examples:
210  - |
211    #include <dt-bindings/clock/imx6qdl-clock.h>
212    #include <dt-bindings/interrupt-controller/arm-gic.h>
213
214    pcie: pcie@1ffc000 {
215        compatible = "fsl,imx6q-pcie";
216        reg = <0x01ffc000 0x04000>,
217              <0x01f00000 0x80000>;
218        reg-names = "dbi", "config";
219        #address-cells = <3>;
220        #size-cells = <2>;
221        device_type = "pci";
222        bus-range = <0x00 0xff>;
223        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
224                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
225        num-lanes = <1>;
226        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
227        interrupt-names = "msi";
228        #interrupt-cells = <1>;
229        interrupt-map-mask = <0 0 0 0x7>;
230        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
231                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
232                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
233                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
234        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
235                <&clks IMX6QDL_CLK_LVDS1_GATE>,
236                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
237        clock-names = "pcie", "pcie_bus", "pcie_phy";
238    };
239...
240