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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT6797 Pin Controller Device Tree Bindings
8
9maintainers:
10  - Sean Wang <sean.wang@kernel.org>
11
12description: |+
13  The MediaTek's MT6797 Pin controller is used to control SoC pins.
14
15properties:
16  compatible:
17    const: mediatek,mt6797-pinctrl
18
19  reg:
20    minItems: 5
21    maxItems: 5
22
23  reg-names:
24    items:
25      - const: gpio
26      - const: iocfgl
27      - const: iocfgb
28      - const: iocfgr
29      - const: iocfgt
30
31  gpio-controller: true
32
33  "#gpio-cells":
34    const: 2
35    description: |
36      Number of cells in GPIO specifier. Since the generic GPIO
37      binding is used, the amount of cells must be specified as 2. See the below
38      mentioned gpio binding representation for description of particular cells.
39
40  interrupt-controller: true
41
42  interrupts:
43    maxItems: 1
44
45  "#interrupt-cells":
46    const: 2
47
48required:
49  - compatible
50  - reg
51  - reg-names
52  - gpio-controller
53  - "#gpio-cells"
54
55patternProperties:
56  '-[0-9]+$':
57    type: object
58    additionalProperties: false
59    patternProperties:
60      'pins':
61        type: object
62        additionalProperties: false
63        description: |
64          A pinctrl node should contain at least one subnodes representing the
65          pinctrl groups available on the machine. Each subnode will list the
66          pins it needs, and how they should be configured, with regard to muxer
67          configuration, pullups, drive strength, input enable/disable and input
68          schmitt.
69        $ref: "/schemas/pinctrl/pincfg-node.yaml"
70
71        properties:
72          pinmux:
73            description:
74              integer array, represents gpio pin number and mux setting.
75              Supported pin number and mux varies for different SoCs, and are
76              defined as macros in <soc>-pinfunc.h directly.
77
78          bias-disable: true
79
80          bias-pull-up: true
81
82          bias-pull-down: true
83
84          input-enable: true
85
86          input-disable: true
87
88          output-enable: true
89
90          output-low: true
91
92          output-high: true
93
94          input-schmitt-enable: true
95
96          input-schmitt-disable: true
97
98          drive-strength:
99            enum: [2, 4, 8, 12, 16]
100
101          slew-rate:
102            enum: [0, 1]
103
104          mediatek,pull-up-adv:
105            description: |
106              Pull up setings for 2 pull resistors, R0 and R1. User can
107              configure those special pins. Valid arguments are described as below:
108              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
109              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
110              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
111              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
112            $ref: /schemas/types.yaml#/definitions/uint32
113            enum: [0, 1, 2, 3]
114
115          mediatek,pull-down-adv:
116            description: |
117              Pull down settings for 2 pull resistors, R0 and R1. User can
118              configure those special pins. Valid arguments are described as below:
119              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
120              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
121              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
122              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
123            $ref: /schemas/types.yaml#/definitions/uint32
124            enum: [0, 1, 2, 3]
125
126          mediatek,tdsel:
127            description: |
128              An integer describing the steps for output level shifter duty
129              cycle when asserted (high pulse width adjustment). Valid arguments
130              are from 0 to 15.
131            $ref: /schemas/types.yaml#/definitions/uint32
132
133          mediatek,rdsel:
134            description: |
135              An integer describing the steps for input level shifter duty cycle
136              when asserted (high pulse width adjustment). Valid arguments are
137              from 0 to 63.
138            $ref: /schemas/types.yaml#/definitions/uint32
139
140        required:
141          - pinmux
142
143additionalProperties: false
144
145examples:
146  - |
147    #include <dt-bindings/interrupt-controller/irq.h>
148    #include <dt-bindings/interrupt-controller/arm-gic.h>
149    #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
150
151    soc {
152        #address-cells = <2>;
153        #size-cells = <2>;
154
155        pio: pinctrl@10005000 {
156            compatible = "mediatek,mt6797-pinctrl";
157            reg = <0 0x10005000 0 0x1000>,
158                  <0 0x10002000 0 0x400>,
159                  <0 0x10002400 0 0x400>,
160                  <0 0x10002800 0 0x400>,
161                  <0 0x10002C00 0 0x400>;
162            reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
163            gpio-controller;
164            #gpio-cells = <2>;
165
166            uart_pins_a: uart-0 {
167                pins1 {
168                    pinmux = <MT6797_GPIO232__FUNC_URXD1>,
169                            <MT6797_GPIO233__FUNC_UTXD1>;
170                };
171            };
172        };
173    };
174