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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT8195 Pin Controller
8
9maintainers:
10  - Sean Wang <sean.wang@mediatek.com>
11
12description: |
13  The Mediatek's Pin controller is used to control SoC pins.
14
15properties:
16  compatible:
17    const: mediatek,mt8195-pinctrl
18
19  gpio-controller: true
20
21  '#gpio-cells':
22    description: |
23      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
24      the amount of cells must be specified as 2. See the below
25      mentioned gpio binding representation for description of particular cells.
26    const: 2
27
28  gpio-ranges:
29    description: gpio valid number range.
30    maxItems: 1
31
32  reg:
33    description: |
34      Physical address base for gpio base registers. There are 8 GPIO
35      physical address base in mt8195.
36    maxItems: 8
37
38  reg-names:
39    description: |
40      Gpio base register names.
41    maxItems: 8
42
43  interrupt-controller: true
44
45  '#interrupt-cells':
46    const: 2
47
48  interrupts:
49    description: The interrupt outputs to sysirq.
50    maxItems: 1
51
52#PIN CONFIGURATION NODES
53patternProperties:
54  '-pins$':
55    type: object
56    description: |
57      A pinctrl node should contain at least one subnodes representing the
58      pinctrl groups available on the machine. Each subnode will list the
59      pins it needs, and how they should be configured, with regard to muxer
60      configuration, pullups, drive strength, input enable/disable and
61      input schmitt.
62      An example of using macro:
63      pincontroller {
64        /* GPIO0 set as multifunction GPIO0 */
65        gpio_pin {
66          pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
67        };
68        /* GPIO8 set as multifunction SDA0 */
69        i2c0_pin {
70          pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
71        };
72      };
73    $ref: "pinmux-node.yaml"
74
75    properties:
76      pinmux:
77        description: |
78          Integer array, represents gpio pin number and mux setting.
79          Supported pin number and mux varies for different SoCs, and are defined
80          as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
81
82      drive-strength:
83        enum: [2, 4, 6, 8, 10, 12, 14, 16]
84
85      bias-pull-down: true
86
87      bias-pull-up: true
88
89      bias-disable: true
90
91      output-high: true
92
93      output-low: true
94
95      input-enable: true
96
97      input-disable: true
98
99      input-schmitt-enable: true
100
101      input-schmitt-disable: true
102
103    required:
104      - pinmux
105
106    additionalProperties: false
107
108required:
109  - compatible
110  - reg
111  - interrupts
112  - interrupt-controller
113  - '#interrupt-cells'
114  - gpio-controller
115  - '#gpio-cells'
116  - gpio-ranges
117
118additionalProperties: false
119
120examples:
121  - |
122            #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
123            #include <dt-bindings/interrupt-controller/arm-gic.h>
124            pio: pinctrl@10005000 {
125                    compatible = "mediatek,mt8195-pinctrl";
126                    reg = <0x10005000 0x1000>,
127                          <0x11d10000 0x1000>,
128                          <0x11d30000 0x1000>,
129                          <0x11d40000 0x1000>,
130                          <0x11e20000 0x1000>,
131                          <0x11eb0000 0x1000>,
132                          <0x11f40000 0x1000>,
133                          <0x1000b000 0x1000>;
134                    reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
135                          "iocfg_br", "iocfg_lm", "iocfg_rb",
136                          "iocfg_tl", "eint";
137                    gpio-controller;
138                    #gpio-cells = <2>;
139                    gpio-ranges = <&pio 0 0 144>;
140                    interrupt-controller;
141                    interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
142                    #interrupt-cells = <2>;
143
144                    pio-pins {
145                      pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
146                      output-low;
147                    };
148            };
149