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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MDM9607 TLMM block
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@somainline.org>
11
12description: |
13  This binding describes the Top Level Mode Multiplexer block found in the
14  MDM9607 platform.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,mdm9607-tlmm
22
23  reg:
24    maxItems: 1
25
26  interrupts: true
27  interrupt-controller: true
28  '#interrupt-cells': true
29  gpio-controller: true
30  gpio-reserved-ranges: true
31  '#gpio-cells': true
32  gpio-ranges: true
33  wakeup-parent: true
34
35required:
36  - compatible
37  - reg
38
39additionalProperties: false
40
41patternProperties:
42  '-state$':
43    oneOf:
44      - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
45      - patternProperties:
46          ".*":
47            $ref: "#/$defs/qcom-mdm9607-tlmm-state"
48
49'$defs':
50  qcom-mdm9607-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
56
57    properties:
58      pins:
59        description:
60          List of gpio pins affected by the properties specified in this
61          subnode.
62        items:
63          oneOf:
64            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
65            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
66                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
67                      qdsd_data3 ]
68        minItems: 1
69        maxItems: 16
70
71      function:
72        description:
73          Specify the alternative function to be configured for the specified
74          pins.
75
76        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
77                atest_char1, atest_char2, atest_char3,
78                atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
79                atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
80                bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
81                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
82                blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
83                blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
84                blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
85                codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
86                cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
87                ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
88                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
89                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
90                gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
91                nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
92                nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
93                pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
94                pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
95                ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
96                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
97                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
98                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
99                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
100                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
101                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
102                rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
103                sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
104                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
105                uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
106
107      bias-disable: true
108      bias-pull-down: true
109      bias-pull-up: true
110      drive-strength: true
111      input-enable: true
112      output-high: true
113      output-low: true
114
115    required:
116      - pins
117      - function
118
119    additionalProperties: false
120
121examples:
122  - |
123        #include <dt-bindings/interrupt-controller/arm-gic.h>
124        tlmm: pinctrl@1000000 {
125          compatible = "qcom,mdm9607-tlmm";
126          reg = <0x01000000 0x300000>;
127          interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
128          gpio-controller;
129          gpio-ranges = <&msmgpio 0 0 80>;
130          #gpio-cells = <2>;
131          interrupt-controller;
132          #interrupt-cells = <2>;
133        };
134