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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive L2 Cache Controller
9
10maintainers:
11  - Sagar Kadam <sagar.kadam@sifive.com>
12  - Yash Shah <yash.shah@sifive.com>
13  - Paul Walmsley  <paul.walmsley@sifive.com>
14
15description:
16  The SiFive Level 2 Cache Controller is used to provide access to fast copies
17  of memory for masters in a Core Complex. The Level 2 Cache Controller also
18  acts as directory-based coherency manager.
19  All the properties in ePAPR/DeviceTree specification applies for this platform.
20
21allOf:
22  - $ref: /schemas/cache-controller.yaml#
23
24select:
25  properties:
26    compatible:
27      contains:
28        enum:
29          - sifive,fu540-c000-ccache
30          - sifive,fu740-c000-ccache
31
32  required:
33    - compatible
34
35properties:
36  compatible:
37    items:
38      - enum:
39          - sifive,fu540-c000-ccache
40          - sifive,fu740-c000-ccache
41      - const: cache
42
43  cache-block-size:
44    const: 64
45
46  cache-level:
47    const: 2
48
49  cache-sets:
50    enum: [1024, 2048]
51
52  cache-size:
53    const: 2097152
54
55  cache-unified: true
56
57  interrupts:
58    minItems: 3
59    items:
60      - description: DirError interrupt
61      - description: DataError interrupt
62      - description: DataFail interrupt
63      - description: DirFail interrupt
64
65  reg:
66    maxItems: 1
67
68  next-level-cache: true
69
70  memory-region:
71    maxItems: 1
72    description: |
73      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
74      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
75
76if:
77  properties:
78    compatible:
79      contains:
80        const: sifive,fu540-c000-ccache
81
82then:
83  properties:
84    interrupts:
85      description: |
86        Must contain entries for DirError, DataError and DataFail signals.
87      maxItems: 3
88    cache-sets:
89      const: 1024
90
91else:
92  properties:
93    interrupts:
94      description: |
95        Must contain entries for DirError, DataError, DataFail, DirFail signals.
96      minItems: 4
97    cache-sets:
98      const: 2048
99
100additionalProperties: false
101
102required:
103  - compatible
104  - cache-block-size
105  - cache-level
106  - cache-sets
107  - cache-size
108  - cache-unified
109  - interrupts
110  - reg
111
112examples:
113  - |
114    cache-controller@2010000 {
115        compatible = "sifive,fu540-c000-ccache", "cache";
116        cache-block-size = <64>;
117        cache-level = <2>;
118        cache-sets = <1024>;
119        cache-size = <2097152>;
120        cache-unified;
121        reg = <0x2010000 0x1000>;
122        interrupt-parent = <&plic0>;
123        interrupts = <1>,
124                     <2>,
125                     <3>;
126        next-level-cache = <&L25>;
127        memory-region = <&l2_lim>;
128    };
129