1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 operating-points = < 27 /* kHz uV */ 28 1416000 1300000 29 1200000 1175000 30 1008000 1125000 31 816000 1125000 32 600000 1100000 33 504000 1100000 34 312000 1075000 35 >; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 }; 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 next-level-cache = <&L2>; 43 reg = <0x1>; 44 }; 45 }; 46 47 display-subsystem { 48 compatible = "rockchip,display-subsystem"; 49 ports = <&vop0_out>, <&vop1_out>; 50 }; 51 52 sram: sram@10080000 { 53 compatible = "mmio-sram"; 54 reg = <0x10080000 0x10000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0 0x10080000 0x10000>; 58 59 smp-sram@0 { 60 compatible = "rockchip,rk3066-smp-sram"; 61 reg = <0x0 0x50>; 62 }; 63 }; 64 65 vop0: vop@1010c000 { 66 compatible = "rockchip,rk3066-vop"; 67 reg = <0x1010c000 0x19c>; 68 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&cru ACLK_LCDC0>, 70 <&cru DCLK_LCDC0>, 71 <&cru HCLK_LCDC0>; 72 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 73 power-domains = <&power RK3066_PD_VIO>; 74 resets = <&cru SRST_LCDC0_AXI>, 75 <&cru SRST_LCDC0_AHB>, 76 <&cru SRST_LCDC0_DCLK>; 77 reset-names = "axi", "ahb", "dclk"; 78 status = "disabled"; 79 80 vop0_out: port { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 vop0_out_hdmi: endpoint@0 { 85 reg = <0>; 86 remote-endpoint = <&hdmi_in_vop0>; 87 }; 88 }; 89 }; 90 91 vop1: vop@1010e000 { 92 compatible = "rockchip,rk3066-vop"; 93 reg = <0x1010e000 0x19c>; 94 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&cru ACLK_LCDC1>, 96 <&cru DCLK_LCDC1>, 97 <&cru HCLK_LCDC1>; 98 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 99 power-domains = <&power RK3066_PD_VIO>; 100 resets = <&cru SRST_LCDC1_AXI>, 101 <&cru SRST_LCDC1_AHB>, 102 <&cru SRST_LCDC1_DCLK>; 103 reset-names = "axi", "ahb", "dclk"; 104 status = "disabled"; 105 106 vop1_out: port { 107 #address-cells = <1>; 108 #size-cells = <0>; 109 110 vop1_out_hdmi: endpoint@0 { 111 reg = <0>; 112 remote-endpoint = <&hdmi_in_vop1>; 113 }; 114 }; 115 }; 116 117 hdmi: hdmi@10116000 { 118 compatible = "rockchip,rk3066-hdmi"; 119 reg = <0x10116000 0x2000>; 120 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&cru HCLK_HDMI>; 122 clock-names = "hclk"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 125 power-domains = <&power RK3066_PD_VIO>; 126 rockchip,grf = <&grf>; 127 status = "disabled"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 hdmi_in: port@0 { 134 reg = <0>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 hdmi_in_vop0: endpoint@0 { 139 reg = <0>; 140 remote-endpoint = <&vop0_out_hdmi>; 141 }; 142 143 hdmi_in_vop1: endpoint@1 { 144 reg = <1>; 145 remote-endpoint = <&vop1_out_hdmi>; 146 }; 147 }; 148 149 hdmi_out: port@1 { 150 reg = <1>; 151 }; 152 }; 153 }; 154 155 i2s0: i2s@10118000 { 156 compatible = "rockchip,rk3066-i2s"; 157 reg = <0x10118000 0x2000>; 158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&i2s0_bus>; 161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 162 clock-names = "i2s_clk", "i2s_hclk"; 163 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 164 dma-names = "tx", "rx"; 165 rockchip,playback-channels = <8>; 166 rockchip,capture-channels = <2>; 167 #sound-dai-cells = <0>; 168 status = "disabled"; 169 }; 170 171 i2s1: i2s@1011a000 { 172 compatible = "rockchip,rk3066-i2s"; 173 reg = <0x1011a000 0x2000>; 174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&i2s1_bus>; 177 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 178 clock-names = "i2s_clk", "i2s_hclk"; 179 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 180 dma-names = "tx", "rx"; 181 rockchip,playback-channels = <2>; 182 rockchip,capture-channels = <2>; 183 #sound-dai-cells = <0>; 184 status = "disabled"; 185 }; 186 187 i2s2: i2s@1011c000 { 188 compatible = "rockchip,rk3066-i2s"; 189 reg = <0x1011c000 0x2000>; 190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&i2s2_bus>; 193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 194 clock-names = "i2s_clk", "i2s_hclk"; 195 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 196 dma-names = "tx", "rx"; 197 rockchip,playback-channels = <2>; 198 rockchip,capture-channels = <2>; 199 #sound-dai-cells = <0>; 200 status = "disabled"; 201 }; 202 203 cru: clock-controller@20000000 { 204 compatible = "rockchip,rk3066a-cru"; 205 reg = <0x20000000 0x1000>; 206 rockchip,grf = <&grf>; 207 208 #clock-cells = <1>; 209 #reset-cells = <1>; 210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 211 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 212 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 213 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 214 assigned-clock-rates = <400000000>, <594000000>, 215 <300000000>, <150000000>, 216 <75000000>, <300000000>, 217 <150000000>, <75000000>; 218 }; 219 220 timer2: timer@2000e000 { 221 compatible = "snps,dw-apb-timer"; 222 reg = <0x2000e000 0x100>; 223 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 225 clock-names = "timer", "pclk"; 226 }; 227 228 efuse: efuse@20010000 { 229 compatible = "rockchip,rk3066a-efuse"; 230 reg = <0x20010000 0x4000>; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 clocks = <&cru PCLK_EFUSE>; 234 clock-names = "pclk_efuse"; 235 236 cpu_leakage: cpu_leakage@17 { 237 reg = <0x17 0x1>; 238 }; 239 }; 240 241 timer0: timer@20038000 { 242 compatible = "snps,dw-apb-timer"; 243 reg = <0x20038000 0x100>; 244 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 246 clock-names = "timer", "pclk"; 247 }; 248 249 timer1: timer@2003a000 { 250 compatible = "snps,dw-apb-timer"; 251 reg = <0x2003a000 0x100>; 252 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 254 clock-names = "timer", "pclk"; 255 }; 256 257 tsadc: tsadc@20060000 { 258 compatible = "rockchip,rk3066-tsadc"; 259 reg = <0x20060000 0x100>; 260 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 261 clock-names = "saradc", "apb_pclk"; 262 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 263 #io-channel-cells = <1>; 264 resets = <&cru SRST_TSADC>; 265 reset-names = "saradc-apb"; 266 status = "disabled"; 267 }; 268 269 pinctrl: pinctrl { 270 compatible = "rockchip,rk3066a-pinctrl"; 271 rockchip,grf = <&grf>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges; 275 276 gpio0: gpio0@20034000 { 277 compatible = "rockchip,gpio-bank"; 278 reg = <0x20034000 0x100>; 279 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&cru PCLK_GPIO0>; 281 282 gpio-controller; 283 #gpio-cells = <2>; 284 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 }; 288 289 gpio1: gpio1@2003c000 { 290 compatible = "rockchip,gpio-bank"; 291 reg = <0x2003c000 0x100>; 292 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cru PCLK_GPIO1>; 294 295 gpio-controller; 296 #gpio-cells = <2>; 297 298 interrupt-controller; 299 #interrupt-cells = <2>; 300 }; 301 302 gpio2: gpio2@2003e000 { 303 compatible = "rockchip,gpio-bank"; 304 reg = <0x2003e000 0x100>; 305 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cru PCLK_GPIO2>; 307 308 gpio-controller; 309 #gpio-cells = <2>; 310 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 315 gpio3: gpio3@20080000 { 316 compatible = "rockchip,gpio-bank"; 317 reg = <0x20080000 0x100>; 318 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&cru PCLK_GPIO3>; 320 321 gpio-controller; 322 #gpio-cells = <2>; 323 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 }; 327 328 gpio4: gpio4@20084000 { 329 compatible = "rockchip,gpio-bank"; 330 reg = <0x20084000 0x100>; 331 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru PCLK_GPIO4>; 333 334 gpio-controller; 335 #gpio-cells = <2>; 336 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 gpio6: gpio6@2000a000 { 342 compatible = "rockchip,gpio-bank"; 343 reg = <0x2000a000 0x100>; 344 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cru PCLK_GPIO6>; 346 347 gpio-controller; 348 #gpio-cells = <2>; 349 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 }; 353 354 pcfg_pull_default: pcfg-pull-default { 355 bias-pull-pin-default; 356 }; 357 358 pcfg_pull_none: pcfg-pull-none { 359 bias-disable; 360 }; 361 362 emac { 363 emac_xfer: emac-xfer { 364 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 365 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 366 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 367 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 368 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 369 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 370 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 371 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 372 }; 373 374 emac_mdio: emac-mdio { 375 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 376 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 377 }; 378 }; 379 380 emmc { 381 emmc_clk: emmc-clk { 382 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 383 }; 384 385 emmc_cmd: emmc-cmd { 386 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 387 }; 388 389 emmc_rst: emmc-rst { 390 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 391 }; 392 393 /* 394 * The data pins are shared between nandc and emmc and 395 * not accessible through pinctrl. Also they should've 396 * been already set correctly by firmware, as 397 * flash/emmc is the boot-device. 398 */ 399 }; 400 401 hdmi { 402 hdmi_hpd: hdmi-hpd { 403 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 404 }; 405 406 hdmii2c_xfer: hdmii2c-xfer { 407 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 408 <0 RK_PA2 1 &pcfg_pull_none>; 409 }; 410 }; 411 412 i2c0 { 413 i2c0_xfer: i2c0-xfer { 414 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 415 <2 RK_PD5 1 &pcfg_pull_none>; 416 }; 417 }; 418 419 i2c1 { 420 i2c1_xfer: i2c1-xfer { 421 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 422 <2 RK_PD7 1 &pcfg_pull_none>; 423 }; 424 }; 425 426 i2c2 { 427 i2c2_xfer: i2c2-xfer { 428 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 429 <3 RK_PA1 1 &pcfg_pull_none>; 430 }; 431 }; 432 433 i2c3 { 434 i2c3_xfer: i2c3-xfer { 435 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 436 <3 RK_PA3 2 &pcfg_pull_none>; 437 }; 438 }; 439 440 i2c4 { 441 i2c4_xfer: i2c4-xfer { 442 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 443 <3 RK_PA5 1 &pcfg_pull_none>; 444 }; 445 }; 446 447 pwm0 { 448 pwm0_out: pwm0-out { 449 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 450 }; 451 }; 452 453 pwm1 { 454 pwm1_out: pwm1-out { 455 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 456 }; 457 }; 458 459 pwm2 { 460 pwm2_out: pwm2-out { 461 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 462 }; 463 }; 464 465 pwm3 { 466 pwm3_out: pwm3-out { 467 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 468 }; 469 }; 470 471 spi0 { 472 spi0_clk: spi0-clk { 473 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 474 }; 475 spi0_cs0: spi0-cs0 { 476 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 477 }; 478 spi0_tx: spi0-tx { 479 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 480 }; 481 spi0_rx: spi0-rx { 482 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 483 }; 484 spi0_cs1: spi0-cs1 { 485 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 486 }; 487 }; 488 489 spi1 { 490 spi1_clk: spi1-clk { 491 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 492 }; 493 spi1_cs0: spi1-cs0 { 494 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 495 }; 496 spi1_rx: spi1-rx { 497 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 498 }; 499 spi1_tx: spi1-tx { 500 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 501 }; 502 spi1_cs1: spi1-cs1 { 503 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 504 }; 505 }; 506 507 uart0 { 508 uart0_xfer: uart0-xfer { 509 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 510 <1 RK_PA1 1 &pcfg_pull_default>; 511 }; 512 513 uart0_cts: uart0-cts { 514 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 515 }; 516 517 uart0_rts: uart0-rts { 518 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 519 }; 520 }; 521 522 uart1 { 523 uart1_xfer: uart1-xfer { 524 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 525 <1 RK_PA5 1 &pcfg_pull_default>; 526 }; 527 528 uart1_cts: uart1-cts { 529 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 530 }; 531 532 uart1_rts: uart1-rts { 533 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 534 }; 535 }; 536 537 uart2 { 538 uart2_xfer: uart2-xfer { 539 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 540 <1 RK_PB1 1 &pcfg_pull_default>; 541 }; 542 /* no rts / cts for uart2 */ 543 }; 544 545 uart3 { 546 uart3_xfer: uart3-xfer { 547 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 548 <3 RK_PD4 1 &pcfg_pull_default>; 549 }; 550 551 uart3_cts: uart3-cts { 552 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 553 }; 554 555 uart3_rts: uart3-rts { 556 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 557 }; 558 }; 559 560 sd0 { 561 sd0_clk: sd0-clk { 562 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 563 }; 564 565 sd0_cmd: sd0-cmd { 566 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 567 }; 568 569 sd0_cd: sd0-cd { 570 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 571 }; 572 573 sd0_wp: sd0-wp { 574 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 575 }; 576 577 sd0_bus1: sd0-bus-width1 { 578 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 579 }; 580 581 sd0_bus4: sd0-bus-width4 { 582 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 583 <3 RK_PB3 1 &pcfg_pull_default>, 584 <3 RK_PB4 1 &pcfg_pull_default>, 585 <3 RK_PB5 1 &pcfg_pull_default>; 586 }; 587 }; 588 589 sd1 { 590 sd1_clk: sd1-clk { 591 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 592 }; 593 594 sd1_cmd: sd1-cmd { 595 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 596 }; 597 598 sd1_cd: sd1-cd { 599 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 600 }; 601 602 sd1_wp: sd1-wp { 603 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 604 }; 605 606 sd1_bus1: sd1-bus-width1 { 607 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 608 }; 609 610 sd1_bus4: sd1-bus-width4 { 611 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 612 <3 RK_PC2 1 &pcfg_pull_default>, 613 <3 RK_PC3 1 &pcfg_pull_default>, 614 <3 RK_PC4 1 &pcfg_pull_default>; 615 }; 616 }; 617 618 i2s0 { 619 i2s0_bus: i2s0-bus { 620 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 621 <0 RK_PB0 1 &pcfg_pull_default>, 622 <0 RK_PB1 1 &pcfg_pull_default>, 623 <0 RK_PB2 1 &pcfg_pull_default>, 624 <0 RK_PB3 1 &pcfg_pull_default>, 625 <0 RK_PB4 1 &pcfg_pull_default>, 626 <0 RK_PB5 1 &pcfg_pull_default>, 627 <0 RK_PB6 1 &pcfg_pull_default>, 628 <0 RK_PB7 1 &pcfg_pull_default>; 629 }; 630 }; 631 632 i2s1 { 633 i2s1_bus: i2s1-bus { 634 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 635 <0 RK_PC1 1 &pcfg_pull_default>, 636 <0 RK_PC2 1 &pcfg_pull_default>, 637 <0 RK_PC3 1 &pcfg_pull_default>, 638 <0 RK_PC4 1 &pcfg_pull_default>, 639 <0 RK_PC5 1 &pcfg_pull_default>; 640 }; 641 }; 642 643 i2s2 { 644 i2s2_bus: i2s2-bus { 645 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 646 <0 RK_PD1 1 &pcfg_pull_default>, 647 <0 RK_PD2 1 &pcfg_pull_default>, 648 <0 RK_PD3 1 &pcfg_pull_default>, 649 <0 RK_PD4 1 &pcfg_pull_default>, 650 <0 RK_PD5 1 &pcfg_pull_default>; 651 }; 652 }; 653 }; 654}; 655 656&gpu { 657 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 658 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "gp", 669 "gpmmu", 670 "pp0", 671 "ppmmu0", 672 "pp1", 673 "ppmmu1", 674 "pp2", 675 "ppmmu2", 676 "pp3", 677 "ppmmu3"; 678 power-domains = <&power RK3066_PD_GPU>; 679}; 680 681&grf { 682 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; 683 684 usbphy: usbphy { 685 compatible = "rockchip,rk3066a-usb-phy", 686 "rockchip,rk3288-usb-phy"; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 691 usbphy0: usb-phy@17c { 692 reg = <0x17c>; 693 clocks = <&cru SCLK_OTGPHY0>; 694 clock-names = "phyclk"; 695 #clock-cells = <0>; 696 #phy-cells = <0>; 697 }; 698 699 usbphy1: usb-phy@188 { 700 reg = <0x188>; 701 clocks = <&cru SCLK_OTGPHY1>; 702 clock-names = "phyclk"; 703 #clock-cells = <0>; 704 #phy-cells = <0>; 705 }; 706 }; 707}; 708 709&i2c0 { 710 pinctrl-names = "default"; 711 pinctrl-0 = <&i2c0_xfer>; 712}; 713 714&i2c1 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c1_xfer>; 717}; 718 719&i2c2 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&i2c2_xfer>; 722}; 723 724&i2c3 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&i2c3_xfer>; 727}; 728 729&i2c4 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c4_xfer>; 732}; 733 734&mmc0 { 735 clock-frequency = <50000000>; 736 dmas = <&dmac2 1>; 737 dma-names = "rx-tx"; 738 max-frequency = <50000000>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 741}; 742 743&mmc1 { 744 dmas = <&dmac2 3>; 745 dma-names = "rx-tx"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 748}; 749 750&emmc { 751 dmas = <&dmac2 4>; 752 dma-names = "rx-tx"; 753}; 754 755&pmu { 756 power: power-controller { 757 compatible = "rockchip,rk3066-power-controller"; 758 #power-domain-cells = <1>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 power-domain@RK3066_PD_VIO { 763 reg = <RK3066_PD_VIO>; 764 clocks = <&cru ACLK_LCDC0>, 765 <&cru ACLK_LCDC1>, 766 <&cru DCLK_LCDC0>, 767 <&cru DCLK_LCDC1>, 768 <&cru HCLK_LCDC0>, 769 <&cru HCLK_LCDC1>, 770 <&cru SCLK_CIF1>, 771 <&cru ACLK_CIF1>, 772 <&cru HCLK_CIF1>, 773 <&cru SCLK_CIF0>, 774 <&cru ACLK_CIF0>, 775 <&cru HCLK_CIF0>, 776 <&cru HCLK_HDMI>, 777 <&cru ACLK_IPP>, 778 <&cru HCLK_IPP>, 779 <&cru ACLK_RGA>, 780 <&cru HCLK_RGA>; 781 pm_qos = <&qos_lcdc0>, 782 <&qos_lcdc1>, 783 <&qos_cif0>, 784 <&qos_cif1>, 785 <&qos_ipp>, 786 <&qos_rga>; 787 #power-domain-cells = <0>; 788 }; 789 790 power-domain@RK3066_PD_VIDEO { 791 reg = <RK3066_PD_VIDEO>; 792 clocks = <&cru ACLK_VDPU>, 793 <&cru ACLK_VEPU>, 794 <&cru HCLK_VDPU>, 795 <&cru HCLK_VEPU>; 796 pm_qos = <&qos_vpu>; 797 #power-domain-cells = <0>; 798 }; 799 800 power-domain@RK3066_PD_GPU { 801 reg = <RK3066_PD_GPU>; 802 clocks = <&cru ACLK_GPU>; 803 pm_qos = <&qos_gpu>; 804 #power-domain-cells = <0>; 805 }; 806 }; 807}; 808 809&pwm0 { 810 pinctrl-names = "default"; 811 pinctrl-0 = <&pwm0_out>; 812}; 813 814&pwm1 { 815 pinctrl-names = "default"; 816 pinctrl-0 = <&pwm1_out>; 817}; 818 819&pwm2 { 820 pinctrl-names = "default"; 821 pinctrl-0 = <&pwm2_out>; 822}; 823 824&pwm3 { 825 pinctrl-names = "default"; 826 pinctrl-0 = <&pwm3_out>; 827}; 828 829&spi0 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 832}; 833 834&spi1 { 835 pinctrl-names = "default"; 836 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 837}; 838 839&uart0 { 840 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 841 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 842 dma-names = "tx", "rx"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&uart0_xfer>; 845}; 846 847&uart1 { 848 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 849 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 850 dma-names = "tx", "rx"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&uart1_xfer>; 853}; 854 855&uart2 { 856 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 857 dmas = <&dmac2 6>, <&dmac2 7>; 858 dma-names = "tx", "rx"; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&uart2_xfer>; 861}; 862 863&uart3 { 864 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 865 dmas = <&dmac2 8>, <&dmac2 9>; 866 dma-names = "tx", "rx"; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&uart3_xfer>; 869}; 870 871&vpu { 872 power-domains = <&power RK3066_PD_VIDEO>; 873}; 874 875&wdt { 876 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 877}; 878 879&emac { 880 compatible = "rockchip,rk3066-emac"; 881}; 882