1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 }; 54 55 clocks { 56 clk_hse: clk-hse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 }; 61 62 clk_hsi: clk-hsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <64000000>; 66 }; 67 68 clk_lse: clk-lse { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 }; 73 74 clk_lsi: clk-lsi { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 }; 79 80 clk_csi: clk-csi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <4000000>; 84 }; 85 }; 86 87 thermal-zones { 88 cpu_thermal: cpu-thermal { 89 polling-delay-passive = <0>; 90 polling-delay = <0>; 91 thermal-sensors = <&dts>; 92 93 trips { 94 cpu_alert1: cpu-alert1 { 95 temperature = <85000>; 96 hysteresis = <0>; 97 type = "passive"; 98 }; 99 100 cpu-crit { 101 temperature = <120000>; 102 hysteresis = <0>; 103 type = "critical"; 104 }; 105 }; 106 107 cooling-maps { 108 }; 109 }; 110 }; 111 112 booster: regulator-booster { 113 compatible = "st,stm32mp1-booster"; 114 st,syscfg = <&syscfg>; 115 status = "disabled"; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 interrupt-parent = <&intc>; 123 ranges; 124 125 timers2: timer@40000000 { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 compatible = "st,stm32-timers"; 129 reg = <0x40000000 0x400>; 130 clocks = <&rcc TIM2_K>; 131 clock-names = "int"; 132 dmas = <&dmamux1 18 0x400 0x1>, 133 <&dmamux1 19 0x400 0x1>, 134 <&dmamux1 20 0x400 0x1>, 135 <&dmamux1 21 0x400 0x1>, 136 <&dmamux1 22 0x400 0x1>; 137 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 138 status = "disabled"; 139 140 pwm { 141 compatible = "st,stm32-pwm"; 142 #pwm-cells = <3>; 143 status = "disabled"; 144 }; 145 146 timer@1 { 147 compatible = "st,stm32h7-timer-trigger"; 148 reg = <1>; 149 status = "disabled"; 150 }; 151 152 counter { 153 compatible = "st,stm32-timer-counter"; 154 status = "disabled"; 155 }; 156 }; 157 158 timers3: timer@40001000 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "st,stm32-timers"; 162 reg = <0x40001000 0x400>; 163 clocks = <&rcc TIM3_K>; 164 clock-names = "int"; 165 dmas = <&dmamux1 23 0x400 0x1>, 166 <&dmamux1 24 0x400 0x1>, 167 <&dmamux1 25 0x400 0x1>, 168 <&dmamux1 26 0x400 0x1>, 169 <&dmamux1 27 0x400 0x1>, 170 <&dmamux1 28 0x400 0x1>; 171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 172 status = "disabled"; 173 174 pwm { 175 compatible = "st,stm32-pwm"; 176 #pwm-cells = <3>; 177 status = "disabled"; 178 }; 179 180 timer@2 { 181 compatible = "st,stm32h7-timer-trigger"; 182 reg = <2>; 183 status = "disabled"; 184 }; 185 186 counter { 187 compatible = "st,stm32-timer-counter"; 188 status = "disabled"; 189 }; 190 }; 191 192 timers4: timer@40002000 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "st,stm32-timers"; 196 reg = <0x40002000 0x400>; 197 clocks = <&rcc TIM4_K>; 198 clock-names = "int"; 199 dmas = <&dmamux1 29 0x400 0x1>, 200 <&dmamux1 30 0x400 0x1>, 201 <&dmamux1 31 0x400 0x1>, 202 <&dmamux1 32 0x400 0x1>; 203 dma-names = "ch1", "ch2", "ch3", "ch4"; 204 status = "disabled"; 205 206 pwm { 207 compatible = "st,stm32-pwm"; 208 #pwm-cells = <3>; 209 status = "disabled"; 210 }; 211 212 timer@3 { 213 compatible = "st,stm32h7-timer-trigger"; 214 reg = <3>; 215 status = "disabled"; 216 }; 217 218 counter { 219 compatible = "st,stm32-timer-counter"; 220 status = "disabled"; 221 }; 222 }; 223 224 timers5: timer@40003000 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "st,stm32-timers"; 228 reg = <0x40003000 0x400>; 229 clocks = <&rcc TIM5_K>; 230 clock-names = "int"; 231 dmas = <&dmamux1 55 0x400 0x1>, 232 <&dmamux1 56 0x400 0x1>, 233 <&dmamux1 57 0x400 0x1>, 234 <&dmamux1 58 0x400 0x1>, 235 <&dmamux1 59 0x400 0x1>, 236 <&dmamux1 60 0x400 0x1>; 237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 238 status = "disabled"; 239 240 pwm { 241 compatible = "st,stm32-pwm"; 242 #pwm-cells = <3>; 243 status = "disabled"; 244 }; 245 246 timer@4 { 247 compatible = "st,stm32h7-timer-trigger"; 248 reg = <4>; 249 status = "disabled"; 250 }; 251 252 counter { 253 compatible = "st,stm32-timer-counter"; 254 status = "disabled"; 255 }; 256 }; 257 258 timers6: timer@40004000 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "st,stm32-timers"; 262 reg = <0x40004000 0x400>; 263 clocks = <&rcc TIM6_K>; 264 clock-names = "int"; 265 dmas = <&dmamux1 69 0x400 0x1>; 266 dma-names = "up"; 267 status = "disabled"; 268 269 timer@5 { 270 compatible = "st,stm32h7-timer-trigger"; 271 reg = <5>; 272 status = "disabled"; 273 }; 274 }; 275 276 timers7: timer@40005000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "st,stm32-timers"; 280 reg = <0x40005000 0x400>; 281 clocks = <&rcc TIM7_K>; 282 clock-names = "int"; 283 dmas = <&dmamux1 70 0x400 0x1>; 284 dma-names = "up"; 285 status = "disabled"; 286 287 timer@6 { 288 compatible = "st,stm32h7-timer-trigger"; 289 reg = <6>; 290 status = "disabled"; 291 }; 292 }; 293 294 timers12: timer@40006000 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 compatible = "st,stm32-timers"; 298 reg = <0x40006000 0x400>; 299 clocks = <&rcc TIM12_K>; 300 clock-names = "int"; 301 status = "disabled"; 302 303 pwm { 304 compatible = "st,stm32-pwm"; 305 #pwm-cells = <3>; 306 status = "disabled"; 307 }; 308 309 timer@11 { 310 compatible = "st,stm32h7-timer-trigger"; 311 reg = <11>; 312 status = "disabled"; 313 }; 314 }; 315 316 timers13: timer@40007000 { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 compatible = "st,stm32-timers"; 320 reg = <0x40007000 0x400>; 321 clocks = <&rcc TIM13_K>; 322 clock-names = "int"; 323 status = "disabled"; 324 325 pwm { 326 compatible = "st,stm32-pwm"; 327 #pwm-cells = <3>; 328 status = "disabled"; 329 }; 330 331 timer@12 { 332 compatible = "st,stm32h7-timer-trigger"; 333 reg = <12>; 334 status = "disabled"; 335 }; 336 }; 337 338 timers14: timer@40008000 { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 compatible = "st,stm32-timers"; 342 reg = <0x40008000 0x400>; 343 clocks = <&rcc TIM14_K>; 344 clock-names = "int"; 345 status = "disabled"; 346 347 pwm { 348 compatible = "st,stm32-pwm"; 349 #pwm-cells = <3>; 350 status = "disabled"; 351 }; 352 353 timer@13 { 354 compatible = "st,stm32h7-timer-trigger"; 355 reg = <13>; 356 status = "disabled"; 357 }; 358 }; 359 360 lptimer1: timer@40009000 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 compatible = "st,stm32-lptimer"; 364 reg = <0x40009000 0x400>; 365 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&rcc LPTIM1_K>; 367 clock-names = "mux"; 368 wakeup-source; 369 status = "disabled"; 370 371 pwm { 372 compatible = "st,stm32-pwm-lp"; 373 #pwm-cells = <3>; 374 status = "disabled"; 375 }; 376 377 trigger@0 { 378 compatible = "st,stm32-lptimer-trigger"; 379 reg = <0>; 380 status = "disabled"; 381 }; 382 383 counter { 384 compatible = "st,stm32-lptimer-counter"; 385 status = "disabled"; 386 }; 387 }; 388 389 spi2: spi@4000b000 { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 compatible = "st,stm32h7-spi"; 393 reg = <0x4000b000 0x400>; 394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&rcc SPI2_K>; 396 resets = <&rcc SPI2_R>; 397 dmas = <&dmamux1 39 0x400 0x05>, 398 <&dmamux1 40 0x400 0x05>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 }; 402 403 i2s2: audio-controller@4000b000 { 404 compatible = "st,stm32h7-i2s"; 405 #sound-dai-cells = <0>; 406 reg = <0x4000b000 0x400>; 407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 408 dmas = <&dmamux1 39 0x400 0x01>, 409 <&dmamux1 40 0x400 0x01>; 410 dma-names = "rx", "tx"; 411 status = "disabled"; 412 }; 413 414 spi3: spi@4000c000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "st,stm32h7-spi"; 418 reg = <0x4000c000 0x400>; 419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&rcc SPI3_K>; 421 resets = <&rcc SPI3_R>; 422 dmas = <&dmamux1 61 0x400 0x05>, 423 <&dmamux1 62 0x400 0x05>; 424 dma-names = "rx", "tx"; 425 status = "disabled"; 426 }; 427 428 i2s3: audio-controller@4000c000 { 429 compatible = "st,stm32h7-i2s"; 430 #sound-dai-cells = <0>; 431 reg = <0x4000c000 0x400>; 432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 433 dmas = <&dmamux1 61 0x400 0x01>, 434 <&dmamux1 62 0x400 0x01>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 spdifrx: audio-controller@4000d000 { 440 compatible = "st,stm32h7-spdifrx"; 441 #sound-dai-cells = <0>; 442 reg = <0x4000d000 0x400>; 443 clocks = <&rcc SPDIF_K>; 444 clock-names = "kclk"; 445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 446 dmas = <&dmamux1 93 0x400 0x01>, 447 <&dmamux1 94 0x400 0x01>; 448 dma-names = "rx", "rx-ctrl"; 449 status = "disabled"; 450 }; 451 452 usart2: serial@4000e000 { 453 compatible = "st,stm32h7-uart"; 454 reg = <0x4000e000 0x400>; 455 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&rcc USART2_K>; 457 wakeup-source; 458 status = "disabled"; 459 }; 460 461 usart3: serial@4000f000 { 462 compatible = "st,stm32h7-uart"; 463 reg = <0x4000f000 0x400>; 464 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&rcc USART3_K>; 466 wakeup-source; 467 status = "disabled"; 468 }; 469 470 uart4: serial@40010000 { 471 compatible = "st,stm32h7-uart"; 472 reg = <0x40010000 0x400>; 473 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&rcc UART4_K>; 475 wakeup-source; 476 status = "disabled"; 477 }; 478 479 uart5: serial@40011000 { 480 compatible = "st,stm32h7-uart"; 481 reg = <0x40011000 0x400>; 482 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&rcc UART5_K>; 484 wakeup-source; 485 status = "disabled"; 486 }; 487 488 i2c1: i2c@40012000 { 489 compatible = "st,stm32mp15-i2c"; 490 reg = <0x40012000 0x400>; 491 interrupt-names = "event", "error"; 492 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&rcc I2C1_K>; 495 resets = <&rcc I2C1_R>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 st,syscfg-fmp = <&syscfg 0x4 0x1>; 499 wakeup-source; 500 i2c-analog-filter; 501 status = "disabled"; 502 }; 503 504 i2c2: i2c@40013000 { 505 compatible = "st,stm32mp15-i2c"; 506 reg = <0x40013000 0x400>; 507 interrupt-names = "event", "error"; 508 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&rcc I2C2_K>; 511 resets = <&rcc I2C2_R>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 st,syscfg-fmp = <&syscfg 0x4 0x2>; 515 wakeup-source; 516 i2c-analog-filter; 517 status = "disabled"; 518 }; 519 520 i2c3: i2c@40014000 { 521 compatible = "st,stm32mp15-i2c"; 522 reg = <0x40014000 0x400>; 523 interrupt-names = "event", "error"; 524 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&rcc I2C3_K>; 527 resets = <&rcc I2C3_R>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 st,syscfg-fmp = <&syscfg 0x4 0x4>; 531 wakeup-source; 532 i2c-analog-filter; 533 status = "disabled"; 534 }; 535 536 i2c5: i2c@40015000 { 537 compatible = "st,stm32mp15-i2c"; 538 reg = <0x40015000 0x400>; 539 interrupt-names = "event", "error"; 540 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&rcc I2C5_K>; 543 resets = <&rcc I2C5_R>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 st,syscfg-fmp = <&syscfg 0x4 0x10>; 547 wakeup-source; 548 i2c-analog-filter; 549 status = "disabled"; 550 }; 551 552 cec: cec@40016000 { 553 compatible = "st,stm32-cec"; 554 reg = <0x40016000 0x400>; 555 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&rcc CEC_K>, <&rcc CEC>; 557 clock-names = "cec", "hdmi-cec"; 558 status = "disabled"; 559 }; 560 561 dac: dac@40017000 { 562 compatible = "st,stm32h7-dac-core"; 563 reg = <0x40017000 0x400>; 564 clocks = <&rcc DAC12>; 565 clock-names = "pclk"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 570 dac1: dac@1 { 571 compatible = "st,stm32-dac"; 572 #io-channel-cells = <1>; 573 reg = <1>; 574 status = "disabled"; 575 }; 576 577 dac2: dac@2 { 578 compatible = "st,stm32-dac"; 579 #io-channel-cells = <1>; 580 reg = <2>; 581 status = "disabled"; 582 }; 583 }; 584 585 uart7: serial@40018000 { 586 compatible = "st,stm32h7-uart"; 587 reg = <0x40018000 0x400>; 588 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&rcc UART7_K>; 590 wakeup-source; 591 status = "disabled"; 592 }; 593 594 uart8: serial@40019000 { 595 compatible = "st,stm32h7-uart"; 596 reg = <0x40019000 0x400>; 597 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&rcc UART8_K>; 599 wakeup-source; 600 status = "disabled"; 601 }; 602 603 timers1: timer@44000000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "st,stm32-timers"; 607 reg = <0x44000000 0x400>; 608 clocks = <&rcc TIM1_K>; 609 clock-names = "int"; 610 dmas = <&dmamux1 11 0x400 0x1>, 611 <&dmamux1 12 0x400 0x1>, 612 <&dmamux1 13 0x400 0x1>, 613 <&dmamux1 14 0x400 0x1>, 614 <&dmamux1 15 0x400 0x1>, 615 <&dmamux1 16 0x400 0x1>, 616 <&dmamux1 17 0x400 0x1>; 617 dma-names = "ch1", "ch2", "ch3", "ch4", 618 "up", "trig", "com"; 619 status = "disabled"; 620 621 pwm { 622 compatible = "st,stm32-pwm"; 623 #pwm-cells = <3>; 624 status = "disabled"; 625 }; 626 627 timer@0 { 628 compatible = "st,stm32h7-timer-trigger"; 629 reg = <0>; 630 status = "disabled"; 631 }; 632 633 counter { 634 compatible = "st,stm32-timer-counter"; 635 status = "disabled"; 636 }; 637 }; 638 639 timers8: timer@44001000 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 compatible = "st,stm32-timers"; 643 reg = <0x44001000 0x400>; 644 clocks = <&rcc TIM8_K>; 645 clock-names = "int"; 646 dmas = <&dmamux1 47 0x400 0x1>, 647 <&dmamux1 48 0x400 0x1>, 648 <&dmamux1 49 0x400 0x1>, 649 <&dmamux1 50 0x400 0x1>, 650 <&dmamux1 51 0x400 0x1>, 651 <&dmamux1 52 0x400 0x1>, 652 <&dmamux1 53 0x400 0x1>; 653 dma-names = "ch1", "ch2", "ch3", "ch4", 654 "up", "trig", "com"; 655 status = "disabled"; 656 657 pwm { 658 compatible = "st,stm32-pwm"; 659 #pwm-cells = <3>; 660 status = "disabled"; 661 }; 662 663 timer@7 { 664 compatible = "st,stm32h7-timer-trigger"; 665 reg = <7>; 666 status = "disabled"; 667 }; 668 669 counter { 670 compatible = "st,stm32-timer-counter"; 671 status = "disabled"; 672 }; 673 }; 674 675 usart6: serial@44003000 { 676 compatible = "st,stm32h7-uart"; 677 reg = <0x44003000 0x400>; 678 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&rcc USART6_K>; 680 wakeup-source; 681 status = "disabled"; 682 }; 683 684 spi1: spi@44004000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "st,stm32h7-spi"; 688 reg = <0x44004000 0x400>; 689 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&rcc SPI1_K>; 691 resets = <&rcc SPI1_R>; 692 dmas = <&dmamux1 37 0x400 0x05>, 693 <&dmamux1 38 0x400 0x05>; 694 dma-names = "rx", "tx"; 695 status = "disabled"; 696 }; 697 698 i2s1: audio-controller@44004000 { 699 compatible = "st,stm32h7-i2s"; 700 #sound-dai-cells = <0>; 701 reg = <0x44004000 0x400>; 702 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 703 dmas = <&dmamux1 37 0x400 0x01>, 704 <&dmamux1 38 0x400 0x01>; 705 dma-names = "rx", "tx"; 706 status = "disabled"; 707 }; 708 709 spi4: spi@44005000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "st,stm32h7-spi"; 713 reg = <0x44005000 0x400>; 714 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&rcc SPI4_K>; 716 resets = <&rcc SPI4_R>; 717 dmas = <&dmamux1 83 0x400 0x05>, 718 <&dmamux1 84 0x400 0x05>; 719 dma-names = "rx", "tx"; 720 status = "disabled"; 721 }; 722 723 timers15: timer@44006000 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 compatible = "st,stm32-timers"; 727 reg = <0x44006000 0x400>; 728 clocks = <&rcc TIM15_K>; 729 clock-names = "int"; 730 dmas = <&dmamux1 105 0x400 0x1>, 731 <&dmamux1 106 0x400 0x1>, 732 <&dmamux1 107 0x400 0x1>, 733 <&dmamux1 108 0x400 0x1>; 734 dma-names = "ch1", "up", "trig", "com"; 735 status = "disabled"; 736 737 pwm { 738 compatible = "st,stm32-pwm"; 739 #pwm-cells = <3>; 740 status = "disabled"; 741 }; 742 743 timer@14 { 744 compatible = "st,stm32h7-timer-trigger"; 745 reg = <14>; 746 status = "disabled"; 747 }; 748 }; 749 750 timers16: timer@44007000 { 751 #address-cells = <1>; 752 #size-cells = <0>; 753 compatible = "st,stm32-timers"; 754 reg = <0x44007000 0x400>; 755 clocks = <&rcc TIM16_K>; 756 clock-names = "int"; 757 dmas = <&dmamux1 109 0x400 0x1>, 758 <&dmamux1 110 0x400 0x1>; 759 dma-names = "ch1", "up"; 760 status = "disabled"; 761 762 pwm { 763 compatible = "st,stm32-pwm"; 764 #pwm-cells = <3>; 765 status = "disabled"; 766 }; 767 timer@15 { 768 compatible = "st,stm32h7-timer-trigger"; 769 reg = <15>; 770 status = "disabled"; 771 }; 772 }; 773 774 timers17: timer@44008000 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 compatible = "st,stm32-timers"; 778 reg = <0x44008000 0x400>; 779 clocks = <&rcc TIM17_K>; 780 clock-names = "int"; 781 dmas = <&dmamux1 111 0x400 0x1>, 782 <&dmamux1 112 0x400 0x1>; 783 dma-names = "ch1", "up"; 784 status = "disabled"; 785 786 pwm { 787 compatible = "st,stm32-pwm"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 timer@16 { 793 compatible = "st,stm32h7-timer-trigger"; 794 reg = <16>; 795 status = "disabled"; 796 }; 797 }; 798 799 spi5: spi@44009000 { 800 #address-cells = <1>; 801 #size-cells = <0>; 802 compatible = "st,stm32h7-spi"; 803 reg = <0x44009000 0x400>; 804 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&rcc SPI5_K>; 806 resets = <&rcc SPI5_R>; 807 dmas = <&dmamux1 85 0x400 0x05>, 808 <&dmamux1 86 0x400 0x05>; 809 dma-names = "rx", "tx"; 810 status = "disabled"; 811 }; 812 813 sai1: sai@4400a000 { 814 compatible = "st,stm32h7-sai"; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 ranges = <0 0x4400a000 0x400>; 818 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 819 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 820 resets = <&rcc SAI1_R>; 821 status = "disabled"; 822 823 sai1a: audio-controller@4400a004 { 824 #sound-dai-cells = <0>; 825 826 compatible = "st,stm32-sai-sub-a"; 827 reg = <0x4 0x20>; 828 clocks = <&rcc SAI1_K>; 829 clock-names = "sai_ck"; 830 dmas = <&dmamux1 87 0x400 0x01>; 831 status = "disabled"; 832 }; 833 834 sai1b: audio-controller@4400a024 { 835 #sound-dai-cells = <0>; 836 compatible = "st,stm32-sai-sub-b"; 837 reg = <0x24 0x20>; 838 clocks = <&rcc SAI1_K>; 839 clock-names = "sai_ck"; 840 dmas = <&dmamux1 88 0x400 0x01>; 841 status = "disabled"; 842 }; 843 }; 844 845 sai2: sai@4400b000 { 846 compatible = "st,stm32h7-sai"; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 ranges = <0 0x4400b000 0x400>; 850 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 851 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 852 resets = <&rcc SAI2_R>; 853 status = "disabled"; 854 855 sai2a: audio-controller@4400b004 { 856 #sound-dai-cells = <0>; 857 compatible = "st,stm32-sai-sub-a"; 858 reg = <0x4 0x20>; 859 clocks = <&rcc SAI2_K>; 860 clock-names = "sai_ck"; 861 dmas = <&dmamux1 89 0x400 0x01>; 862 status = "disabled"; 863 }; 864 865 sai2b: audio-controller@4400b024 { 866 #sound-dai-cells = <0>; 867 compatible = "st,stm32-sai-sub-b"; 868 reg = <0x24 0x20>; 869 clocks = <&rcc SAI2_K>; 870 clock-names = "sai_ck"; 871 dmas = <&dmamux1 90 0x400 0x01>; 872 status = "disabled"; 873 }; 874 }; 875 876 sai3: sai@4400c000 { 877 compatible = "st,stm32h7-sai"; 878 #address-cells = <1>; 879 #size-cells = <1>; 880 ranges = <0 0x4400c000 0x400>; 881 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 882 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 883 resets = <&rcc SAI3_R>; 884 status = "disabled"; 885 886 sai3a: audio-controller@4400c004 { 887 #sound-dai-cells = <0>; 888 compatible = "st,stm32-sai-sub-a"; 889 reg = <0x04 0x20>; 890 clocks = <&rcc SAI3_K>; 891 clock-names = "sai_ck"; 892 dmas = <&dmamux1 113 0x400 0x01>; 893 status = "disabled"; 894 }; 895 896 sai3b: audio-controller@4400c024 { 897 #sound-dai-cells = <0>; 898 compatible = "st,stm32-sai-sub-b"; 899 reg = <0x24 0x20>; 900 clocks = <&rcc SAI3_K>; 901 clock-names = "sai_ck"; 902 dmas = <&dmamux1 114 0x400 0x01>; 903 status = "disabled"; 904 }; 905 }; 906 907 dfsdm: dfsdm@4400d000 { 908 compatible = "st,stm32mp1-dfsdm"; 909 reg = <0x4400d000 0x800>; 910 clocks = <&rcc DFSDM_K>; 911 clock-names = "dfsdm"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 status = "disabled"; 915 916 dfsdm0: filter@0 { 917 compatible = "st,stm32-dfsdm-adc"; 918 #io-channel-cells = <1>; 919 reg = <0>; 920 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 921 dmas = <&dmamux1 101 0x400 0x01>; 922 dma-names = "rx"; 923 status = "disabled"; 924 }; 925 926 dfsdm1: filter@1 { 927 compatible = "st,stm32-dfsdm-adc"; 928 #io-channel-cells = <1>; 929 reg = <1>; 930 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 931 dmas = <&dmamux1 102 0x400 0x01>; 932 dma-names = "rx"; 933 status = "disabled"; 934 }; 935 936 dfsdm2: filter@2 { 937 compatible = "st,stm32-dfsdm-adc"; 938 #io-channel-cells = <1>; 939 reg = <2>; 940 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 941 dmas = <&dmamux1 103 0x400 0x01>; 942 dma-names = "rx"; 943 status = "disabled"; 944 }; 945 946 dfsdm3: filter@3 { 947 compatible = "st,stm32-dfsdm-adc"; 948 #io-channel-cells = <1>; 949 reg = <3>; 950 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 951 dmas = <&dmamux1 104 0x400 0x01>; 952 dma-names = "rx"; 953 status = "disabled"; 954 }; 955 956 dfsdm4: filter@4 { 957 compatible = "st,stm32-dfsdm-adc"; 958 #io-channel-cells = <1>; 959 reg = <4>; 960 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 961 dmas = <&dmamux1 91 0x400 0x01>; 962 dma-names = "rx"; 963 status = "disabled"; 964 }; 965 966 dfsdm5: filter@5 { 967 compatible = "st,stm32-dfsdm-adc"; 968 #io-channel-cells = <1>; 969 reg = <5>; 970 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 971 dmas = <&dmamux1 92 0x400 0x01>; 972 dma-names = "rx"; 973 status = "disabled"; 974 }; 975 }; 976 977 dma1: dma-controller@48000000 { 978 compatible = "st,stm32-dma"; 979 reg = <0x48000000 0x400>; 980 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&rcc DMA1>; 989 resets = <&rcc DMA1_R>; 990 #dma-cells = <4>; 991 st,mem2mem; 992 dma-requests = <8>; 993 }; 994 995 dma2: dma-controller@48001000 { 996 compatible = "st,stm32-dma"; 997 reg = <0x48001000 0x400>; 998 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&rcc DMA2>; 1007 resets = <&rcc DMA2_R>; 1008 #dma-cells = <4>; 1009 st,mem2mem; 1010 dma-requests = <8>; 1011 }; 1012 1013 dmamux1: dma-router@48002000 { 1014 compatible = "st,stm32h7-dmamux"; 1015 reg = <0x48002000 0x40>; 1016 #dma-cells = <3>; 1017 dma-requests = <128>; 1018 dma-masters = <&dma1 &dma2>; 1019 dma-channels = <16>; 1020 clocks = <&rcc DMAMUX>; 1021 resets = <&rcc DMAMUX_R>; 1022 }; 1023 1024 adc: adc@48003000 { 1025 compatible = "st,stm32mp1-adc-core"; 1026 reg = <0x48003000 0x400>; 1027 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1030 clock-names = "bus", "adc"; 1031 interrupt-controller; 1032 st,syscfg = <&syscfg>; 1033 #interrupt-cells = <1>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 status = "disabled"; 1037 1038 adc1: adc@0 { 1039 compatible = "st,stm32mp1-adc"; 1040 #io-channel-cells = <1>; 1041 reg = <0x0>; 1042 interrupt-parent = <&adc>; 1043 interrupts = <0>; 1044 dmas = <&dmamux1 9 0x400 0x01>; 1045 dma-names = "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 adc2: adc@100 { 1050 compatible = "st,stm32mp1-adc"; 1051 #io-channel-cells = <1>; 1052 reg = <0x100>; 1053 interrupt-parent = <&adc>; 1054 interrupts = <1>; 1055 dmas = <&dmamux1 10 0x400 0x01>; 1056 dma-names = "rx"; 1057 status = "disabled"; 1058 }; 1059 }; 1060 1061 sdmmc3: mmc@48004000 { 1062 compatible = "arm,pl18x", "arm,primecell"; 1063 arm,primecell-periphid = <0x00253180>; 1064 reg = <0x48004000 0x400>; 1065 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1066 interrupt-names = "cmd_irq"; 1067 clocks = <&rcc SDMMC3_K>; 1068 clock-names = "apb_pclk"; 1069 resets = <&rcc SDMMC3_R>; 1070 cap-sd-highspeed; 1071 cap-mmc-highspeed; 1072 max-frequency = <120000000>; 1073 status = "disabled"; 1074 }; 1075 1076 usbotg_hs: usb-otg@49000000 { 1077 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1078 reg = <0x49000000 0x10000>; 1079 clocks = <&rcc USBO_K>; 1080 clock-names = "otg"; 1081 resets = <&rcc USBO_R>; 1082 reset-names = "dwc2"; 1083 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1084 g-rx-fifo-size = <512>; 1085 g-np-tx-fifo-size = <32>; 1086 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1087 dr_mode = "otg"; 1088 usb33d-supply = <&usb33>; 1089 status = "disabled"; 1090 }; 1091 1092 ipcc: mailbox@4c001000 { 1093 compatible = "st,stm32mp1-ipcc"; 1094 #mbox-cells = <1>; 1095 reg = <0x4c001000 0x400>; 1096 st,proc-id = <0>; 1097 interrupts-extended = 1098 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1099 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1100 <&exti 61 1>; 1101 interrupt-names = "rx", "tx", "wakeup"; 1102 clocks = <&rcc IPCC>; 1103 wakeup-source; 1104 status = "disabled"; 1105 }; 1106 1107 dcmi: dcmi@4c006000 { 1108 compatible = "st,stm32-dcmi"; 1109 reg = <0x4c006000 0x400>; 1110 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1111 resets = <&rcc CAMITF_R>; 1112 clocks = <&rcc DCMI>; 1113 clock-names = "mclk"; 1114 dmas = <&dmamux1 75 0x400 0x01>; 1115 dma-names = "tx"; 1116 status = "disabled"; 1117 }; 1118 1119 rcc: rcc@50000000 { 1120 compatible = "st,stm32mp1-rcc", "syscon"; 1121 reg = <0x50000000 0x1000>; 1122 #clock-cells = <1>; 1123 #reset-cells = <1>; 1124 }; 1125 1126 pwr_regulators: pwr@50001000 { 1127 compatible = "st,stm32mp1,pwr-reg"; 1128 reg = <0x50001000 0x10>; 1129 1130 reg11: reg11 { 1131 regulator-name = "reg11"; 1132 regulator-min-microvolt = <1100000>; 1133 regulator-max-microvolt = <1100000>; 1134 }; 1135 1136 reg18: reg18 { 1137 regulator-name = "reg18"; 1138 regulator-min-microvolt = <1800000>; 1139 regulator-max-microvolt = <1800000>; 1140 }; 1141 1142 usb33: usb33 { 1143 regulator-name = "usb33"; 1144 regulator-min-microvolt = <3300000>; 1145 regulator-max-microvolt = <3300000>; 1146 }; 1147 }; 1148 1149 pwr_mcu: pwr_mcu@50001014 { 1150 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 1151 reg = <0x50001014 0x4>; 1152 }; 1153 1154 exti: interrupt-controller@5000d000 { 1155 compatible = "st,stm32mp1-exti", "syscon"; 1156 interrupt-controller; 1157 #interrupt-cells = <2>; 1158 reg = <0x5000d000 0x400>; 1159 }; 1160 1161 syscfg: syscon@50020000 { 1162 compatible = "st,stm32mp157-syscfg", "syscon"; 1163 reg = <0x50020000 0x400>; 1164 clocks = <&rcc SYSCFG>; 1165 }; 1166 1167 lptimer2: timer@50021000 { 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 compatible = "st,stm32-lptimer"; 1171 reg = <0x50021000 0x400>; 1172 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&rcc LPTIM2_K>; 1174 clock-names = "mux"; 1175 wakeup-source; 1176 status = "disabled"; 1177 1178 pwm { 1179 compatible = "st,stm32-pwm-lp"; 1180 #pwm-cells = <3>; 1181 status = "disabled"; 1182 }; 1183 1184 trigger@1 { 1185 compatible = "st,stm32-lptimer-trigger"; 1186 reg = <1>; 1187 status = "disabled"; 1188 }; 1189 1190 counter { 1191 compatible = "st,stm32-lptimer-counter"; 1192 status = "disabled"; 1193 }; 1194 }; 1195 1196 lptimer3: timer@50022000 { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 compatible = "st,stm32-lptimer"; 1200 reg = <0x50022000 0x400>; 1201 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&rcc LPTIM3_K>; 1203 clock-names = "mux"; 1204 wakeup-source; 1205 status = "disabled"; 1206 1207 pwm { 1208 compatible = "st,stm32-pwm-lp"; 1209 #pwm-cells = <3>; 1210 status = "disabled"; 1211 }; 1212 1213 trigger@2 { 1214 compatible = "st,stm32-lptimer-trigger"; 1215 reg = <2>; 1216 status = "disabled"; 1217 }; 1218 }; 1219 1220 lptimer4: timer@50023000 { 1221 compatible = "st,stm32-lptimer"; 1222 reg = <0x50023000 0x400>; 1223 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&rcc LPTIM4_K>; 1225 clock-names = "mux"; 1226 wakeup-source; 1227 status = "disabled"; 1228 1229 pwm { 1230 compatible = "st,stm32-pwm-lp"; 1231 #pwm-cells = <3>; 1232 status = "disabled"; 1233 }; 1234 }; 1235 1236 lptimer5: timer@50024000 { 1237 compatible = "st,stm32-lptimer"; 1238 reg = <0x50024000 0x400>; 1239 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&rcc LPTIM5_K>; 1241 clock-names = "mux"; 1242 wakeup-source; 1243 status = "disabled"; 1244 1245 pwm { 1246 compatible = "st,stm32-pwm-lp"; 1247 #pwm-cells = <3>; 1248 status = "disabled"; 1249 }; 1250 }; 1251 1252 vrefbuf: vrefbuf@50025000 { 1253 compatible = "st,stm32-vrefbuf"; 1254 reg = <0x50025000 0x8>; 1255 regulator-min-microvolt = <1500000>; 1256 regulator-max-microvolt = <2500000>; 1257 clocks = <&rcc VREF>; 1258 status = "disabled"; 1259 }; 1260 1261 sai4: sai@50027000 { 1262 compatible = "st,stm32h7-sai"; 1263 #address-cells = <1>; 1264 #size-cells = <1>; 1265 ranges = <0 0x50027000 0x400>; 1266 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1267 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1268 resets = <&rcc SAI4_R>; 1269 status = "disabled"; 1270 1271 sai4a: audio-controller@50027004 { 1272 #sound-dai-cells = <0>; 1273 compatible = "st,stm32-sai-sub-a"; 1274 reg = <0x04 0x20>; 1275 clocks = <&rcc SAI4_K>; 1276 clock-names = "sai_ck"; 1277 dmas = <&dmamux1 99 0x400 0x01>; 1278 status = "disabled"; 1279 }; 1280 1281 sai4b: audio-controller@50027024 { 1282 #sound-dai-cells = <0>; 1283 compatible = "st,stm32-sai-sub-b"; 1284 reg = <0x24 0x20>; 1285 clocks = <&rcc SAI4_K>; 1286 clock-names = "sai_ck"; 1287 dmas = <&dmamux1 100 0x400 0x01>; 1288 status = "disabled"; 1289 }; 1290 }; 1291 1292 dts: thermal@50028000 { 1293 compatible = "st,stm32-thermal"; 1294 reg = <0x50028000 0x100>; 1295 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&rcc TMPSENS>; 1297 clock-names = "pclk"; 1298 #thermal-sensor-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 hash1: hash@54002000 { 1303 compatible = "st,stm32f756-hash"; 1304 reg = <0x54002000 0x400>; 1305 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&rcc HASH1>; 1307 resets = <&rcc HASH1_R>; 1308 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1309 dma-names = "in"; 1310 dma-maxburst = <2>; 1311 status = "disabled"; 1312 }; 1313 1314 rng1: rng@54003000 { 1315 compatible = "st,stm32-rng"; 1316 reg = <0x54003000 0x400>; 1317 clocks = <&rcc RNG1_K>; 1318 resets = <&rcc RNG1_R>; 1319 status = "disabled"; 1320 }; 1321 1322 mdma1: dma-controller@58000000 { 1323 compatible = "st,stm32h7-mdma"; 1324 reg = <0x58000000 0x1000>; 1325 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&rcc MDMA>; 1327 resets = <&rcc MDMA_R>; 1328 #dma-cells = <5>; 1329 dma-channels = <32>; 1330 dma-requests = <48>; 1331 }; 1332 1333 fmc: memory-controller@58002000 { 1334 #address-cells = <2>; 1335 #size-cells = <1>; 1336 compatible = "st,stm32mp1-fmc2-ebi"; 1337 reg = <0x58002000 0x1000>; 1338 clocks = <&rcc FMC_K>; 1339 resets = <&rcc FMC_R>; 1340 status = "disabled"; 1341 1342 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1343 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1344 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1345 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1346 <4 0 0x80000000 0x10000000>; /* NAND */ 1347 1348 nand-controller@4,0 { 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 compatible = "st,stm32mp1-fmc2-nfc"; 1352 reg = <4 0x00000000 0x1000>, 1353 <4 0x08010000 0x1000>, 1354 <4 0x08020000 0x1000>, 1355 <4 0x01000000 0x1000>, 1356 <4 0x09010000 0x1000>, 1357 <4 0x09020000 0x1000>; 1358 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1359 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1360 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1361 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1362 dma-names = "tx", "rx", "ecc"; 1363 status = "disabled"; 1364 }; 1365 }; 1366 1367 qspi: spi@58003000 { 1368 compatible = "st,stm32f469-qspi"; 1369 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1370 reg-names = "qspi", "qspi_mm"; 1371 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1372 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1373 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1374 dma-names = "tx", "rx"; 1375 clocks = <&rcc QSPI_K>; 1376 resets = <&rcc QSPI_R>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 sdmmc1: mmc@58005000 { 1383 compatible = "arm,pl18x", "arm,primecell"; 1384 arm,primecell-periphid = <0x00253180>; 1385 reg = <0x58005000 0x1000>; 1386 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1387 interrupt-names = "cmd_irq"; 1388 clocks = <&rcc SDMMC1_K>; 1389 clock-names = "apb_pclk"; 1390 resets = <&rcc SDMMC1_R>; 1391 cap-sd-highspeed; 1392 cap-mmc-highspeed; 1393 max-frequency = <120000000>; 1394 status = "disabled"; 1395 }; 1396 1397 sdmmc2: mmc@58007000 { 1398 compatible = "arm,pl18x", "arm,primecell"; 1399 arm,primecell-periphid = <0x00253180>; 1400 reg = <0x58007000 0x1000>; 1401 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1402 interrupt-names = "cmd_irq"; 1403 clocks = <&rcc SDMMC2_K>; 1404 clock-names = "apb_pclk"; 1405 resets = <&rcc SDMMC2_R>; 1406 cap-sd-highspeed; 1407 cap-mmc-highspeed; 1408 max-frequency = <120000000>; 1409 status = "disabled"; 1410 }; 1411 1412 crc1: crc@58009000 { 1413 compatible = "st,stm32f7-crc"; 1414 reg = <0x58009000 0x400>; 1415 clocks = <&rcc CRC1>; 1416 status = "disabled"; 1417 }; 1418 1419 ethernet0: ethernet@5800a000 { 1420 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1421 reg = <0x5800a000 0x2000>; 1422 reg-names = "stmmaceth"; 1423 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1424 interrupt-names = "macirq"; 1425 clock-names = "stmmaceth", 1426 "mac-clk-tx", 1427 "mac-clk-rx", 1428 "eth-ck", 1429 "ptp_ref", 1430 "ethstp"; 1431 clocks = <&rcc ETHMAC>, 1432 <&rcc ETHTX>, 1433 <&rcc ETHRX>, 1434 <&rcc ETHCK_K>, 1435 <&rcc ETHPTP_K>, 1436 <&rcc ETHSTP>; 1437 st,syscon = <&syscfg 0x4>; 1438 snps,mixed-burst; 1439 snps,pbl = <2>; 1440 snps,en-tx-lpi-clockgating; 1441 snps,axi-config = <&stmmac_axi_config_0>; 1442 snps,tso; 1443 status = "disabled"; 1444 1445 stmmac_axi_config_0: stmmac-axi-config { 1446 snps,wr_osr_lmt = <0x7>; 1447 snps,rd_osr_lmt = <0x7>; 1448 snps,blen = <0 0 0 0 16 8 4>; 1449 }; 1450 }; 1451 1452 usbh_ohci: usb@5800c000 { 1453 compatible = "generic-ohci"; 1454 reg = <0x5800c000 0x1000>; 1455 clocks = <&usbphyc>, <&rcc USBH>; 1456 resets = <&rcc USBH_R>; 1457 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1458 status = "disabled"; 1459 }; 1460 1461 usbh_ehci: usb@5800d000 { 1462 compatible = "generic-ehci"; 1463 reg = <0x5800d000 0x1000>; 1464 clocks = <&usbphyc>, <&rcc USBH>; 1465 resets = <&rcc USBH_R>; 1466 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1467 companion = <&usbh_ohci>; 1468 status = "disabled"; 1469 }; 1470 1471 ltdc: display-controller@5a001000 { 1472 compatible = "st,stm32-ltdc"; 1473 reg = <0x5a001000 0x400>; 1474 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&rcc LTDC_PX>; 1477 clock-names = "lcd"; 1478 resets = <&rcc LTDC_R>; 1479 status = "disabled"; 1480 1481 port { 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 }; 1485 }; 1486 1487 iwdg2: watchdog@5a002000 { 1488 compatible = "st,stm32mp1-iwdg"; 1489 reg = <0x5a002000 0x400>; 1490 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 1491 clock-names = "pclk", "lsi"; 1492 status = "disabled"; 1493 }; 1494 1495 usbphyc: usbphyc@5a006000 { 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 #clock-cells = <0>; 1499 compatible = "st,stm32mp1-usbphyc"; 1500 reg = <0x5a006000 0x1000>; 1501 clocks = <&rcc USBPHY_K>; 1502 resets = <&rcc USBPHY_R>; 1503 vdda1v1-supply = <®11>; 1504 vdda1v8-supply = <®18>; 1505 status = "disabled"; 1506 1507 usbphyc_port0: usb-phy@0 { 1508 #phy-cells = <0>; 1509 reg = <0>; 1510 }; 1511 1512 usbphyc_port1: usb-phy@1 { 1513 #phy-cells = <1>; 1514 reg = <1>; 1515 }; 1516 }; 1517 1518 usart1: serial@5c000000 { 1519 compatible = "st,stm32h7-uart"; 1520 reg = <0x5c000000 0x400>; 1521 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1522 clocks = <&rcc USART1_K>; 1523 wakeup-source; 1524 status = "disabled"; 1525 }; 1526 1527 spi6: spi@5c001000 { 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 compatible = "st,stm32h7-spi"; 1531 reg = <0x5c001000 0x400>; 1532 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&rcc SPI6_K>; 1534 resets = <&rcc SPI6_R>; 1535 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1536 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1537 dma-names = "rx", "tx"; 1538 status = "disabled"; 1539 }; 1540 1541 i2c4: i2c@5c002000 { 1542 compatible = "st,stm32mp15-i2c"; 1543 reg = <0x5c002000 0x400>; 1544 interrupt-names = "event", "error"; 1545 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1547 clocks = <&rcc I2C4_K>; 1548 resets = <&rcc I2C4_R>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1552 wakeup-source; 1553 i2c-analog-filter; 1554 status = "disabled"; 1555 }; 1556 1557 rtc: rtc@5c004000 { 1558 compatible = "st,stm32mp1-rtc"; 1559 reg = <0x5c004000 0x400>; 1560 clocks = <&rcc RTCAPB>, <&rcc RTC>; 1561 clock-names = "pclk", "rtc_ck"; 1562 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1563 status = "disabled"; 1564 }; 1565 1566 bsec: efuse@5c005000 { 1567 compatible = "st,stm32mp15-bsec"; 1568 reg = <0x5c005000 0x400>; 1569 #address-cells = <1>; 1570 #size-cells = <1>; 1571 ts_cal1: calib@5c { 1572 reg = <0x5c 0x2>; 1573 }; 1574 ts_cal2: calib@5e { 1575 reg = <0x5e 0x2>; 1576 }; 1577 }; 1578 1579 i2c6: i2c@5c009000 { 1580 compatible = "st,stm32mp15-i2c"; 1581 reg = <0x5c009000 0x400>; 1582 interrupt-names = "event", "error"; 1583 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1585 clocks = <&rcc I2C6_K>; 1586 resets = <&rcc I2C6_R>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1590 wakeup-source; 1591 i2c-analog-filter; 1592 status = "disabled"; 1593 }; 1594 1595 tamp: tamp@5c00a000 { 1596 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1597 reg = <0x5c00a000 0x400>; 1598 }; 1599 1600 /* 1601 * Break node order to solve dependency probe issue between 1602 * pinctrl and exti. 1603 */ 1604 pinctrl: pin-controller@50002000 { 1605 #address-cells = <1>; 1606 #size-cells = <1>; 1607 compatible = "st,stm32mp157-pinctrl"; 1608 ranges = <0 0x50002000 0xa400>; 1609 interrupt-parent = <&exti>; 1610 st,syscfg = <&exti 0x60 0xff>; 1611 pins-are-numbered; 1612 1613 gpioa: gpio@50002000 { 1614 gpio-controller; 1615 #gpio-cells = <2>; 1616 interrupt-controller; 1617 #interrupt-cells = <2>; 1618 reg = <0x0 0x400>; 1619 clocks = <&rcc GPIOA>; 1620 st,bank-name = "GPIOA"; 1621 status = "disabled"; 1622 }; 1623 1624 gpiob: gpio@50003000 { 1625 gpio-controller; 1626 #gpio-cells = <2>; 1627 interrupt-controller; 1628 #interrupt-cells = <2>; 1629 reg = <0x1000 0x400>; 1630 clocks = <&rcc GPIOB>; 1631 st,bank-name = "GPIOB"; 1632 status = "disabled"; 1633 }; 1634 1635 gpioc: gpio@50004000 { 1636 gpio-controller; 1637 #gpio-cells = <2>; 1638 interrupt-controller; 1639 #interrupt-cells = <2>; 1640 reg = <0x2000 0x400>; 1641 clocks = <&rcc GPIOC>; 1642 st,bank-name = "GPIOC"; 1643 status = "disabled"; 1644 }; 1645 1646 gpiod: gpio@50005000 { 1647 gpio-controller; 1648 #gpio-cells = <2>; 1649 interrupt-controller; 1650 #interrupt-cells = <2>; 1651 reg = <0x3000 0x400>; 1652 clocks = <&rcc GPIOD>; 1653 st,bank-name = "GPIOD"; 1654 status = "disabled"; 1655 }; 1656 1657 gpioe: gpio@50006000 { 1658 gpio-controller; 1659 #gpio-cells = <2>; 1660 interrupt-controller; 1661 #interrupt-cells = <2>; 1662 reg = <0x4000 0x400>; 1663 clocks = <&rcc GPIOE>; 1664 st,bank-name = "GPIOE"; 1665 status = "disabled"; 1666 }; 1667 1668 gpiof: gpio@50007000 { 1669 gpio-controller; 1670 #gpio-cells = <2>; 1671 interrupt-controller; 1672 #interrupt-cells = <2>; 1673 reg = <0x5000 0x400>; 1674 clocks = <&rcc GPIOF>; 1675 st,bank-name = "GPIOF"; 1676 status = "disabled"; 1677 }; 1678 1679 gpiog: gpio@50008000 { 1680 gpio-controller; 1681 #gpio-cells = <2>; 1682 interrupt-controller; 1683 #interrupt-cells = <2>; 1684 reg = <0x6000 0x400>; 1685 clocks = <&rcc GPIOG>; 1686 st,bank-name = "GPIOG"; 1687 status = "disabled"; 1688 }; 1689 1690 gpioh: gpio@50009000 { 1691 gpio-controller; 1692 #gpio-cells = <2>; 1693 interrupt-controller; 1694 #interrupt-cells = <2>; 1695 reg = <0x7000 0x400>; 1696 clocks = <&rcc GPIOH>; 1697 st,bank-name = "GPIOH"; 1698 status = "disabled"; 1699 }; 1700 1701 gpioi: gpio@5000a000 { 1702 gpio-controller; 1703 #gpio-cells = <2>; 1704 interrupt-controller; 1705 #interrupt-cells = <2>; 1706 reg = <0x8000 0x400>; 1707 clocks = <&rcc GPIOI>; 1708 st,bank-name = "GPIOI"; 1709 status = "disabled"; 1710 }; 1711 1712 gpioj: gpio@5000b000 { 1713 gpio-controller; 1714 #gpio-cells = <2>; 1715 interrupt-controller; 1716 #interrupt-cells = <2>; 1717 reg = <0x9000 0x400>; 1718 clocks = <&rcc GPIOJ>; 1719 st,bank-name = "GPIOJ"; 1720 status = "disabled"; 1721 }; 1722 1723 gpiok: gpio@5000c000 { 1724 gpio-controller; 1725 #gpio-cells = <2>; 1726 interrupt-controller; 1727 #interrupt-cells = <2>; 1728 reg = <0xa000 0x400>; 1729 clocks = <&rcc GPIOK>; 1730 st,bank-name = "GPIOK"; 1731 status = "disabled"; 1732 }; 1733 }; 1734 1735 pinctrl_z: pin-controller-z@54004000 { 1736 #address-cells = <1>; 1737 #size-cells = <1>; 1738 compatible = "st,stm32mp157-z-pinctrl"; 1739 ranges = <0 0x54004000 0x400>; 1740 pins-are-numbered; 1741 interrupt-parent = <&exti>; 1742 st,syscfg = <&exti 0x60 0xff>; 1743 1744 gpioz: gpio@54004000 { 1745 gpio-controller; 1746 #gpio-cells = <2>; 1747 interrupt-controller; 1748 #interrupt-cells = <2>; 1749 reg = <0 0x400>; 1750 clocks = <&rcc GPIOZ>; 1751 st,bank-name = "GPIOZ"; 1752 st,bank-ioport = <11>; 1753 status = "disabled"; 1754 }; 1755 }; 1756 }; 1757 1758 mlahb: ahb { 1759 compatible = "st,mlahb", "simple-bus"; 1760 #address-cells = <1>; 1761 #size-cells = <1>; 1762 ranges; 1763 dma-ranges = <0x00000000 0x38000000 0x10000>, 1764 <0x10000000 0x10000000 0x60000>, 1765 <0x30000000 0x30000000 0x60000>; 1766 1767 m4_rproc: m4@10000000 { 1768 compatible = "st,stm32mp1-m4"; 1769 reg = <0x10000000 0x40000>, 1770 <0x30000000 0x40000>, 1771 <0x38000000 0x10000>; 1772 resets = <&rcc MCU_R>; 1773 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1774 st,syscfg-tz = <&rcc 0x000 0x1>; 1775 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1776 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1777 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1778 status = "disabled"; 1779 }; 1780 }; 1781}; 1782