1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/memory.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER 23#include <mach/entry-macro.S> 24#endif 25#include <asm/thread_notify.h> 26#include <asm/unwind.h> 27#include <asm/unistd.h> 28#include <asm/tls.h> 29#include <asm/system_info.h> 30#include <asm/uaccess-asm.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34#include <asm/probes.h> 35 36/* 37 * Interrupt handling. 38 */ 39 .macro irq_handler 40#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 41 ldr r1, =handle_arch_irq 42 mov r0, sp 43 badr lr, 9997f 44 ldr pc, [r1] 45#else 46 arch_irq_handler_default 47#endif 489997: 49 .endm 50 51 .macro pabt_helper 52 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 53#ifdef MULTI_PABORT 54 ldr ip, .LCprocfns 55 mov lr, pc 56 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 57#else 58 bl CPU_PABORT_HANDLER 59#endif 60 .endm 61 62 .macro dabt_helper 63 64 @ 65 @ Call the processor-specific abort handler: 66 @ 67 @ r2 - pt_regs 68 @ r4 - aborted context pc 69 @ r5 - aborted context psr 70 @ 71 @ The abort handler must return the aborted address in r0, and 72 @ the fault status register in r1. r9 must be preserved. 73 @ 74#ifdef MULTI_DABORT 75 ldr ip, .LCprocfns 76 mov lr, pc 77 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 78#else 79 bl CPU_DABORT_HANDLER 80#endif 81 .endm 82 83 .section .entry.text,"ax",%progbits 84 85/* 86 * Invalid mode handlers 87 */ 88 .macro inv_entry, reason 89 sub sp, sp, #PT_REGS_SIZE 90 ARM( stmib sp, {r1 - lr} ) 91 THUMB( stmia sp, {r0 - r12} ) 92 THUMB( str sp, [sp, #S_SP] ) 93 THUMB( str lr, [sp, #S_LR] ) 94 mov r1, #\reason 95 .endm 96 97__pabt_invalid: 98 inv_entry BAD_PREFETCH 99 b common_invalid 100ENDPROC(__pabt_invalid) 101 102__dabt_invalid: 103 inv_entry BAD_DATA 104 b common_invalid 105ENDPROC(__dabt_invalid) 106 107__irq_invalid: 108 inv_entry BAD_IRQ 109 b common_invalid 110ENDPROC(__irq_invalid) 111 112__und_invalid: 113 inv_entry BAD_UNDEFINSTR 114 115 @ 116 @ XXX fall through to common_invalid 117 @ 118 119@ 120@ common_invalid - generic code for failed exception (re-entrant version of handlers) 121@ 122common_invalid: 123 zero_fp 124 125 ldmia r0, {r4 - r6} 126 add r0, sp, #S_PC @ here for interlock avoidance 127 mov r7, #-1 @ "" "" "" "" 128 str r4, [sp] @ save preserved r0 129 stmia r0, {r5 - r7} @ lr_<exception>, 130 @ cpsr_<exception>, "old_r0" 131 132 mov r0, sp 133 b bad_mode 134ENDPROC(__und_invalid) 135 136/* 137 * SVC mode handlers 138 */ 139 140#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 141#define SPFIX(code...) code 142#else 143#define SPFIX(code...) 144#endif 145 146 .macro svc_entry, stack_hole=0, trace=1, uaccess=1 147 UNWIND(.fnstart ) 148 UNWIND(.save {r0 - pc} ) 149 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 150#ifdef CONFIG_THUMB2_KERNEL 151 SPFIX( str r0, [sp] ) @ temporarily saved 152 SPFIX( mov r0, sp ) 153 SPFIX( tst r0, #4 ) @ test original stack alignment 154 SPFIX( ldr r0, [sp] ) @ restored 155#else 156 SPFIX( tst sp, #4 ) 157#endif 158 SPFIX( subeq sp, sp, #4 ) 159 stmia sp, {r1 - r12} 160 161 ldmia r0, {r3 - r5} 162 add r7, sp, #S_SP - 4 @ here for interlock avoidance 163 mov r6, #-1 @ "" "" "" "" 164 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) 165 SPFIX( addeq r2, r2, #4 ) 166 str r3, [sp, #-4]! @ save the "real" r0 copied 167 @ from the exception stack 168 169 mov r3, lr 170 171 @ 172 @ We are now ready to fill in the remaining blanks on the stack: 173 @ 174 @ r2 - sp_svc 175 @ r3 - lr_svc 176 @ r4 - lr_<exception>, already fixed up for correct return/restart 177 @ r5 - spsr_<exception> 178 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 179 @ 180 stmia r7, {r2 - r6} 181 182 get_thread_info tsk 183 uaccess_entry tsk, r0, r1, r2, \uaccess 184 185 .if \trace 186#ifdef CONFIG_TRACE_IRQFLAGS 187 bl trace_hardirqs_off 188#endif 189 .endif 190 .endm 191 192 .align 5 193__dabt_svc: 194 svc_entry uaccess=0 195 mov r2, sp 196 dabt_helper 197 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 198 svc_exit r5 @ return from exception 199 UNWIND(.fnend ) 200ENDPROC(__dabt_svc) 201 202 .align 5 203__irq_svc: 204 svc_entry 205 irq_handler 206 207#ifdef CONFIG_PREEMPTION 208 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 209 ldr r0, [tsk, #TI_FLAGS] @ get flags 210 teq r8, #0 @ if preempt count != 0 211 movne r0, #0 @ force flags to 0 212 tst r0, #_TIF_NEED_RESCHED 213 blne svc_preempt 214#endif 215 216 svc_exit r5, irq = 1 @ return from exception 217 UNWIND(.fnend ) 218ENDPROC(__irq_svc) 219 220 .ltorg 221 222#ifdef CONFIG_PREEMPTION 223svc_preempt: 224 mov r8, lr 2251: bl preempt_schedule_irq @ irq en/disable is done inside 226 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 227 tst r0, #_TIF_NEED_RESCHED 228 reteq r8 @ go again 229 b 1b 230#endif 231 232__und_fault: 233 @ Correct the PC such that it is pointing at the instruction 234 @ which caused the fault. If the faulting instruction was ARM 235 @ the PC will be pointing at the next instruction, and have to 236 @ subtract 4. Otherwise, it is Thumb, and the PC will be 237 @ pointing at the second half of the Thumb instruction. We 238 @ have to subtract 2. 239 ldr r2, [r0, #S_PC] 240 sub r2, r2, r1 241 str r2, [r0, #S_PC] 242 b do_undefinstr 243ENDPROC(__und_fault) 244 245 .align 5 246__und_svc: 247#ifdef CONFIG_KPROBES 248 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 249 @ it obviously needs free stack space which then will belong to 250 @ the saved context. 251 svc_entry MAX_STACK_SIZE 252#else 253 svc_entry 254#endif 255 256 mov r1, #4 @ PC correction to apply 257 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 258 THUMB( movne r1, #2 ) @ if so, fix up PC correction 259 mov r0, sp @ struct pt_regs *regs 260 bl __und_fault 261 262__und_svc_finish: 263 get_thread_info tsk 264 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 265 svc_exit r5 @ return from exception 266 UNWIND(.fnend ) 267ENDPROC(__und_svc) 268 269 .align 5 270__pabt_svc: 271 svc_entry 272 mov r2, sp @ regs 273 pabt_helper 274 svc_exit r5 @ return from exception 275 UNWIND(.fnend ) 276ENDPROC(__pabt_svc) 277 278 .align 5 279__fiq_svc: 280 svc_entry trace=0 281 mov r0, sp @ struct pt_regs *regs 282 bl handle_fiq_as_nmi 283 svc_exit_via_fiq 284 UNWIND(.fnend ) 285ENDPROC(__fiq_svc) 286 287 .align 5 288.LCcralign: 289 .word cr_alignment 290#ifdef MULTI_DABORT 291.LCprocfns: 292 .word processor 293#endif 294.LCfp: 295 .word fp_enter 296 297/* 298 * Abort mode handlers 299 */ 300 301@ 302@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 303@ and reuses the same macros. However in abort mode we must also 304@ save/restore lr_abt and spsr_abt to make nested aborts safe. 305@ 306 .align 5 307__fiq_abt: 308 svc_entry trace=0 309 310 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 311 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 312 THUMB( msr cpsr_c, r0 ) 313 mov r1, lr @ Save lr_abt 314 mrs r2, spsr @ Save spsr_abt, abort is now safe 315 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 316 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 317 THUMB( msr cpsr_c, r0 ) 318 stmfd sp!, {r1 - r2} 319 320 add r0, sp, #8 @ struct pt_regs *regs 321 bl handle_fiq_as_nmi 322 323 ldmfd sp!, {r1 - r2} 324 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 325 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 326 THUMB( msr cpsr_c, r0 ) 327 mov lr, r1 @ Restore lr_abt, abort is unsafe 328 msr spsr_cxsf, r2 @ Restore spsr_abt 329 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 330 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 331 THUMB( msr cpsr_c, r0 ) 332 333 svc_exit_via_fiq 334 UNWIND(.fnend ) 335ENDPROC(__fiq_abt) 336 337/* 338 * User mode handlers 339 * 340 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 341 */ 342 343#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 344#error "sizeof(struct pt_regs) must be a multiple of 8" 345#endif 346 347 .macro usr_entry, trace=1, uaccess=1 348 UNWIND(.fnstart ) 349 UNWIND(.cantunwind ) @ don't unwind the user space 350 sub sp, sp, #PT_REGS_SIZE 351 ARM( stmib sp, {r1 - r12} ) 352 THUMB( stmia sp, {r0 - r12} ) 353 354 ATRAP( mrc p15, 0, r7, c1, c0, 0) 355 ATRAP( ldr r8, .LCcralign) 356 357 ldmia r0, {r3 - r5} 358 add r0, sp, #S_PC @ here for interlock avoidance 359 mov r6, #-1 @ "" "" "" "" 360 361 str r3, [sp] @ save the "real" r0 copied 362 @ from the exception stack 363 364 ATRAP( ldr r8, [r8, #0]) 365 366 @ 367 @ We are now ready to fill in the remaining blanks on the stack: 368 @ 369 @ r4 - lr_<exception>, already fixed up for correct return/restart 370 @ r5 - spsr_<exception> 371 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 372 @ 373 @ Also, separately save sp_usr and lr_usr 374 @ 375 stmia r0, {r4 - r6} 376 ARM( stmdb r0, {sp, lr}^ ) 377 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 378 379 .if \uaccess 380 uaccess_disable ip 381 .endif 382 383 @ Enable the alignment trap while in kernel mode 384 ATRAP( teq r8, r7) 385 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 386 387 @ 388 @ Clear FP to mark the first stack frame 389 @ 390 zero_fp 391 392 .if \trace 393#ifdef CONFIG_TRACE_IRQFLAGS 394 bl trace_hardirqs_off 395#endif 396 ct_user_exit save = 0 397 .endif 398 .endm 399 400 .macro kuser_cmpxchg_check 401#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 402#ifndef CONFIG_MMU 403#warning "NPTL on non MMU needs fixing" 404#else 405 @ Make sure our user space atomic helper is restarted 406 @ if it was interrupted in a critical region. Here we 407 @ perform a quick test inline since it should be false 408 @ 99.9999% of the time. The rest is done out of line. 409 ldr r0, =TASK_SIZE 410 cmp r4, r0 411 blhs kuser_cmpxchg64_fixup 412#endif 413#endif 414 .endm 415 416 .align 5 417__dabt_usr: 418 usr_entry uaccess=0 419 kuser_cmpxchg_check 420 mov r2, sp 421 dabt_helper 422 b ret_from_exception 423 UNWIND(.fnend ) 424ENDPROC(__dabt_usr) 425 426 .align 5 427__irq_usr: 428 usr_entry 429 kuser_cmpxchg_check 430 irq_handler 431 get_thread_info tsk 432 mov why, #0 433 b ret_to_user_from_irq 434 UNWIND(.fnend ) 435ENDPROC(__irq_usr) 436 437 .ltorg 438 439 .align 5 440__und_usr: 441 usr_entry uaccess=0 442 443 mov r2, r4 444 mov r3, r5 445 446 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 447 @ faulting instruction depending on Thumb mode. 448 @ r3 = regs->ARM_cpsr 449 @ 450 @ The emulation code returns using r9 if it has emulated the 451 @ instruction, or the more conventional lr if we are to treat 452 @ this as a real undefined instruction 453 @ 454 badr r9, ret_from_exception 455 456 @ IRQs must be enabled before attempting to read the instruction from 457 @ user space since that could cause a page/translation fault if the 458 @ page table was modified by another CPU. 459 enable_irq 460 461 tst r3, #PSR_T_BIT @ Thumb mode? 462 bne __und_usr_thumb 463 sub r4, r2, #4 @ ARM instr at LR - 4 4641: ldrt r0, [r4] 465 ARM_BE8(rev r0, r0) @ little endian instruction 466 467 uaccess_disable ip 468 469 @ r0 = 32-bit ARM instruction which caused the exception 470 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 471 @ r4 = PC value for the faulting instruction 472 @ lr = 32-bit undefined instruction function 473 badr lr, __und_usr_fault_32 474 b call_fpe 475 476__und_usr_thumb: 477 @ Thumb instruction 478 sub r4, r2, #2 @ First half of thumb instr at LR - 2 479#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 480/* 481 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 482 * can never be supported in a single kernel, this code is not applicable at 483 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 484 * made about .arch directives. 485 */ 486#if __LINUX_ARM_ARCH__ < 7 487/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 488#define NEED_CPU_ARCHITECTURE 489 ldr r5, .LCcpu_architecture 490 ldr r5, [r5] 491 cmp r5, #CPU_ARCH_ARMv7 492 blo __und_usr_fault_16 @ 16bit undefined instruction 493/* 494 * The following code won't get run unless the running CPU really is v7, so 495 * coding round the lack of ldrht on older arches is pointless. Temporarily 496 * override the assembler target arch with the minimum required instead: 497 */ 498 .arch armv6t2 499#endif 5002: ldrht r5, [r4] 501ARM_BE8(rev16 r5, r5) @ little endian instruction 502 cmp r5, #0xe800 @ 32bit instruction if xx != 0 503 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5043: ldrht r0, [r2] 505ARM_BE8(rev16 r0, r0) @ little endian instruction 506 uaccess_disable ip 507 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 508 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 509 orr r0, r0, r5, lsl #16 510 badr lr, __und_usr_fault_32 511 @ r0 = the two 16-bit Thumb instructions which caused the exception 512 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 513 @ r4 = PC value for the first 16-bit Thumb instruction 514 @ lr = 32bit undefined instruction function 515 516#if __LINUX_ARM_ARCH__ < 7 517/* If the target arch was overridden, change it back: */ 518#ifdef CONFIG_CPU_32v6K 519 .arch armv6k 520#else 521 .arch armv6 522#endif 523#endif /* __LINUX_ARM_ARCH__ < 7 */ 524#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 525 b __und_usr_fault_16 526#endif 527 UNWIND(.fnend) 528ENDPROC(__und_usr) 529 530/* 531 * The out of line fixup for the ldrt instructions above. 532 */ 533 .pushsection .text.fixup, "ax" 534 .align 2 5354: str r4, [sp, #S_PC] @ retry current instruction 536 ret r9 537 .popsection 538 .pushsection __ex_table,"a" 539 .long 1b, 4b 540#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 541 .long 2b, 4b 542 .long 3b, 4b 543#endif 544 .popsection 545 546/* 547 * Check whether the instruction is a co-processor instruction. 548 * If yes, we need to call the relevant co-processor handler. 549 * 550 * Note that we don't do a full check here for the co-processor 551 * instructions; all instructions with bit 27 set are well 552 * defined. The only instructions that should fault are the 553 * co-processor instructions. However, we have to watch out 554 * for the ARM6/ARM7 SWI bug. 555 * 556 * NEON is a special case that has to be handled here. Not all 557 * NEON instructions are co-processor instructions, so we have 558 * to make a special case of checking for them. Plus, there's 559 * five groups of them, so we have a table of mask/opcode pairs 560 * to check against, and if any match then we branch off into the 561 * NEON handler code. 562 * 563 * Emulators may wish to make use of the following registers: 564 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 565 * r2 = PC value to resume execution after successful emulation 566 * r9 = normal "successful" return address 567 * r10 = this threads thread_info structure 568 * lr = unrecognised instruction return address 569 * IRQs enabled, FIQs enabled. 570 */ 571 @ 572 @ Fall-through from Thumb-2 __und_usr 573 @ 574#ifdef CONFIG_NEON 575 get_thread_info r10 @ get current thread 576 adr r6, .LCneon_thumb_opcodes 577 b 2f 578#endif 579call_fpe: 580 get_thread_info r10 @ get current thread 581#ifdef CONFIG_NEON 582 adr r6, .LCneon_arm_opcodes 5832: ldr r5, [r6], #4 @ mask value 584 ldr r7, [r6], #4 @ opcode bits matching in mask 585 cmp r5, #0 @ end mask? 586 beq 1f 587 and r8, r0, r5 588 cmp r8, r7 @ NEON instruction? 589 bne 2b 590 mov r7, #1 591 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 592 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 593 b do_vfp @ let VFP handler handle this 5941: 595#endif 596 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 597 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 598 reteq lr 599 and r8, r0, #0x00000f00 @ mask out CP number 600 mov r7, #1 601 add r6, r10, r8, lsr #8 @ add used_cp[] array offset first 602 strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[] 603#ifdef CONFIG_IWMMXT 604 @ Test if we need to give access to iWMMXt coprocessors 605 ldr r5, [r10, #TI_FLAGS] 606 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 607 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 608 bcs iwmmxt_task_enable 609#endif 610 ARM( add pc, pc, r8, lsr #6 ) 611 THUMB( lsr r8, r8, #6 ) 612 THUMB( add pc, r8 ) 613 nop 614 615 ret.w lr @ CP#0 616 W(b) do_fpe @ CP#1 (FPE) 617 W(b) do_fpe @ CP#2 (FPE) 618 ret.w lr @ CP#3 619 ret.w lr @ CP#4 620 ret.w lr @ CP#5 621 ret.w lr @ CP#6 622 ret.w lr @ CP#7 623 ret.w lr @ CP#8 624 ret.w lr @ CP#9 625#ifdef CONFIG_VFP 626 W(b) do_vfp @ CP#10 (VFP) 627 W(b) do_vfp @ CP#11 (VFP) 628#else 629 ret.w lr @ CP#10 (VFP) 630 ret.w lr @ CP#11 (VFP) 631#endif 632 ret.w lr @ CP#12 633 ret.w lr @ CP#13 634 ret.w lr @ CP#14 (Debug) 635 ret.w lr @ CP#15 (Control) 636 637#ifdef NEED_CPU_ARCHITECTURE 638 .align 2 639.LCcpu_architecture: 640 .word __cpu_architecture 641#endif 642 643#ifdef CONFIG_NEON 644 .align 6 645 646.LCneon_arm_opcodes: 647 .word 0xfe000000 @ mask 648 .word 0xf2000000 @ opcode 649 650 .word 0xff100000 @ mask 651 .word 0xf4000000 @ opcode 652 653 .word 0x00000000 @ mask 654 .word 0x00000000 @ opcode 655 656.LCneon_thumb_opcodes: 657 .word 0xef000000 @ mask 658 .word 0xef000000 @ opcode 659 660 .word 0xff100000 @ mask 661 .word 0xf9000000 @ opcode 662 663 .word 0x00000000 @ mask 664 .word 0x00000000 @ opcode 665#endif 666 667do_fpe: 668 ldr r4, .LCfp 669 add r10, r10, #TI_FPSTATE @ r10 = workspace 670 ldr pc, [r4] @ Call FP module USR entry point 671 672/* 673 * The FP module is called with these registers set: 674 * r0 = instruction 675 * r2 = PC+4 676 * r9 = normal "successful" return address 677 * r10 = FP workspace 678 * lr = unrecognised FP instruction return address 679 */ 680 681 .pushsection .data 682 .align 2 683ENTRY(fp_enter) 684 .word no_fp 685 .popsection 686 687ENTRY(no_fp) 688 ret lr 689ENDPROC(no_fp) 690 691__und_usr_fault_32: 692 mov r1, #4 693 b 1f 694__und_usr_fault_16_pan: 695 uaccess_disable ip 696__und_usr_fault_16: 697 mov r1, #2 6981: mov r0, sp 699 badr lr, ret_from_exception 700 b __und_fault 701ENDPROC(__und_usr_fault_32) 702ENDPROC(__und_usr_fault_16) 703 704 .align 5 705__pabt_usr: 706 usr_entry 707 mov r2, sp @ regs 708 pabt_helper 709 UNWIND(.fnend ) 710 /* fall through */ 711/* 712 * This is the return code to user mode for abort handlers 713 */ 714ENTRY(ret_from_exception) 715 UNWIND(.fnstart ) 716 UNWIND(.cantunwind ) 717 get_thread_info tsk 718 mov why, #0 719 b ret_to_user 720 UNWIND(.fnend ) 721ENDPROC(__pabt_usr) 722ENDPROC(ret_from_exception) 723 724 .align 5 725__fiq_usr: 726 usr_entry trace=0 727 kuser_cmpxchg_check 728 mov r0, sp @ struct pt_regs *regs 729 bl handle_fiq_as_nmi 730 get_thread_info tsk 731 restore_user_regs fast = 0, offset = 0 732 UNWIND(.fnend ) 733ENDPROC(__fiq_usr) 734 735/* 736 * Register switch for ARMv3 and ARMv4 processors 737 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 738 * previous and next are guaranteed not to be the same. 739 */ 740ENTRY(__switch_to) 741 UNWIND(.fnstart ) 742 UNWIND(.cantunwind ) 743 add ip, r1, #TI_CPU_SAVE 744 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 745 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 746 THUMB( str sp, [ip], #4 ) 747 THUMB( str lr, [ip], #4 ) 748 ldr r4, [r2, #TI_TP_VALUE] 749 ldr r5, [r2, #TI_TP_VALUE + 4] 750#ifdef CONFIG_CPU_USE_DOMAINS 751 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 752 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 753 ldr r6, [r2, #TI_CPU_DOMAIN] 754#endif 755 switch_tls r1, r4, r5, r3, r7 756#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 757 ldr r7, [r2, #TI_TASK] 758 ldr r8, =__stack_chk_guard 759 .if (TSK_STACK_CANARY > IMM12_MASK) 760 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK 761 .endif 762 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] 763#endif 764#ifdef CONFIG_CPU_USE_DOMAINS 765 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 766#endif 767 mov r5, r0 768 add r4, r2, #TI_CPU_SAVE 769 ldr r0, =thread_notify_head 770 mov r1, #THREAD_NOTIFY_SWITCH 771 bl atomic_notifier_call_chain 772#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 773 str r7, [r8] 774#endif 775 THUMB( mov ip, r4 ) 776 mov r0, r5 777 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 778 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 779 THUMB( ldr sp, [ip], #4 ) 780 THUMB( ldr pc, [ip] ) 781 UNWIND(.fnend ) 782ENDPROC(__switch_to) 783 784 __INIT 785 786/* 787 * User helpers. 788 * 789 * Each segment is 32-byte aligned and will be moved to the top of the high 790 * vector page. New segments (if ever needed) must be added in front of 791 * existing ones. This mechanism should be used only for things that are 792 * really small and justified, and not be abused freely. 793 * 794 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 795 */ 796 THUMB( .arm ) 797 798 .macro usr_ret, reg 799#ifdef CONFIG_ARM_THUMB 800 bx \reg 801#else 802 ret \reg 803#endif 804 .endm 805 806 .macro kuser_pad, sym, size 807 .if (. - \sym) & 3 808 .rept 4 - (. - \sym) & 3 809 .byte 0 810 .endr 811 .endif 812 .rept (\size - (. - \sym)) / 4 813 .word 0xe7fddef1 814 .endr 815 .endm 816 817#ifdef CONFIG_KUSER_HELPERS 818 .align 5 819 .globl __kuser_helper_start 820__kuser_helper_start: 821 822/* 823 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 824 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 825 */ 826 827__kuser_cmpxchg64: @ 0xffff0f60 828 829#if defined(CONFIG_CPU_32v6K) 830 831 stmfd sp!, {r4, r5, r6, r7} 832 ldrd r4, r5, [r0] @ load old val 833 ldrd r6, r7, [r1] @ load new val 834 smp_dmb arm 8351: ldrexd r0, r1, [r2] @ load current val 836 eors r3, r0, r4 @ compare with oldval (1) 837 eorseq r3, r1, r5 @ compare with oldval (2) 838 strexdeq r3, r6, r7, [r2] @ store newval if eq 839 teqeq r3, #1 @ success? 840 beq 1b @ if no then retry 841 smp_dmb arm 842 rsbs r0, r3, #0 @ set returned val and C flag 843 ldmfd sp!, {r4, r5, r6, r7} 844 usr_ret lr 845 846#elif !defined(CONFIG_SMP) 847 848#ifdef CONFIG_MMU 849 850 /* 851 * The only thing that can break atomicity in this cmpxchg64 852 * implementation is either an IRQ or a data abort exception 853 * causing another process/thread to be scheduled in the middle of 854 * the critical sequence. The same strategy as for cmpxchg is used. 855 */ 856 stmfd sp!, {r4, r5, r6, lr} 857 ldmia r0, {r4, r5} @ load old val 858 ldmia r1, {r6, lr} @ load new val 8591: ldmia r2, {r0, r1} @ load current val 860 eors r3, r0, r4 @ compare with oldval (1) 861 eorseq r3, r1, r5 @ compare with oldval (2) 8622: stmiaeq r2, {r6, lr} @ store newval if eq 863 rsbs r0, r3, #0 @ set return val and C flag 864 ldmfd sp!, {r4, r5, r6, pc} 865 866 .text 867kuser_cmpxchg64_fixup: 868 @ Called from kuser_cmpxchg_fixup. 869 @ r4 = address of interrupted insn (must be preserved). 870 @ sp = saved regs. r7 and r8 are clobbered. 871 @ 1b = first critical insn, 2b = last critical insn. 872 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 873 mov r7, #0xffff0fff 874 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 875 subs r8, r4, r7 876 rsbscs r8, r8, #(2b - 1b) 877 strcs r7, [sp, #S_PC] 878#if __LINUX_ARM_ARCH__ < 6 879 bcc kuser_cmpxchg32_fixup 880#endif 881 ret lr 882 .previous 883 884#else 885#warning "NPTL on non MMU needs fixing" 886 mov r0, #-1 887 adds r0, r0, #0 888 usr_ret lr 889#endif 890 891#else 892#error "incoherent kernel configuration" 893#endif 894 895 kuser_pad __kuser_cmpxchg64, 64 896 897__kuser_memory_barrier: @ 0xffff0fa0 898 smp_dmb arm 899 usr_ret lr 900 901 kuser_pad __kuser_memory_barrier, 32 902 903__kuser_cmpxchg: @ 0xffff0fc0 904 905#if __LINUX_ARM_ARCH__ < 6 906 907#ifdef CONFIG_MMU 908 909 /* 910 * The only thing that can break atomicity in this cmpxchg 911 * implementation is either an IRQ or a data abort exception 912 * causing another process/thread to be scheduled in the middle 913 * of the critical sequence. To prevent this, code is added to 914 * the IRQ and data abort exception handlers to set the pc back 915 * to the beginning of the critical section if it is found to be 916 * within that critical section (see kuser_cmpxchg_fixup). 917 */ 9181: ldr r3, [r2] @ load current val 919 subs r3, r3, r0 @ compare with oldval 9202: streq r1, [r2] @ store newval if eq 921 rsbs r0, r3, #0 @ set return val and C flag 922 usr_ret lr 923 924 .text 925kuser_cmpxchg32_fixup: 926 @ Called from kuser_cmpxchg_check macro. 927 @ r4 = address of interrupted insn (must be preserved). 928 @ sp = saved regs. r7 and r8 are clobbered. 929 @ 1b = first critical insn, 2b = last critical insn. 930 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 931 mov r7, #0xffff0fff 932 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 933 subs r8, r4, r7 934 rsbscs r8, r8, #(2b - 1b) 935 strcs r7, [sp, #S_PC] 936 ret lr 937 .previous 938 939#else 940#warning "NPTL on non MMU needs fixing" 941 mov r0, #-1 942 adds r0, r0, #0 943 usr_ret lr 944#endif 945 946#else 947 948 smp_dmb arm 9491: ldrex r3, [r2] 950 subs r3, r3, r0 951 strexeq r3, r1, [r2] 952 teqeq r3, #1 953 beq 1b 954 rsbs r0, r3, #0 955 /* beware -- each __kuser slot must be 8 instructions max */ 956 ALT_SMP(b __kuser_memory_barrier) 957 ALT_UP(usr_ret lr) 958 959#endif 960 961 kuser_pad __kuser_cmpxchg, 32 962 963__kuser_get_tls: @ 0xffff0fe0 964 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 965 usr_ret lr 966 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 967 kuser_pad __kuser_get_tls, 16 968 .rep 3 969 .word 0 @ 0xffff0ff0 software TLS value, then 970 .endr @ pad up to __kuser_helper_version 971 972__kuser_helper_version: @ 0xffff0ffc 973 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 974 975 .globl __kuser_helper_end 976__kuser_helper_end: 977 978#endif 979 980 THUMB( .thumb ) 981 982/* 983 * Vector stubs. 984 * 985 * This code is copied to 0xffff1000 so we can use branches in the 986 * vectors, rather than ldr's. Note that this code must not exceed 987 * a page size. 988 * 989 * Common stub entry macro: 990 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 991 * 992 * SP points to a minimal amount of processor-private memory, the address 993 * of which is copied into r0 for the mode specific abort handler. 994 */ 995 .macro vector_stub, name, mode, correction=0 996 .align 5 997 998vector_\name: 999 .if \correction 1000 sub lr, lr, #\correction 1001 .endif 1002 1003 @ Save r0, lr_<exception> (parent PC) 1004 stmia sp, {r0, lr} @ save r0, lr 1005 1006 @ Save spsr_<exception> (parent CPSR) 10072: mrs lr, spsr 1008 str lr, [sp, #8] @ save spsr 1009 1010 @ 1011 @ Prepare for SVC32 mode. IRQs remain disabled. 1012 @ 1013 mrs r0, cpsr 1014 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1015 msr spsr_cxsf, r0 1016 1017 @ 1018 @ the branch table must immediately follow this code 1019 @ 1020 and lr, lr, #0x0f 1021 THUMB( adr r0, 1f ) 1022 THUMB( ldr lr, [r0, lr, lsl #2] ) 1023 mov r0, sp 1024 ARM( ldr lr, [pc, lr, lsl #2] ) 1025 movs pc, lr @ branch to handler in SVC mode 1026ENDPROC(vector_\name) 1027 1028#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1029 .subsection 1 1030 .align 5 1031vector_bhb_loop8_\name: 1032 .if \correction 1033 sub lr, lr, #\correction 1034 .endif 1035 1036 @ Save r0, lr_<exception> (parent PC) 1037 stmia sp, {r0, lr} 1038 1039 @ bhb workaround 1040 mov r0, #8 10413: W(b) . + 4 1042 subs r0, r0, #1 1043 bne 3b 1044 dsb 1045 isb 1046 b 2b 1047ENDPROC(vector_bhb_loop8_\name) 1048 1049vector_bhb_bpiall_\name: 1050 .if \correction 1051 sub lr, lr, #\correction 1052 .endif 1053 1054 @ Save r0, lr_<exception> (parent PC) 1055 stmia sp, {r0, lr} 1056 1057 @ bhb workaround 1058 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 1059 @ isb not needed due to "movs pc, lr" in the vector stub 1060 @ which gives a "context synchronisation". 1061 b 2b 1062ENDPROC(vector_bhb_bpiall_\name) 1063 .previous 1064#endif 1065 1066 .align 2 1067 @ handler addresses follow this label 10681: 1069 .endm 1070 1071 .section .stubs, "ax", %progbits 1072 @ This must be the first word 1073 .word vector_swi 1074#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1075 .word vector_bhb_loop8_swi 1076 .word vector_bhb_bpiall_swi 1077#endif 1078 1079vector_rst: 1080 ARM( swi SYS_ERROR0 ) 1081 THUMB( svc #0 ) 1082 THUMB( nop ) 1083 b vector_und 1084 1085/* 1086 * Interrupt dispatcher 1087 */ 1088 vector_stub irq, IRQ_MODE, 4 1089 1090 .long __irq_usr @ 0 (USR_26 / USR_32) 1091 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1092 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1093 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1094 .long __irq_invalid @ 4 1095 .long __irq_invalid @ 5 1096 .long __irq_invalid @ 6 1097 .long __irq_invalid @ 7 1098 .long __irq_invalid @ 8 1099 .long __irq_invalid @ 9 1100 .long __irq_invalid @ a 1101 .long __irq_invalid @ b 1102 .long __irq_invalid @ c 1103 .long __irq_invalid @ d 1104 .long __irq_invalid @ e 1105 .long __irq_invalid @ f 1106 1107/* 1108 * Data abort dispatcher 1109 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1110 */ 1111 vector_stub dabt, ABT_MODE, 8 1112 1113 .long __dabt_usr @ 0 (USR_26 / USR_32) 1114 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1115 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1116 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1117 .long __dabt_invalid @ 4 1118 .long __dabt_invalid @ 5 1119 .long __dabt_invalid @ 6 1120 .long __dabt_invalid @ 7 1121 .long __dabt_invalid @ 8 1122 .long __dabt_invalid @ 9 1123 .long __dabt_invalid @ a 1124 .long __dabt_invalid @ b 1125 .long __dabt_invalid @ c 1126 .long __dabt_invalid @ d 1127 .long __dabt_invalid @ e 1128 .long __dabt_invalid @ f 1129 1130/* 1131 * Prefetch abort dispatcher 1132 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1133 */ 1134 vector_stub pabt, ABT_MODE, 4 1135 1136 .long __pabt_usr @ 0 (USR_26 / USR_32) 1137 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1138 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1139 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1140 .long __pabt_invalid @ 4 1141 .long __pabt_invalid @ 5 1142 .long __pabt_invalid @ 6 1143 .long __pabt_invalid @ 7 1144 .long __pabt_invalid @ 8 1145 .long __pabt_invalid @ 9 1146 .long __pabt_invalid @ a 1147 .long __pabt_invalid @ b 1148 .long __pabt_invalid @ c 1149 .long __pabt_invalid @ d 1150 .long __pabt_invalid @ e 1151 .long __pabt_invalid @ f 1152 1153/* 1154 * Undef instr entry dispatcher 1155 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1156 */ 1157 vector_stub und, UND_MODE 1158 1159 .long __und_usr @ 0 (USR_26 / USR_32) 1160 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1161 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1162 .long __und_svc @ 3 (SVC_26 / SVC_32) 1163 .long __und_invalid @ 4 1164 .long __und_invalid @ 5 1165 .long __und_invalid @ 6 1166 .long __und_invalid @ 7 1167 .long __und_invalid @ 8 1168 .long __und_invalid @ 9 1169 .long __und_invalid @ a 1170 .long __und_invalid @ b 1171 .long __und_invalid @ c 1172 .long __und_invalid @ d 1173 .long __und_invalid @ e 1174 .long __und_invalid @ f 1175 1176 .align 5 1177 1178/*============================================================================= 1179 * Address exception handler 1180 *----------------------------------------------------------------------------- 1181 * These aren't too critical. 1182 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1183 */ 1184 1185vector_addrexcptn: 1186 b vector_addrexcptn 1187 1188/*============================================================================= 1189 * FIQ "NMI" handler 1190 *----------------------------------------------------------------------------- 1191 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1192 * systems. This must be the last vector stub, so lets place it in its own 1193 * subsection. 1194 */ 1195 .subsection 2 1196 vector_stub fiq, FIQ_MODE, 4 1197 1198 .long __fiq_usr @ 0 (USR_26 / USR_32) 1199 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1200 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1201 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1202 .long __fiq_svc @ 4 1203 .long __fiq_svc @ 5 1204 .long __fiq_svc @ 6 1205 .long __fiq_abt @ 7 1206 .long __fiq_svc @ 8 1207 .long __fiq_svc @ 9 1208 .long __fiq_svc @ a 1209 .long __fiq_svc @ b 1210 .long __fiq_svc @ c 1211 .long __fiq_svc @ d 1212 .long __fiq_svc @ e 1213 .long __fiq_svc @ f 1214 1215 .globl vector_fiq 1216 1217 .section .vectors, "ax", %progbits 1218.L__vectors_start: 1219 W(b) vector_rst 1220 W(b) vector_und 1221 W(ldr) pc, .L__vectors_start + 0x1000 1222 W(b) vector_pabt 1223 W(b) vector_dabt 1224 W(b) vector_addrexcptn 1225 W(b) vector_irq 1226 W(b) vector_fiq 1227 1228#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1229 .section .vectors.bhb.loop8, "ax", %progbits 1230.L__vectors_bhb_loop8_start: 1231 W(b) vector_rst 1232 W(b) vector_bhb_loop8_und 1233 W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 1234 W(b) vector_bhb_loop8_pabt 1235 W(b) vector_bhb_loop8_dabt 1236 W(b) vector_addrexcptn 1237 W(b) vector_bhb_loop8_irq 1238 W(b) vector_bhb_loop8_fiq 1239 1240 .section .vectors.bhb.bpiall, "ax", %progbits 1241.L__vectors_bhb_bpiall_start: 1242 W(b) vector_rst 1243 W(b) vector_bhb_bpiall_und 1244 W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 1245 W(b) vector_bhb_bpiall_pabt 1246 W(b) vector_bhb_bpiall_dabt 1247 W(b) vector_addrexcptn 1248 W(b) vector_bhb_bpiall_irq 1249 W(b) vector_bhb_bpiall_fiq 1250#endif 1251 1252 .data 1253 .align 2 1254 1255 .globl cr_alignment 1256cr_alignment: 1257 .space 4 1258