1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * arch/arm/mach-dove/pcie.c
4 *
5 * PCIe functions for Marvell Dove 88AP510 SoC
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/clk.h>
11 #include <video/vga.h>
12 #include <asm/mach/pci.h>
13 #include <asm/mach/arch.h>
14 #include <asm/setup.h>
15 #include <asm/delay.h>
16 #include <plat/pcie.h>
17 #include <plat/addr-map.h>
18 #include "irqs.h"
19 #include "bridge-regs.h"
20 #include "common.h"
21
22 struct pcie_port {
23 u8 index;
24 u8 root_bus_nr;
25 void __iomem *base;
26 spinlock_t conf_lock;
27 char mem_space_name[16];
28 struct resource res;
29 };
30
31 static struct pcie_port pcie_port[2];
32 static int num_pcie_ports;
33
34
dove_pcie_setup(int nr,struct pci_sys_data * sys)35 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
36 {
37 struct pcie_port *pp;
38
39 if (nr >= num_pcie_ports)
40 return 0;
41
42 pp = &pcie_port[nr];
43 sys->private_data = pp;
44 pp->root_bus_nr = sys->busnr;
45
46 /*
47 * Generic PCIe unit setup.
48 */
49 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
50
51 orion_pcie_setup(pp->base);
52
53 if (pp->index == 0)
54 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
55 else
56 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
57
58 /*
59 * IORESOURCE_MEM
60 */
61 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
62 "PCIe %d MEM", pp->index);
63 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
64 pp->res.name = pp->mem_space_name;
65 if (pp->index == 0) {
66 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
67 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
68 } else {
69 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
70 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
71 }
72 pp->res.flags = IORESOURCE_MEM;
73 if (request_resource(&iomem_resource, &pp->res))
74 panic("Request PCIe Memory resource failed\n");
75 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
76
77 return 1;
78 }
79
pcie_valid_config(struct pcie_port * pp,int bus,int dev)80 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
81 {
82 /*
83 * Don't go out when trying to access nonexisting devices
84 * on the local bus.
85 */
86 if (bus == pp->root_bus_nr && dev > 1)
87 return 0;
88
89 return 1;
90 }
91
pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)92 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
93 int size, u32 *val)
94 {
95 struct pci_sys_data *sys = bus->sysdata;
96 struct pcie_port *pp = sys->private_data;
97 unsigned long flags;
98 int ret;
99
100 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
101 *val = 0xffffffff;
102 return PCIBIOS_DEVICE_NOT_FOUND;
103 }
104
105 spin_lock_irqsave(&pp->conf_lock, flags);
106 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
107 spin_unlock_irqrestore(&pp->conf_lock, flags);
108
109 return ret;
110 }
111
pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)112 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
113 int where, int size, u32 val)
114 {
115 struct pci_sys_data *sys = bus->sysdata;
116 struct pcie_port *pp = sys->private_data;
117 unsigned long flags;
118 int ret;
119
120 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
121 return PCIBIOS_DEVICE_NOT_FOUND;
122
123 spin_lock_irqsave(&pp->conf_lock, flags);
124 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
125 spin_unlock_irqrestore(&pp->conf_lock, flags);
126
127 return ret;
128 }
129
130 static struct pci_ops pcie_ops = {
131 .read = pcie_rd_conf,
132 .write = pcie_wr_conf,
133 };
134
rc_pci_fixup(struct pci_dev * dev)135 static void rc_pci_fixup(struct pci_dev *dev)
136 {
137 /*
138 * Prevent enumeration of root complex.
139 */
140 if (dev->bus->parent == NULL && dev->devfn == 0) {
141 int i;
142
143 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
144 dev->resource[i].start = 0;
145 dev->resource[i].end = 0;
146 dev->resource[i].flags = 0;
147 }
148 }
149 }
150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
151
152 static int __init
dove_pcie_scan_bus(int nr,struct pci_host_bridge * bridge)153 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
154 {
155 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
156
157 if (nr >= num_pcie_ports) {
158 BUG();
159 return -EINVAL;
160 }
161
162 list_splice_init(&sys->resources, &bridge->windows);
163 bridge->dev.parent = NULL;
164 bridge->sysdata = sys;
165 bridge->busnr = sys->busnr;
166 bridge->ops = &pcie_ops;
167
168 return pci_scan_root_bus_bridge(bridge);
169 }
170
dove_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)171 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
172 {
173 struct pci_sys_data *sys = dev->sysdata;
174 struct pcie_port *pp = sys->private_data;
175
176 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
177 }
178
179 static struct hw_pci dove_pci __initdata = {
180 .nr_controllers = 2,
181 .setup = dove_pcie_setup,
182 .scan = dove_pcie_scan_bus,
183 .map_irq = dove_pcie_map_irq,
184 };
185
add_pcie_port(int index,void __iomem * base)186 static void __init add_pcie_port(int index, void __iomem *base)
187 {
188 printk(KERN_INFO "Dove PCIe port %d: ", index);
189
190 if (orion_pcie_link_up(base)) {
191 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
192 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
193
194 if (!IS_ERR(clk))
195 clk_prepare_enable(clk);
196
197 printk(KERN_INFO "link up\n");
198
199 pp->index = index;
200 pp->root_bus_nr = -1;
201 pp->base = base;
202 spin_lock_init(&pp->conf_lock);
203 memset(&pp->res, 0, sizeof(pp->res));
204 } else {
205 printk(KERN_INFO "link down, ignoring\n");
206 }
207 }
208
dove_pcie_init(int init_port0,int init_port1)209 void __init dove_pcie_init(int init_port0, int init_port1)
210 {
211 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
212
213 if (init_port0)
214 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
215
216 if (init_port1)
217 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
218
219 pci_common_init(&dove_pci);
220 }
221