1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 mmc0 = &sd_emmc_b; /* SD card */ 22 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc2 = &sd_emmc_a; /* SDIO */ 24 }; 25 26 chosen { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 simplefb_cvbs: framebuffer-cvbs { 32 compatible = "amlogic,simple-framebuffer", 33 "simple-framebuffer"; 34 amlogic,pipeline = "vpu-cvbs"; 35 clocks = <&clkc CLKID_HDMI>, 36 <&clkc CLKID_HTX_PCLK>, 37 <&clkc CLKID_VPU_INTR>; 38 status = "disabled"; 39 }; 40 41 simplefb_hdmi: framebuffer-hdmi { 42 compatible = "amlogic,simple-framebuffer", 43 "simple-framebuffer"; 44 amlogic,pipeline = "vpu-hdmi"; 45 clocks = <&clkc CLKID_HDMI>, 46 <&clkc CLKID_HTX_PCLK>, 47 <&clkc CLKID_VPU_INTR>; 48 status = "disabled"; 49 }; 50 }; 51 52 efuse: efuse { 53 compatible = "amlogic,meson-gxbb-efuse"; 54 clocks = <&clkc CLKID_EFUSE>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 read-only; 58 secure-monitor = <&sm>; 59 }; 60 61 gpu_opp_table: opp-table-gpu { 62 compatible = "operating-points-v2"; 63 64 opp-124999998 { 65 opp-hz = /bits/ 64 <124999998>; 66 opp-microvolt = <800000>; 67 }; 68 opp-249999996 { 69 opp-hz = /bits/ 64 <249999996>; 70 opp-microvolt = <800000>; 71 }; 72 opp-285714281 { 73 opp-hz = /bits/ 64 <285714281>; 74 opp-microvolt = <800000>; 75 }; 76 opp-399999994 { 77 opp-hz = /bits/ 64 <399999994>; 78 opp-microvolt = <800000>; 79 }; 80 opp-499999992 { 81 opp-hz = /bits/ 64 <499999992>; 82 opp-microvolt = <800000>; 83 }; 84 opp-666666656 { 85 opp-hz = /bits/ 64 <666666656>; 86 opp-microvolt = <800000>; 87 }; 88 opp-799999987 { 89 opp-hz = /bits/ 64 <799999987>; 90 opp-microvolt = <800000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 reserved-memory { 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 105 secmon_reserved: secmon@5000000 { 106 reg = <0x0 0x05000000 0x0 0x300000>; 107 no-map; 108 }; 109 110 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 111 secmon_reserved_bl32: secmon@5300000 { 112 reg = <0x0 0x05300000 0x0 0x2000000>; 113 no-map; 114 }; 115 116 linux,cma { 117 compatible = "shared-dma-pool"; 118 reusable; 119 size = <0x0 0x10000000>; 120 alignment = <0x0 0x400000>; 121 linux,cma-default; 122 }; 123 }; 124 125 sm: secure-monitor { 126 compatible = "amlogic,meson-gxbb-sm"; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 pcie: pcie@fc000000 { 136 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 137 reg = <0x0 0xfc000000 0x0 0x400000>, 138 <0x0 0xff648000 0x0 0x2000>, 139 <0x0 0xfc400000 0x0 0x200000>; 140 reg-names = "elbi", "cfg", "config"; 141 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 142 #interrupt-cells = <1>; 143 interrupt-map-mask = <0 0 0 0>; 144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 145 bus-range = <0x0 0xff>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 device_type = "pci"; 149 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 150 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 151 152 clocks = <&clkc CLKID_PCIE_PHY 153 &clkc CLKID_PCIE_COMB 154 &clkc CLKID_PCIE_PLL>; 155 clock-names = "general", 156 "pclk", 157 "port"; 158 resets = <&reset RESET_PCIE_CTRL_A>, 159 <&reset RESET_PCIE_APB>; 160 reset-names = "port", 161 "apb"; 162 num-lanes = <1>; 163 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 164 phy-names = "pcie"; 165 status = "disabled"; 166 }; 167 168 thermal-zones { 169 cpu_thermal: cpu-thermal { 170 polling-delay = <1000>; 171 polling-delay-passive = <100>; 172 thermal-sensors = <&cpu_temp>; 173 174 trips { 175 cpu_passive: cpu-passive { 176 temperature = <85000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "passive"; 179 }; 180 181 cpu_hot: cpu-hot { 182 temperature = <95000>; /* millicelsius */ 183 hysteresis = <2000>; /* millicelsius */ 184 type = "hot"; 185 }; 186 187 cpu_critical: cpu-critical { 188 temperature = <110000>; /* millicelsius */ 189 hysteresis = <2000>; /* millicelsius */ 190 type = "critical"; 191 }; 192 }; 193 }; 194 195 ddr_thermal: ddr-thermal { 196 polling-delay = <1000>; 197 polling-delay-passive = <100>; 198 thermal-sensors = <&ddr_temp>; 199 200 trips { 201 ddr_passive: ddr-passive { 202 temperature = <85000>; /* millicelsius */ 203 hysteresis = <2000>; /* millicelsius */ 204 type = "passive"; 205 }; 206 207 ddr_critical: ddr-critical { 208 temperature = <110000>; /* millicelsius */ 209 hysteresis = <2000>; /* millicelsius */ 210 type = "critical"; 211 }; 212 }; 213 214 cooling-maps { 215 map { 216 trip = <&ddr_passive>; 217 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 218 }; 219 }; 220 }; 221 }; 222 223 ethmac: ethernet@ff3f0000 { 224 compatible = "amlogic,meson-g12a-dwmac", 225 "snps,dwmac-3.70a", 226 "snps,dwmac"; 227 reg = <0x0 0xff3f0000 0x0 0x10000>, 228 <0x0 0xff634540 0x0 0x8>; 229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "macirq"; 231 clocks = <&clkc CLKID_ETH>, 232 <&clkc CLKID_FCLK_DIV2>, 233 <&clkc CLKID_MPLL2>, 234 <&clkc CLKID_FCLK_DIV2>; 235 clock-names = "stmmaceth", "clkin0", "clkin1", 236 "timing-adjustment"; 237 rx-fifo-depth = <4096>; 238 tx-fifo-depth = <2048>; 239 status = "disabled"; 240 241 mdio0: mdio { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "snps,dwmac-mdio"; 245 }; 246 }; 247 248 apb: bus@ff600000 { 249 compatible = "simple-bus"; 250 reg = <0x0 0xff600000 0x0 0x200000>; 251 #address-cells = <2>; 252 #size-cells = <2>; 253 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 254 255 hdmi_tx: hdmi-tx@0 { 256 compatible = "amlogic,meson-g12a-dw-hdmi"; 257 reg = <0x0 0x0 0x0 0x10000>; 258 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 259 resets = <&reset RESET_HDMITX_CAPB3>, 260 <&reset RESET_HDMITX_PHY>, 261 <&reset RESET_HDMITX>; 262 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 263 clocks = <&clkc CLKID_HDMI>, 264 <&clkc CLKID_HTX_PCLK>, 265 <&clkc CLKID_VPU_INTR>; 266 clock-names = "isfr", "iahb", "venci"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 #sound-dai-cells = <0>; 270 status = "disabled"; 271 272 /* VPU VENC Input */ 273 hdmi_tx_venc_port: port@0 { 274 reg = <0>; 275 276 hdmi_tx_in: endpoint { 277 remote-endpoint = <&hdmi_tx_out>; 278 }; 279 }; 280 281 /* TMDS Output */ 282 hdmi_tx_tmds_port: port@1 { 283 reg = <1>; 284 }; 285 }; 286 287 apb_efuse: bus@30000 { 288 compatible = "simple-bus"; 289 reg = <0x0 0x30000 0x0 0x2000>; 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 293 294 hwrng: rng@218 { 295 compatible = "amlogic,meson-rng"; 296 reg = <0x0 0x218 0x0 0x4>; 297 clocks = <&clkc CLKID_RNG0>; 298 clock-names = "core"; 299 }; 300 }; 301 302 acodec: audio-controller@32000 { 303 compatible = "amlogic,t9015"; 304 reg = <0x0 0x32000 0x0 0x14>; 305 #sound-dai-cells = <0>; 306 sound-name-prefix = "ACODEC"; 307 clocks = <&clkc CLKID_AUDIO_CODEC>; 308 clock-names = "pclk"; 309 resets = <&reset RESET_AUDIO_CODEC>; 310 status = "disabled"; 311 }; 312 313 periphs: bus@34400 { 314 compatible = "simple-bus"; 315 reg = <0x0 0x34400 0x0 0x400>; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 319 320 periphs_pinctrl: pinctrl@40 { 321 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 322 #address-cells = <2>; 323 #size-cells = <2>; 324 ranges; 325 326 gpio: bank@40 { 327 reg = <0x0 0x40 0x0 0x4c>, 328 <0x0 0xe8 0x0 0x18>, 329 <0x0 0x120 0x0 0x18>, 330 <0x0 0x2c0 0x0 0x40>, 331 <0x0 0x340 0x0 0x1c>; 332 reg-names = "gpio", 333 "pull", 334 "pull-enable", 335 "mux", 336 "ds"; 337 gpio-controller; 338 #gpio-cells = <2>; 339 gpio-ranges = <&periphs_pinctrl 0 0 86>; 340 }; 341 342 cec_ao_a_h_pins: cec_ao_a_h { 343 mux { 344 groups = "cec_ao_a_h"; 345 function = "cec_ao_a_h"; 346 bias-disable; 347 }; 348 }; 349 350 cec_ao_b_h_pins: cec_ao_b_h { 351 mux { 352 groups = "cec_ao_b_h"; 353 function = "cec_ao_b_h"; 354 bias-disable; 355 }; 356 }; 357 358 emmc_ctrl_pins: emmc-ctrl { 359 mux-0 { 360 groups = "emmc_cmd"; 361 function = "emmc"; 362 bias-pull-up; 363 drive-strength-microamp = <4000>; 364 }; 365 366 mux-1 { 367 groups = "emmc_clk"; 368 function = "emmc"; 369 bias-disable; 370 drive-strength-microamp = <4000>; 371 }; 372 }; 373 374 emmc_data_4b_pins: emmc-data-4b { 375 mux-0 { 376 groups = "emmc_nand_d0", 377 "emmc_nand_d1", 378 "emmc_nand_d2", 379 "emmc_nand_d3"; 380 function = "emmc"; 381 bias-pull-up; 382 drive-strength-microamp = <4000>; 383 }; 384 }; 385 386 emmc_data_8b_pins: emmc-data-8b { 387 mux-0 { 388 groups = "emmc_nand_d0", 389 "emmc_nand_d1", 390 "emmc_nand_d2", 391 "emmc_nand_d3", 392 "emmc_nand_d4", 393 "emmc_nand_d5", 394 "emmc_nand_d6", 395 "emmc_nand_d7"; 396 function = "emmc"; 397 bias-pull-up; 398 drive-strength-microamp = <4000>; 399 }; 400 }; 401 402 emmc_ds_pins: emmc-ds { 403 mux { 404 groups = "emmc_nand_ds"; 405 function = "emmc"; 406 bias-pull-down; 407 drive-strength-microamp = <4000>; 408 }; 409 }; 410 411 emmc_clk_gate_pins: emmc_clk_gate { 412 mux { 413 groups = "BOOT_8"; 414 function = "gpio_periphs"; 415 bias-pull-down; 416 drive-strength-microamp = <4000>; 417 }; 418 }; 419 420 hdmitx_ddc_pins: hdmitx_ddc { 421 mux { 422 groups = "hdmitx_sda", 423 "hdmitx_sck"; 424 function = "hdmitx"; 425 bias-disable; 426 drive-strength-microamp = <4000>; 427 }; 428 }; 429 430 hdmitx_hpd_pins: hdmitx_hpd { 431 mux { 432 groups = "hdmitx_hpd_in"; 433 function = "hdmitx"; 434 bias-disable; 435 }; 436 }; 437 438 439 i2c0_sda_c_pins: i2c0-sda-c { 440 mux { 441 groups = "i2c0_sda_c"; 442 function = "i2c0"; 443 bias-disable; 444 drive-strength-microamp = <3000>; 445 446 }; 447 }; 448 449 i2c0_sck_c_pins: i2c0-sck-c { 450 mux { 451 groups = "i2c0_sck_c"; 452 function = "i2c0"; 453 bias-disable; 454 drive-strength-microamp = <3000>; 455 }; 456 }; 457 458 i2c0_sda_z0_pins: i2c0-sda-z0 { 459 mux { 460 groups = "i2c0_sda_z0"; 461 function = "i2c0"; 462 bias-disable; 463 drive-strength-microamp = <3000>; 464 }; 465 }; 466 467 i2c0_sck_z1_pins: i2c0-sck-z1 { 468 mux { 469 groups = "i2c0_sck_z1"; 470 function = "i2c0"; 471 bias-disable; 472 drive-strength-microamp = <3000>; 473 }; 474 }; 475 476 i2c0_sda_z7_pins: i2c0-sda-z7 { 477 mux { 478 groups = "i2c0_sda_z7"; 479 function = "i2c0"; 480 bias-disable; 481 drive-strength-microamp = <3000>; 482 }; 483 }; 484 485 i2c0_sda_z8_pins: i2c0-sda-z8 { 486 mux { 487 groups = "i2c0_sda_z8"; 488 function = "i2c0"; 489 bias-disable; 490 drive-strength-microamp = <3000>; 491 }; 492 }; 493 494 i2c1_sda_x_pins: i2c1-sda-x { 495 mux { 496 groups = "i2c1_sda_x"; 497 function = "i2c1"; 498 bias-disable; 499 drive-strength-microamp = <3000>; 500 }; 501 }; 502 503 i2c1_sck_x_pins: i2c1-sck-x { 504 mux { 505 groups = "i2c1_sck_x"; 506 function = "i2c1"; 507 bias-disable; 508 drive-strength-microamp = <3000>; 509 }; 510 }; 511 512 i2c1_sda_h2_pins: i2c1-sda-h2 { 513 mux { 514 groups = "i2c1_sda_h2"; 515 function = "i2c1"; 516 bias-disable; 517 drive-strength-microamp = <3000>; 518 }; 519 }; 520 521 i2c1_sck_h3_pins: i2c1-sck-h3 { 522 mux { 523 groups = "i2c1_sck_h3"; 524 function = "i2c1"; 525 bias-disable; 526 drive-strength-microamp = <3000>; 527 }; 528 }; 529 530 i2c1_sda_h6_pins: i2c1-sda-h6 { 531 mux { 532 groups = "i2c1_sda_h6"; 533 function = "i2c1"; 534 bias-disable; 535 drive-strength-microamp = <3000>; 536 }; 537 }; 538 539 i2c1_sck_h7_pins: i2c1-sck-h7 { 540 mux { 541 groups = "i2c1_sck_h7"; 542 function = "i2c1"; 543 bias-disable; 544 drive-strength-microamp = <3000>; 545 }; 546 }; 547 548 i2c2_sda_x_pins: i2c2-sda-x { 549 mux { 550 groups = "i2c2_sda_x"; 551 function = "i2c2"; 552 bias-disable; 553 drive-strength-microamp = <3000>; 554 }; 555 }; 556 557 i2c2_sck_x_pins: i2c2-sck-x { 558 mux { 559 groups = "i2c2_sck_x"; 560 function = "i2c2"; 561 bias-disable; 562 drive-strength-microamp = <3000>; 563 }; 564 }; 565 566 i2c2_sda_z_pins: i2c2-sda-z { 567 mux { 568 groups = "i2c2_sda_z"; 569 function = "i2c2"; 570 bias-disable; 571 drive-strength-microamp = <3000>; 572 }; 573 }; 574 575 i2c2_sck_z_pins: i2c2-sck-z { 576 mux { 577 groups = "i2c2_sck_z"; 578 function = "i2c2"; 579 bias-disable; 580 drive-strength-microamp = <3000>; 581 }; 582 }; 583 584 i2c3_sda_h_pins: i2c3-sda-h { 585 mux { 586 groups = "i2c3_sda_h"; 587 function = "i2c3"; 588 bias-disable; 589 drive-strength-microamp = <3000>; 590 }; 591 }; 592 593 i2c3_sck_h_pins: i2c3-sck-h { 594 mux { 595 groups = "i2c3_sck_h"; 596 function = "i2c3"; 597 bias-disable; 598 drive-strength-microamp = <3000>; 599 }; 600 }; 601 602 i2c3_sda_a_pins: i2c3-sda-a { 603 mux { 604 groups = "i2c3_sda_a"; 605 function = "i2c3"; 606 bias-disable; 607 drive-strength-microamp = <3000>; 608 }; 609 }; 610 611 i2c3_sck_a_pins: i2c3-sck-a { 612 mux { 613 groups = "i2c3_sck_a"; 614 function = "i2c3"; 615 bias-disable; 616 drive-strength-microamp = <3000>; 617 }; 618 }; 619 620 mclk0_a_pins: mclk0-a { 621 mux { 622 groups = "mclk0_a"; 623 function = "mclk0"; 624 bias-disable; 625 drive-strength-microamp = <3000>; 626 }; 627 }; 628 629 mclk1_a_pins: mclk1-a { 630 mux { 631 groups = "mclk1_a"; 632 function = "mclk1"; 633 bias-disable; 634 drive-strength-microamp = <3000>; 635 }; 636 }; 637 638 mclk1_x_pins: mclk1-x { 639 mux { 640 groups = "mclk1_x"; 641 function = "mclk1"; 642 bias-disable; 643 drive-strength-microamp = <3000>; 644 }; 645 }; 646 647 mclk1_z_pins: mclk1-z { 648 mux { 649 groups = "mclk1_z"; 650 function = "mclk1"; 651 bias-disable; 652 drive-strength-microamp = <3000>; 653 }; 654 }; 655 656 nor_pins: nor { 657 mux { 658 groups = "nor_d", 659 "nor_q", 660 "nor_c", 661 "nor_cs"; 662 function = "nor"; 663 bias-disable; 664 }; 665 }; 666 667 pdm_din0_a_pins: pdm-din0-a { 668 mux { 669 groups = "pdm_din0_a"; 670 function = "pdm"; 671 bias-disable; 672 }; 673 }; 674 675 pdm_din0_c_pins: pdm-din0-c { 676 mux { 677 groups = "pdm_din0_c"; 678 function = "pdm"; 679 bias-disable; 680 }; 681 }; 682 683 pdm_din0_x_pins: pdm-din0-x { 684 mux { 685 groups = "pdm_din0_x"; 686 function = "pdm"; 687 bias-disable; 688 }; 689 }; 690 691 pdm_din0_z_pins: pdm-din0-z { 692 mux { 693 groups = "pdm_din0_z"; 694 function = "pdm"; 695 bias-disable; 696 }; 697 }; 698 699 pdm_din1_a_pins: pdm-din1-a { 700 mux { 701 groups = "pdm_din1_a"; 702 function = "pdm"; 703 bias-disable; 704 }; 705 }; 706 707 pdm_din1_c_pins: pdm-din1-c { 708 mux { 709 groups = "pdm_din1_c"; 710 function = "pdm"; 711 bias-disable; 712 }; 713 }; 714 715 pdm_din1_x_pins: pdm-din1-x { 716 mux { 717 groups = "pdm_din1_x"; 718 function = "pdm"; 719 bias-disable; 720 }; 721 }; 722 723 pdm_din1_z_pins: pdm-din1-z { 724 mux { 725 groups = "pdm_din1_z"; 726 function = "pdm"; 727 bias-disable; 728 }; 729 }; 730 731 pdm_din2_a_pins: pdm-din2-a { 732 mux { 733 groups = "pdm_din2_a"; 734 function = "pdm"; 735 bias-disable; 736 }; 737 }; 738 739 pdm_din2_c_pins: pdm-din2-c { 740 mux { 741 groups = "pdm_din2_c"; 742 function = "pdm"; 743 bias-disable; 744 }; 745 }; 746 747 pdm_din2_x_pins: pdm-din2-x { 748 mux { 749 groups = "pdm_din2_x"; 750 function = "pdm"; 751 bias-disable; 752 }; 753 }; 754 755 pdm_din2_z_pins: pdm-din2-z { 756 mux { 757 groups = "pdm_din2_z"; 758 function = "pdm"; 759 bias-disable; 760 }; 761 }; 762 763 pdm_din3_a_pins: pdm-din3-a { 764 mux { 765 groups = "pdm_din3_a"; 766 function = "pdm"; 767 bias-disable; 768 }; 769 }; 770 771 pdm_din3_c_pins: pdm-din3-c { 772 mux { 773 groups = "pdm_din3_c"; 774 function = "pdm"; 775 bias-disable; 776 }; 777 }; 778 779 pdm_din3_x_pins: pdm-din3-x { 780 mux { 781 groups = "pdm_din3_x"; 782 function = "pdm"; 783 bias-disable; 784 }; 785 }; 786 787 pdm_din3_z_pins: pdm-din3-z { 788 mux { 789 groups = "pdm_din3_z"; 790 function = "pdm"; 791 bias-disable; 792 }; 793 }; 794 795 pdm_dclk_a_pins: pdm-dclk-a { 796 mux { 797 groups = "pdm_dclk_a"; 798 function = "pdm"; 799 bias-disable; 800 drive-strength-microamp = <500>; 801 }; 802 }; 803 804 pdm_dclk_c_pins: pdm-dclk-c { 805 mux { 806 groups = "pdm_dclk_c"; 807 function = "pdm"; 808 bias-disable; 809 drive-strength-microamp = <500>; 810 }; 811 }; 812 813 pdm_dclk_x_pins: pdm-dclk-x { 814 mux { 815 groups = "pdm_dclk_x"; 816 function = "pdm"; 817 bias-disable; 818 drive-strength-microamp = <500>; 819 }; 820 }; 821 822 pdm_dclk_z_pins: pdm-dclk-z { 823 mux { 824 groups = "pdm_dclk_z"; 825 function = "pdm"; 826 bias-disable; 827 drive-strength-microamp = <500>; 828 }; 829 }; 830 831 pwm_a_pins: pwm-a { 832 mux { 833 groups = "pwm_a"; 834 function = "pwm_a"; 835 bias-disable; 836 }; 837 }; 838 839 pwm_b_x7_pins: pwm-b-x7 { 840 mux { 841 groups = "pwm_b_x7"; 842 function = "pwm_b"; 843 bias-disable; 844 }; 845 }; 846 847 pwm_b_x19_pins: pwm-b-x19 { 848 mux { 849 groups = "pwm_b_x19"; 850 function = "pwm_b"; 851 bias-disable; 852 }; 853 }; 854 855 pwm_c_c_pins: pwm-c-c { 856 mux { 857 groups = "pwm_c_c"; 858 function = "pwm_c"; 859 bias-disable; 860 }; 861 }; 862 863 pwm_c_x5_pins: pwm-c-x5 { 864 mux { 865 groups = "pwm_c_x5"; 866 function = "pwm_c"; 867 bias-disable; 868 }; 869 }; 870 871 pwm_c_x8_pins: pwm-c-x8 { 872 mux { 873 groups = "pwm_c_x8"; 874 function = "pwm_c"; 875 bias-disable; 876 }; 877 }; 878 879 pwm_d_x3_pins: pwm-d-x3 { 880 mux { 881 groups = "pwm_d_x3"; 882 function = "pwm_d"; 883 bias-disable; 884 }; 885 }; 886 887 pwm_d_x6_pins: pwm-d-x6 { 888 mux { 889 groups = "pwm_d_x6"; 890 function = "pwm_d"; 891 bias-disable; 892 }; 893 }; 894 895 pwm_e_pins: pwm-e { 896 mux { 897 groups = "pwm_e"; 898 function = "pwm_e"; 899 bias-disable; 900 }; 901 }; 902 903 pwm_f_x_pins: pwm-f-x { 904 mux { 905 groups = "pwm_f_x"; 906 function = "pwm_f"; 907 bias-disable; 908 }; 909 }; 910 911 pwm_f_h_pins: pwm-f-h { 912 mux { 913 groups = "pwm_f_h"; 914 function = "pwm_f"; 915 bias-disable; 916 }; 917 }; 918 919 sdcard_c_pins: sdcard_c { 920 mux-0 { 921 groups = "sdcard_d0_c", 922 "sdcard_d1_c", 923 "sdcard_d2_c", 924 "sdcard_d3_c", 925 "sdcard_cmd_c"; 926 function = "sdcard"; 927 bias-pull-up; 928 drive-strength-microamp = <4000>; 929 }; 930 931 mux-1 { 932 groups = "sdcard_clk_c"; 933 function = "sdcard"; 934 bias-disable; 935 drive-strength-microamp = <4000>; 936 }; 937 }; 938 939 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 940 mux { 941 groups = "GPIOC_4"; 942 function = "gpio_periphs"; 943 bias-pull-down; 944 drive-strength-microamp = <4000>; 945 }; 946 }; 947 948 sdcard_z_pins: sdcard_z { 949 mux-0 { 950 groups = "sdcard_d0_z", 951 "sdcard_d1_z", 952 "sdcard_d2_z", 953 "sdcard_d3_z", 954 "sdcard_cmd_z"; 955 function = "sdcard"; 956 bias-pull-up; 957 drive-strength-microamp = <4000>; 958 }; 959 960 mux-1 { 961 groups = "sdcard_clk_z"; 962 function = "sdcard"; 963 bias-disable; 964 drive-strength-microamp = <4000>; 965 }; 966 }; 967 968 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 969 mux { 970 groups = "GPIOZ_6"; 971 function = "gpio_periphs"; 972 bias-pull-down; 973 drive-strength-microamp = <4000>; 974 }; 975 }; 976 977 sdio_pins: sdio { 978 mux { 979 groups = "sdio_d0", 980 "sdio_d1", 981 "sdio_d2", 982 "sdio_d3", 983 "sdio_clk", 984 "sdio_cmd"; 985 function = "sdio"; 986 bias-disable; 987 drive-strength-microamp = <4000>; 988 }; 989 }; 990 991 sdio_clk_gate_pins: sdio_clk_gate { 992 mux { 993 groups = "GPIOX_4"; 994 function = "gpio_periphs"; 995 bias-pull-down; 996 drive-strength-microamp = <4000>; 997 }; 998 }; 999 1000 spdif_in_a10_pins: spdif-in-a10 { 1001 mux { 1002 groups = "spdif_in_a10"; 1003 function = "spdif_in"; 1004 bias-disable; 1005 }; 1006 }; 1007 1008 spdif_in_a12_pins: spdif-in-a12 { 1009 mux { 1010 groups = "spdif_in_a12"; 1011 function = "spdif_in"; 1012 bias-disable; 1013 }; 1014 }; 1015 1016 spdif_in_h_pins: spdif-in-h { 1017 mux { 1018 groups = "spdif_in_h"; 1019 function = "spdif_in"; 1020 bias-disable; 1021 }; 1022 }; 1023 1024 spdif_out_h_pins: spdif-out-h { 1025 mux { 1026 groups = "spdif_out_h"; 1027 function = "spdif_out"; 1028 drive-strength-microamp = <500>; 1029 bias-disable; 1030 }; 1031 }; 1032 1033 spdif_out_a11_pins: spdif-out-a11 { 1034 mux { 1035 groups = "spdif_out_a11"; 1036 function = "spdif_out"; 1037 drive-strength-microamp = <500>; 1038 bias-disable; 1039 }; 1040 }; 1041 1042 spdif_out_a13_pins: spdif-out-a13 { 1043 mux { 1044 groups = "spdif_out_a13"; 1045 function = "spdif_out"; 1046 drive-strength-microamp = <500>; 1047 bias-disable; 1048 }; 1049 }; 1050 1051 spicc0_x_pins: spicc0-x { 1052 mux { 1053 groups = "spi0_mosi_x", 1054 "spi0_miso_x", 1055 "spi0_clk_x"; 1056 function = "spi0"; 1057 drive-strength-microamp = <4000>; 1058 bias-disable; 1059 }; 1060 }; 1061 1062 spicc0_ss0_x_pins: spicc0-ss0-x { 1063 mux { 1064 groups = "spi0_ss0_x"; 1065 function = "spi0"; 1066 drive-strength-microamp = <4000>; 1067 bias-disable; 1068 }; 1069 }; 1070 1071 spicc0_c_pins: spicc0-c { 1072 mux { 1073 groups = "spi0_mosi_c", 1074 "spi0_miso_c", 1075 "spi0_ss0_c", 1076 "spi0_clk_c"; 1077 function = "spi0"; 1078 drive-strength-microamp = <4000>; 1079 bias-disable; 1080 }; 1081 }; 1082 1083 spicc1_pins: spicc1 { 1084 mux { 1085 groups = "spi1_mosi", 1086 "spi1_miso", 1087 "spi1_clk"; 1088 function = "spi1"; 1089 drive-strength-microamp = <4000>; 1090 }; 1091 }; 1092 1093 spicc1_ss0_pins: spicc1-ss0 { 1094 mux { 1095 groups = "spi1_ss0"; 1096 function = "spi1"; 1097 drive-strength-microamp = <4000>; 1098 bias-disable; 1099 }; 1100 }; 1101 1102 tdm_a_din0_pins: tdm-a-din0 { 1103 mux { 1104 groups = "tdm_a_din0"; 1105 function = "tdm_a"; 1106 bias-disable; 1107 }; 1108 }; 1109 1110 1111 tdm_a_din1_pins: tdm-a-din1 { 1112 mux { 1113 groups = "tdm_a_din1"; 1114 function = "tdm_a"; 1115 bias-disable; 1116 }; 1117 }; 1118 1119 tdm_a_dout0_pins: tdm-a-dout0 { 1120 mux { 1121 groups = "tdm_a_dout0"; 1122 function = "tdm_a"; 1123 bias-disable; 1124 drive-strength-microamp = <3000>; 1125 }; 1126 }; 1127 1128 tdm_a_dout1_pins: tdm-a-dout1 { 1129 mux { 1130 groups = "tdm_a_dout1"; 1131 function = "tdm_a"; 1132 bias-disable; 1133 drive-strength-microamp = <3000>; 1134 }; 1135 }; 1136 1137 tdm_a_fs_pins: tdm-a-fs { 1138 mux { 1139 groups = "tdm_a_fs"; 1140 function = "tdm_a"; 1141 bias-disable; 1142 drive-strength-microamp = <3000>; 1143 }; 1144 }; 1145 1146 tdm_a_sclk_pins: tdm-a-sclk { 1147 mux { 1148 groups = "tdm_a_sclk"; 1149 function = "tdm_a"; 1150 bias-disable; 1151 drive-strength-microamp = <3000>; 1152 }; 1153 }; 1154 1155 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1156 mux { 1157 groups = "tdm_a_slv_fs"; 1158 function = "tdm_a"; 1159 bias-disable; 1160 }; 1161 }; 1162 1163 1164 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1165 mux { 1166 groups = "tdm_a_slv_sclk"; 1167 function = "tdm_a"; 1168 bias-disable; 1169 }; 1170 }; 1171 1172 tdm_b_din0_pins: tdm-b-din0 { 1173 mux { 1174 groups = "tdm_b_din0"; 1175 function = "tdm_b"; 1176 bias-disable; 1177 }; 1178 }; 1179 1180 tdm_b_din1_pins: tdm-b-din1 { 1181 mux { 1182 groups = "tdm_b_din1"; 1183 function = "tdm_b"; 1184 bias-disable; 1185 }; 1186 }; 1187 1188 tdm_b_din2_pins: tdm-b-din2 { 1189 mux { 1190 groups = "tdm_b_din2"; 1191 function = "tdm_b"; 1192 bias-disable; 1193 }; 1194 }; 1195 1196 tdm_b_din3_a_pins: tdm-b-din3-a { 1197 mux { 1198 groups = "tdm_b_din3_a"; 1199 function = "tdm_b"; 1200 bias-disable; 1201 }; 1202 }; 1203 1204 tdm_b_din3_h_pins: tdm-b-din3-h { 1205 mux { 1206 groups = "tdm_b_din3_h"; 1207 function = "tdm_b"; 1208 bias-disable; 1209 }; 1210 }; 1211 1212 tdm_b_dout0_pins: tdm-b-dout0 { 1213 mux { 1214 groups = "tdm_b_dout0"; 1215 function = "tdm_b"; 1216 bias-disable; 1217 drive-strength-microamp = <3000>; 1218 }; 1219 }; 1220 1221 tdm_b_dout1_pins: tdm-b-dout1 { 1222 mux { 1223 groups = "tdm_b_dout1"; 1224 function = "tdm_b"; 1225 bias-disable; 1226 drive-strength-microamp = <3000>; 1227 }; 1228 }; 1229 1230 tdm_b_dout2_pins: tdm-b-dout2 { 1231 mux { 1232 groups = "tdm_b_dout2"; 1233 function = "tdm_b"; 1234 bias-disable; 1235 drive-strength-microamp = <3000>; 1236 }; 1237 }; 1238 1239 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1240 mux { 1241 groups = "tdm_b_dout3_a"; 1242 function = "tdm_b"; 1243 bias-disable; 1244 drive-strength-microamp = <3000>; 1245 }; 1246 }; 1247 1248 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1249 mux { 1250 groups = "tdm_b_dout3_h"; 1251 function = "tdm_b"; 1252 bias-disable; 1253 drive-strength-microamp = <3000>; 1254 }; 1255 }; 1256 1257 tdm_b_fs_pins: tdm-b-fs { 1258 mux { 1259 groups = "tdm_b_fs"; 1260 function = "tdm_b"; 1261 bias-disable; 1262 drive-strength-microamp = <3000>; 1263 }; 1264 }; 1265 1266 tdm_b_sclk_pins: tdm-b-sclk { 1267 mux { 1268 groups = "tdm_b_sclk"; 1269 function = "tdm_b"; 1270 bias-disable; 1271 drive-strength-microamp = <3000>; 1272 }; 1273 }; 1274 1275 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1276 mux { 1277 groups = "tdm_b_slv_fs"; 1278 function = "tdm_b"; 1279 bias-disable; 1280 }; 1281 }; 1282 1283 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1284 mux { 1285 groups = "tdm_b_slv_sclk"; 1286 function = "tdm_b"; 1287 bias-disable; 1288 }; 1289 }; 1290 1291 tdm_c_din0_a_pins: tdm-c-din0-a { 1292 mux { 1293 groups = "tdm_c_din0_a"; 1294 function = "tdm_c"; 1295 bias-disable; 1296 }; 1297 }; 1298 1299 tdm_c_din0_z_pins: tdm-c-din0-z { 1300 mux { 1301 groups = "tdm_c_din0_z"; 1302 function = "tdm_c"; 1303 bias-disable; 1304 }; 1305 }; 1306 1307 tdm_c_din1_a_pins: tdm-c-din1-a { 1308 mux { 1309 groups = "tdm_c_din1_a"; 1310 function = "tdm_c"; 1311 bias-disable; 1312 }; 1313 }; 1314 1315 tdm_c_din1_z_pins: tdm-c-din1-z { 1316 mux { 1317 groups = "tdm_c_din1_z"; 1318 function = "tdm_c"; 1319 bias-disable; 1320 }; 1321 }; 1322 1323 tdm_c_din2_a_pins: tdm-c-din2-a { 1324 mux { 1325 groups = "tdm_c_din2_a"; 1326 function = "tdm_c"; 1327 bias-disable; 1328 }; 1329 }; 1330 1331 eth_leds_pins: eth-leds { 1332 mux { 1333 groups = "eth_link_led", 1334 "eth_act_led"; 1335 function = "eth"; 1336 bias-disable; 1337 }; 1338 }; 1339 1340 eth_pins: eth { 1341 mux { 1342 groups = "eth_mdio", 1343 "eth_mdc", 1344 "eth_rgmii_rx_clk", 1345 "eth_rx_dv", 1346 "eth_rxd0", 1347 "eth_rxd1", 1348 "eth_txen", 1349 "eth_txd0", 1350 "eth_txd1"; 1351 function = "eth"; 1352 drive-strength-microamp = <4000>; 1353 bias-disable; 1354 }; 1355 }; 1356 1357 eth_rgmii_pins: eth-rgmii { 1358 mux { 1359 groups = "eth_rxd2_rgmii", 1360 "eth_rxd3_rgmii", 1361 "eth_rgmii_tx_clk", 1362 "eth_txd2_rgmii", 1363 "eth_txd3_rgmii"; 1364 function = "eth"; 1365 drive-strength-microamp = <4000>; 1366 bias-disable; 1367 }; 1368 }; 1369 1370 tdm_c_din2_z_pins: tdm-c-din2-z { 1371 mux { 1372 groups = "tdm_c_din2_z"; 1373 function = "tdm_c"; 1374 bias-disable; 1375 }; 1376 }; 1377 1378 tdm_c_din3_a_pins: tdm-c-din3-a { 1379 mux { 1380 groups = "tdm_c_din3_a"; 1381 function = "tdm_c"; 1382 bias-disable; 1383 }; 1384 }; 1385 1386 tdm_c_din3_z_pins: tdm-c-din3-z { 1387 mux { 1388 groups = "tdm_c_din3_z"; 1389 function = "tdm_c"; 1390 bias-disable; 1391 }; 1392 }; 1393 1394 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1395 mux { 1396 groups = "tdm_c_dout0_a"; 1397 function = "tdm_c"; 1398 bias-disable; 1399 drive-strength-microamp = <3000>; 1400 }; 1401 }; 1402 1403 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1404 mux { 1405 groups = "tdm_c_dout0_z"; 1406 function = "tdm_c"; 1407 bias-disable; 1408 drive-strength-microamp = <3000>; 1409 }; 1410 }; 1411 1412 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1413 mux { 1414 groups = "tdm_c_dout1_a"; 1415 function = "tdm_c"; 1416 bias-disable; 1417 drive-strength-microamp = <3000>; 1418 }; 1419 }; 1420 1421 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1422 mux { 1423 groups = "tdm_c_dout1_z"; 1424 function = "tdm_c"; 1425 bias-disable; 1426 drive-strength-microamp = <3000>; 1427 }; 1428 }; 1429 1430 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1431 mux { 1432 groups = "tdm_c_dout2_a"; 1433 function = "tdm_c"; 1434 bias-disable; 1435 drive-strength-microamp = <3000>; 1436 }; 1437 }; 1438 1439 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1440 mux { 1441 groups = "tdm_c_dout2_z"; 1442 function = "tdm_c"; 1443 bias-disable; 1444 drive-strength-microamp = <3000>; 1445 }; 1446 }; 1447 1448 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1449 mux { 1450 groups = "tdm_c_dout3_a"; 1451 function = "tdm_c"; 1452 bias-disable; 1453 drive-strength-microamp = <3000>; 1454 }; 1455 }; 1456 1457 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1458 mux { 1459 groups = "tdm_c_dout3_z"; 1460 function = "tdm_c"; 1461 bias-disable; 1462 drive-strength-microamp = <3000>; 1463 }; 1464 }; 1465 1466 tdm_c_fs_a_pins: tdm-c-fs-a { 1467 mux { 1468 groups = "tdm_c_fs_a"; 1469 function = "tdm_c"; 1470 bias-disable; 1471 drive-strength-microamp = <3000>; 1472 }; 1473 }; 1474 1475 tdm_c_fs_z_pins: tdm-c-fs-z { 1476 mux { 1477 groups = "tdm_c_fs_z"; 1478 function = "tdm_c"; 1479 bias-disable; 1480 drive-strength-microamp = <3000>; 1481 }; 1482 }; 1483 1484 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1485 mux { 1486 groups = "tdm_c_sclk_a"; 1487 function = "tdm_c"; 1488 bias-disable; 1489 drive-strength-microamp = <3000>; 1490 }; 1491 }; 1492 1493 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1494 mux { 1495 groups = "tdm_c_sclk_z"; 1496 function = "tdm_c"; 1497 bias-disable; 1498 drive-strength-microamp = <3000>; 1499 }; 1500 }; 1501 1502 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1503 mux { 1504 groups = "tdm_c_slv_fs_a"; 1505 function = "tdm_c"; 1506 bias-disable; 1507 }; 1508 }; 1509 1510 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1511 mux { 1512 groups = "tdm_c_slv_fs_z"; 1513 function = "tdm_c"; 1514 bias-disable; 1515 }; 1516 }; 1517 1518 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1519 mux { 1520 groups = "tdm_c_slv_sclk_a"; 1521 function = "tdm_c"; 1522 bias-disable; 1523 }; 1524 }; 1525 1526 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1527 mux { 1528 groups = "tdm_c_slv_sclk_z"; 1529 function = "tdm_c"; 1530 bias-disable; 1531 }; 1532 }; 1533 1534 uart_a_pins: uart-a { 1535 mux { 1536 groups = "uart_a_tx", 1537 "uart_a_rx"; 1538 function = "uart_a"; 1539 bias-disable; 1540 }; 1541 }; 1542 1543 uart_a_cts_rts_pins: uart-a-cts-rts { 1544 mux { 1545 groups = "uart_a_cts", 1546 "uart_a_rts"; 1547 function = "uart_a"; 1548 bias-disable; 1549 }; 1550 }; 1551 1552 uart_b_pins: uart-b { 1553 mux { 1554 groups = "uart_b_tx", 1555 "uart_b_rx"; 1556 function = "uart_b"; 1557 bias-disable; 1558 }; 1559 }; 1560 1561 uart_c_pins: uart-c { 1562 mux { 1563 groups = "uart_c_tx", 1564 "uart_c_rx"; 1565 function = "uart_c"; 1566 bias-disable; 1567 }; 1568 }; 1569 1570 uart_c_cts_rts_pins: uart-c-cts-rts { 1571 mux { 1572 groups = "uart_c_cts", 1573 "uart_c_rts"; 1574 function = "uart_c"; 1575 bias-disable; 1576 }; 1577 }; 1578 }; 1579 }; 1580 1581 cpu_temp: temperature-sensor@34800 { 1582 compatible = "amlogic,g12a-cpu-thermal", 1583 "amlogic,g12a-thermal"; 1584 reg = <0x0 0x34800 0x0 0x50>; 1585 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1586 clocks = <&clkc CLKID_TS>; 1587 #thermal-sensor-cells = <0>; 1588 amlogic,ao-secure = <&sec_AO>; 1589 }; 1590 1591 ddr_temp: temperature-sensor@34c00 { 1592 compatible = "amlogic,g12a-ddr-thermal", 1593 "amlogic,g12a-thermal"; 1594 reg = <0x0 0x34c00 0x0 0x50>; 1595 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1596 clocks = <&clkc CLKID_TS>; 1597 #thermal-sensor-cells = <0>; 1598 amlogic,ao-secure = <&sec_AO>; 1599 }; 1600 1601 usb2_phy0: phy@36000 { 1602 compatible = "amlogic,g12a-usb2-phy"; 1603 reg = <0x0 0x36000 0x0 0x2000>; 1604 clocks = <&xtal>; 1605 clock-names = "xtal"; 1606 resets = <&reset RESET_USB_PHY20>; 1607 reset-names = "phy"; 1608 #phy-cells = <0>; 1609 }; 1610 1611 dmc: bus@38000 { 1612 compatible = "simple-bus"; 1613 #address-cells = <2>; 1614 #size-cells = <2>; 1615 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>; 1616 1617 canvas: video-lut@48 { 1618 compatible = "amlogic,canvas"; 1619 reg = <0x0 0x48 0x0 0x14>; 1620 }; 1621 }; 1622 1623 usb2_phy1: phy@3a000 { 1624 compatible = "amlogic,g12a-usb2-phy"; 1625 reg = <0x0 0x3a000 0x0 0x2000>; 1626 clocks = <&xtal>; 1627 clock-names = "xtal"; 1628 resets = <&reset RESET_USB_PHY21>; 1629 reset-names = "phy"; 1630 #phy-cells = <0>; 1631 }; 1632 1633 hiu: bus@3c000 { 1634 compatible = "simple-bus"; 1635 reg = <0x0 0x3c000 0x0 0x1400>; 1636 #address-cells = <2>; 1637 #size-cells = <2>; 1638 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1639 1640 hhi: system-controller@0 { 1641 compatible = "amlogic,meson-gx-hhi-sysctrl", 1642 "simple-mfd", "syscon"; 1643 reg = <0 0 0 0x400>; 1644 1645 clkc: clock-controller { 1646 compatible = "amlogic,g12a-clkc"; 1647 #clock-cells = <1>; 1648 clocks = <&xtal>; 1649 clock-names = "xtal"; 1650 }; 1651 1652 pwrc: power-controller { 1653 compatible = "amlogic,meson-g12a-pwrc"; 1654 #power-domain-cells = <1>; 1655 amlogic,ao-sysctrl = <&rti>; 1656 resets = <&reset RESET_VIU>, 1657 <&reset RESET_VENC>, 1658 <&reset RESET_VCBUS>, 1659 <&reset RESET_BT656>, 1660 <&reset RESET_RDMA>, 1661 <&reset RESET_VENCI>, 1662 <&reset RESET_VENCP>, 1663 <&reset RESET_VDAC>, 1664 <&reset RESET_VDI6>, 1665 <&reset RESET_VENCL>, 1666 <&reset RESET_VID_LOCK>; 1667 reset-names = "viu", "venc", "vcbus", "bt656", 1668 "rdma", "venci", "vencp", "vdac", 1669 "vdi6", "vencl", "vid_lock"; 1670 clocks = <&clkc CLKID_VPU>, 1671 <&clkc CLKID_VAPB>; 1672 clock-names = "vpu", "vapb"; 1673 /* 1674 * VPU clocking is provided by two identical clock paths 1675 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1676 * free mux to safely change frequency while running. 1677 * Same for VAPB but with a final gate after the glitch free mux. 1678 */ 1679 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1680 <&clkc CLKID_VPU_0>, 1681 <&clkc CLKID_VPU>, /* Glitch free mux */ 1682 <&clkc CLKID_VAPB_0_SEL>, 1683 <&clkc CLKID_VAPB_0>, 1684 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1685 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1686 <0>, /* Do Nothing */ 1687 <&clkc CLKID_VPU_0>, 1688 <&clkc CLKID_FCLK_DIV4>, 1689 <0>, /* Do Nothing */ 1690 <&clkc CLKID_VAPB_0>; 1691 assigned-clock-rates = <0>, /* Do Nothing */ 1692 <666666666>, 1693 <0>, /* Do Nothing */ 1694 <0>, /* Do Nothing */ 1695 <250000000>, 1696 <0>; /* Do Nothing */ 1697 }; 1698 }; 1699 }; 1700 1701 usb3_pcie_phy: phy@46000 { 1702 compatible = "amlogic,g12a-usb3-pcie-phy"; 1703 reg = <0x0 0x46000 0x0 0x2000>; 1704 clocks = <&clkc CLKID_PCIE_PLL>; 1705 clock-names = "ref_clk"; 1706 resets = <&reset RESET_PCIE_PHY>; 1707 reset-names = "phy"; 1708 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1709 assigned-clock-rates = <100000000>; 1710 #phy-cells = <1>; 1711 }; 1712 1713 eth_phy: mdio-multiplexer@4c000 { 1714 compatible = "amlogic,g12a-mdio-mux"; 1715 reg = <0x0 0x4c000 0x0 0xa4>; 1716 clocks = <&clkc CLKID_ETH_PHY>, 1717 <&xtal>, 1718 <&clkc CLKID_MPLL_50M>; 1719 clock-names = "pclk", "clkin0", "clkin1"; 1720 mdio-parent-bus = <&mdio0>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 ext_mdio: mdio@0 { 1725 reg = <0>; 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 }; 1729 1730 int_mdio: mdio@1 { 1731 reg = <1>; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 internal_ephy: ethernet-phy@8 { 1736 compatible = "ethernet-phy-id0180.3301", 1737 "ethernet-phy-ieee802.3-c22"; 1738 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1739 reg = <8>; 1740 max-speed = <100>; 1741 }; 1742 }; 1743 }; 1744 }; 1745 1746 aobus: bus@ff800000 { 1747 compatible = "simple-bus"; 1748 reg = <0x0 0xff800000 0x0 0x100000>; 1749 #address-cells = <2>; 1750 #size-cells = <2>; 1751 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1752 1753 rti: sys-ctrl@0 { 1754 compatible = "amlogic,meson-gx-ao-sysctrl", 1755 "simple-mfd", "syscon"; 1756 reg = <0x0 0x0 0x0 0x100>; 1757 #address-cells = <2>; 1758 #size-cells = <2>; 1759 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1760 1761 clkc_AO: clock-controller { 1762 compatible = "amlogic,meson-g12a-aoclkc"; 1763 #clock-cells = <1>; 1764 #reset-cells = <1>; 1765 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1766 clock-names = "xtal", "mpeg-clk"; 1767 }; 1768 1769 ao_pinctrl: pinctrl@14 { 1770 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1771 #address-cells = <2>; 1772 #size-cells = <2>; 1773 ranges; 1774 1775 gpio_ao: bank@14 { 1776 reg = <0x0 0x14 0x0 0x8>, 1777 <0x0 0x1c 0x0 0x8>, 1778 <0x0 0x24 0x0 0x14>; 1779 reg-names = "mux", 1780 "ds", 1781 "gpio"; 1782 gpio-controller; 1783 #gpio-cells = <2>; 1784 gpio-ranges = <&ao_pinctrl 0 0 15>; 1785 }; 1786 1787 i2c_ao_sck_pins: i2c_ao_sck_pins { 1788 mux { 1789 groups = "i2c_ao_sck"; 1790 function = "i2c_ao"; 1791 bias-disable; 1792 drive-strength-microamp = <3000>; 1793 }; 1794 }; 1795 1796 i2c_ao_sda_pins: i2c_ao_sda { 1797 mux { 1798 groups = "i2c_ao_sda"; 1799 function = "i2c_ao"; 1800 bias-disable; 1801 drive-strength-microamp = <3000>; 1802 }; 1803 }; 1804 1805 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1806 mux { 1807 groups = "i2c_ao_sck_e"; 1808 function = "i2c_ao"; 1809 bias-disable; 1810 drive-strength-microamp = <3000>; 1811 }; 1812 }; 1813 1814 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1815 mux { 1816 groups = "i2c_ao_sda_e"; 1817 function = "i2c_ao"; 1818 bias-disable; 1819 drive-strength-microamp = <3000>; 1820 }; 1821 }; 1822 1823 mclk0_ao_pins: mclk0-ao { 1824 mux { 1825 groups = "mclk0_ao"; 1826 function = "mclk0_ao"; 1827 bias-disable; 1828 drive-strength-microamp = <3000>; 1829 }; 1830 }; 1831 1832 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1833 mux { 1834 groups = "tdm_ao_b_din0"; 1835 function = "tdm_ao_b"; 1836 bias-disable; 1837 }; 1838 }; 1839 1840 spdif_ao_out_pins: spdif-ao-out { 1841 mux { 1842 groups = "spdif_ao_out"; 1843 function = "spdif_ao_out"; 1844 drive-strength-microamp = <500>; 1845 bias-disable; 1846 }; 1847 }; 1848 1849 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1850 mux { 1851 groups = "tdm_ao_b_din1"; 1852 function = "tdm_ao_b"; 1853 bias-disable; 1854 }; 1855 }; 1856 1857 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1858 mux { 1859 groups = "tdm_ao_b_din2"; 1860 function = "tdm_ao_b"; 1861 bias-disable; 1862 }; 1863 }; 1864 1865 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1866 mux { 1867 groups = "tdm_ao_b_dout0"; 1868 function = "tdm_ao_b"; 1869 bias-disable; 1870 drive-strength-microamp = <3000>; 1871 }; 1872 }; 1873 1874 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1875 mux { 1876 groups = "tdm_ao_b_dout1"; 1877 function = "tdm_ao_b"; 1878 bias-disable; 1879 drive-strength-microamp = <3000>; 1880 }; 1881 }; 1882 1883 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1884 mux { 1885 groups = "tdm_ao_b_dout2"; 1886 function = "tdm_ao_b"; 1887 bias-disable; 1888 drive-strength-microamp = <3000>; 1889 }; 1890 }; 1891 1892 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1893 mux { 1894 groups = "tdm_ao_b_fs"; 1895 function = "tdm_ao_b"; 1896 bias-disable; 1897 drive-strength-microamp = <3000>; 1898 }; 1899 }; 1900 1901 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1902 mux { 1903 groups = "tdm_ao_b_sclk"; 1904 function = "tdm_ao_b"; 1905 bias-disable; 1906 drive-strength-microamp = <3000>; 1907 }; 1908 }; 1909 1910 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1911 mux { 1912 groups = "tdm_ao_b_slv_fs"; 1913 function = "tdm_ao_b"; 1914 bias-disable; 1915 }; 1916 }; 1917 1918 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1919 mux { 1920 groups = "tdm_ao_b_slv_sclk"; 1921 function = "tdm_ao_b"; 1922 bias-disable; 1923 }; 1924 }; 1925 1926 uart_ao_a_pins: uart-a-ao { 1927 mux { 1928 groups = "uart_ao_a_tx", 1929 "uart_ao_a_rx"; 1930 function = "uart_ao_a"; 1931 bias-disable; 1932 }; 1933 }; 1934 1935 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1936 mux { 1937 groups = "uart_ao_a_cts", 1938 "uart_ao_a_rts"; 1939 function = "uart_ao_a"; 1940 bias-disable; 1941 }; 1942 }; 1943 1944 pwm_a_e_pins: pwm-a-e { 1945 mux { 1946 groups = "pwm_a_e"; 1947 function = "pwm_a_e"; 1948 bias-disable; 1949 }; 1950 }; 1951 1952 pwm_ao_a_pins: pwm-ao-a { 1953 mux { 1954 groups = "pwm_ao_a"; 1955 function = "pwm_ao_a"; 1956 bias-disable; 1957 }; 1958 }; 1959 1960 pwm_ao_b_pins: pwm-ao-b { 1961 mux { 1962 groups = "pwm_ao_b"; 1963 function = "pwm_ao_b"; 1964 bias-disable; 1965 }; 1966 }; 1967 1968 pwm_ao_c_4_pins: pwm-ao-c-4 { 1969 mux { 1970 groups = "pwm_ao_c_4"; 1971 function = "pwm_ao_c"; 1972 bias-disable; 1973 }; 1974 }; 1975 1976 pwm_ao_c_6_pins: pwm-ao-c-6 { 1977 mux { 1978 groups = "pwm_ao_c_6"; 1979 function = "pwm_ao_c"; 1980 bias-disable; 1981 }; 1982 }; 1983 1984 pwm_ao_d_5_pins: pwm-ao-d-5 { 1985 mux { 1986 groups = "pwm_ao_d_5"; 1987 function = "pwm_ao_d"; 1988 bias-disable; 1989 }; 1990 }; 1991 1992 pwm_ao_d_10_pins: pwm-ao-d-10 { 1993 mux { 1994 groups = "pwm_ao_d_10"; 1995 function = "pwm_ao_d"; 1996 bias-disable; 1997 }; 1998 }; 1999 2000 pwm_ao_d_e_pins: pwm-ao-d-e { 2001 mux { 2002 groups = "pwm_ao_d_e"; 2003 function = "pwm_ao_d"; 2004 }; 2005 }; 2006 2007 remote_input_ao_pins: remote-input-ao { 2008 mux { 2009 groups = "remote_ao_input"; 2010 function = "remote_ao_input"; 2011 bias-disable; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 vrtc: rtc@a8 { 2018 compatible = "amlogic,meson-vrtc"; 2019 reg = <0x0 0x000a8 0x0 0x4>; 2020 }; 2021 2022 cec_AO: cec@100 { 2023 compatible = "amlogic,meson-gx-ao-cec"; 2024 reg = <0x0 0x00100 0x0 0x14>; 2025 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2026 clocks = <&clkc_AO CLKID_AO_CEC>; 2027 clock-names = "core"; 2028 status = "disabled"; 2029 }; 2030 2031 sec_AO: ao-secure@140 { 2032 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2033 reg = <0x0 0x140 0x0 0x140>; 2034 amlogic,has-chip-id; 2035 }; 2036 2037 cecb_AO: cec@280 { 2038 compatible = "amlogic,meson-g12a-ao-cec"; 2039 reg = <0x0 0x00280 0x0 0x1c>; 2040 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2041 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2042 clock-names = "oscin"; 2043 status = "disabled"; 2044 }; 2045 2046 pwm_AO_cd: pwm@2000 { 2047 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2048 reg = <0x0 0x2000 0x0 0x20>; 2049 #pwm-cells = <3>; 2050 status = "disabled"; 2051 }; 2052 2053 uart_AO: serial@3000 { 2054 compatible = "amlogic,meson-gx-uart", 2055 "amlogic,meson-ao-uart"; 2056 reg = <0x0 0x3000 0x0 0x18>; 2057 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2058 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2059 clock-names = "xtal", "pclk", "baud"; 2060 status = "disabled"; 2061 }; 2062 2063 uart_AO_B: serial@4000 { 2064 compatible = "amlogic,meson-gx-uart", 2065 "amlogic,meson-ao-uart"; 2066 reg = <0x0 0x4000 0x0 0x18>; 2067 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2068 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2069 clock-names = "xtal", "pclk", "baud"; 2070 status = "disabled"; 2071 }; 2072 2073 i2c_AO: i2c@5000 { 2074 compatible = "amlogic,meson-axg-i2c"; 2075 status = "disabled"; 2076 reg = <0x0 0x05000 0x0 0x20>; 2077 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2078 #address-cells = <1>; 2079 #size-cells = <0>; 2080 clocks = <&clkc CLKID_I2C>; 2081 }; 2082 2083 pwm_AO_ab: pwm@7000 { 2084 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2085 reg = <0x0 0x7000 0x0 0x20>; 2086 #pwm-cells = <3>; 2087 status = "disabled"; 2088 }; 2089 2090 ir: ir@8000 { 2091 compatible = "amlogic,meson-gxbb-ir"; 2092 reg = <0x0 0x8000 0x0 0x20>; 2093 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2094 status = "disabled"; 2095 }; 2096 2097 saradc: adc@9000 { 2098 compatible = "amlogic,meson-g12a-saradc", 2099 "amlogic,meson-saradc"; 2100 reg = <0x0 0x9000 0x0 0x48>; 2101 #io-channel-cells = <1>; 2102 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2103 clocks = <&xtal>, 2104 <&clkc_AO CLKID_AO_SAR_ADC>, 2105 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2106 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2107 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2108 status = "disabled"; 2109 }; 2110 }; 2111 2112 vdec: video-decoder@ff620000 { 2113 compatible = "amlogic,g12a-vdec"; 2114 reg = <0x0 0xff620000 0x0 0x10000>, 2115 <0x0 0xffd0e180 0x0 0xe4>; 2116 reg-names = "dos", "esparser"; 2117 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2118 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2119 interrupt-names = "vdec", "esparser"; 2120 2121 amlogic,ao-sysctrl = <&rti>; 2122 amlogic,canvas = <&canvas>; 2123 2124 clocks = <&clkc CLKID_PARSER>, 2125 <&clkc CLKID_DOS>, 2126 <&clkc CLKID_VDEC_1>, 2127 <&clkc CLKID_VDEC_HEVC>, 2128 <&clkc CLKID_VDEC_HEVCF>; 2129 clock-names = "dos_parser", "dos", "vdec_1", 2130 "vdec_hevc", "vdec_hevcf"; 2131 resets = <&reset RESET_PARSER>; 2132 reset-names = "esparser"; 2133 }; 2134 2135 vpu: vpu@ff900000 { 2136 compatible = "amlogic,meson-g12a-vpu"; 2137 reg = <0x0 0xff900000 0x0 0x100000>, 2138 <0x0 0xff63c000 0x0 0x1000>; 2139 reg-names = "vpu", "hhi"; 2140 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 amlogic,canvas = <&canvas>; 2144 2145 /* CVBS VDAC output port */ 2146 cvbs_vdac_port: port@0 { 2147 reg = <0>; 2148 }; 2149 2150 /* HDMI-TX output port */ 2151 hdmi_tx_port: port@1 { 2152 reg = <1>; 2153 2154 hdmi_tx_out: endpoint { 2155 remote-endpoint = <&hdmi_tx_in>; 2156 }; 2157 }; 2158 }; 2159 2160 gic: interrupt-controller@ffc01000 { 2161 compatible = "arm,gic-400"; 2162 reg = <0x0 0xffc01000 0 0x1000>, 2163 <0x0 0xffc02000 0 0x2000>, 2164 <0x0 0xffc04000 0 0x2000>, 2165 <0x0 0xffc06000 0 0x2000>; 2166 interrupt-controller; 2167 interrupts = <GIC_PPI 9 2168 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2169 #interrupt-cells = <3>; 2170 #address-cells = <0>; 2171 }; 2172 2173 cbus: bus@ffd00000 { 2174 compatible = "simple-bus"; 2175 reg = <0x0 0xffd00000 0x0 0x100000>; 2176 #address-cells = <2>; 2177 #size-cells = <2>; 2178 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2179 2180 reset: reset-controller@1004 { 2181 compatible = "amlogic,meson-axg-reset"; 2182 reg = <0x0 0x1004 0x0 0x9c>; 2183 #reset-cells = <1>; 2184 }; 2185 2186 gpio_intc: interrupt-controller@f080 { 2187 compatible = "amlogic,meson-g12a-gpio-intc", 2188 "amlogic,meson-gpio-intc"; 2189 reg = <0x0 0xf080 0x0 0x10>; 2190 interrupt-controller; 2191 #interrupt-cells = <2>; 2192 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2193 }; 2194 2195 watchdog: watchdog@f0d0 { 2196 compatible = "amlogic,meson-gxbb-wdt"; 2197 reg = <0x0 0xf0d0 0x0 0x10>; 2198 clocks = <&xtal>; 2199 }; 2200 2201 spicc0: spi@13000 { 2202 compatible = "amlogic,meson-g12a-spicc"; 2203 reg = <0x0 0x13000 0x0 0x44>; 2204 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2205 clocks = <&clkc CLKID_SPICC0>, 2206 <&clkc CLKID_SPICC0_SCLK>; 2207 clock-names = "core", "pclk"; 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 status = "disabled"; 2211 }; 2212 2213 spicc1: spi@15000 { 2214 compatible = "amlogic,meson-g12a-spicc"; 2215 reg = <0x0 0x15000 0x0 0x44>; 2216 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2217 clocks = <&clkc CLKID_SPICC1>, 2218 <&clkc CLKID_SPICC1_SCLK>; 2219 clock-names = "core", "pclk"; 2220 #address-cells = <1>; 2221 #size-cells = <0>; 2222 status = "disabled"; 2223 }; 2224 2225 spifc: spi@14000 { 2226 compatible = "amlogic,meson-gxbb-spifc"; 2227 status = "disabled"; 2228 reg = <0x0 0x14000 0x0 0x80>; 2229 #address-cells = <1>; 2230 #size-cells = <0>; 2231 clocks = <&clkc CLKID_CLK81>; 2232 }; 2233 2234 pwm_ef: pwm@19000 { 2235 compatible = "amlogic,meson-g12a-ee-pwm"; 2236 reg = <0x0 0x19000 0x0 0x20>; 2237 #pwm-cells = <3>; 2238 status = "disabled"; 2239 }; 2240 2241 pwm_cd: pwm@1a000 { 2242 compatible = "amlogic,meson-g12a-ee-pwm"; 2243 reg = <0x0 0x1a000 0x0 0x20>; 2244 #pwm-cells = <3>; 2245 status = "disabled"; 2246 }; 2247 2248 pwm_ab: pwm@1b000 { 2249 compatible = "amlogic,meson-g12a-ee-pwm"; 2250 reg = <0x0 0x1b000 0x0 0x20>; 2251 #pwm-cells = <3>; 2252 status = "disabled"; 2253 }; 2254 2255 i2c3: i2c@1c000 { 2256 compatible = "amlogic,meson-axg-i2c"; 2257 status = "disabled"; 2258 reg = <0x0 0x1c000 0x0 0x20>; 2259 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 clocks = <&clkc CLKID_I2C>; 2263 }; 2264 2265 i2c2: i2c@1d000 { 2266 compatible = "amlogic,meson-axg-i2c"; 2267 status = "disabled"; 2268 reg = <0x0 0x1d000 0x0 0x20>; 2269 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 clocks = <&clkc CLKID_I2C>; 2273 }; 2274 2275 i2c1: i2c@1e000 { 2276 compatible = "amlogic,meson-axg-i2c"; 2277 status = "disabled"; 2278 reg = <0x0 0x1e000 0x0 0x20>; 2279 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2280 #address-cells = <1>; 2281 #size-cells = <0>; 2282 clocks = <&clkc CLKID_I2C>; 2283 }; 2284 2285 i2c0: i2c@1f000 { 2286 compatible = "amlogic,meson-axg-i2c"; 2287 status = "disabled"; 2288 reg = <0x0 0x1f000 0x0 0x20>; 2289 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 clocks = <&clkc CLKID_I2C>; 2293 }; 2294 2295 clk_msr: clock-measure@18000 { 2296 compatible = "amlogic,meson-g12a-clk-measure"; 2297 reg = <0x0 0x18000 0x0 0x10>; 2298 }; 2299 2300 uart_C: serial@22000 { 2301 compatible = "amlogic,meson-gx-uart"; 2302 reg = <0x0 0x22000 0x0 0x18>; 2303 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2304 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2305 clock-names = "xtal", "pclk", "baud"; 2306 status = "disabled"; 2307 }; 2308 2309 uart_B: serial@23000 { 2310 compatible = "amlogic,meson-gx-uart"; 2311 reg = <0x0 0x23000 0x0 0x18>; 2312 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2313 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2314 clock-names = "xtal", "pclk", "baud"; 2315 status = "disabled"; 2316 }; 2317 2318 uart_A: serial@24000 { 2319 compatible = "amlogic,meson-gx-uart"; 2320 reg = <0x0 0x24000 0x0 0x18>; 2321 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2322 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2323 clock-names = "xtal", "pclk", "baud"; 2324 status = "disabled"; 2325 fifo-size = <128>; 2326 }; 2327 }; 2328 2329 sd_emmc_a: sd@ffe03000 { 2330 compatible = "amlogic,meson-axg-mmc"; 2331 reg = <0x0 0xffe03000 0x0 0x800>; 2332 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2333 status = "disabled"; 2334 clocks = <&clkc CLKID_SD_EMMC_A>, 2335 <&clkc CLKID_SD_EMMC_A_CLK0>, 2336 <&clkc CLKID_FCLK_DIV2>; 2337 clock-names = "core", "clkin0", "clkin1"; 2338 resets = <&reset RESET_SD_EMMC_A>; 2339 }; 2340 2341 sd_emmc_b: sd@ffe05000 { 2342 compatible = "amlogic,meson-axg-mmc"; 2343 reg = <0x0 0xffe05000 0x0 0x800>; 2344 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2345 status = "disabled"; 2346 clocks = <&clkc CLKID_SD_EMMC_B>, 2347 <&clkc CLKID_SD_EMMC_B_CLK0>, 2348 <&clkc CLKID_FCLK_DIV2>; 2349 clock-names = "core", "clkin0", "clkin1"; 2350 resets = <&reset RESET_SD_EMMC_B>; 2351 }; 2352 2353 sd_emmc_c: mmc@ffe07000 { 2354 compatible = "amlogic,meson-axg-mmc"; 2355 reg = <0x0 0xffe07000 0x0 0x800>; 2356 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2357 status = "disabled"; 2358 clocks = <&clkc CLKID_SD_EMMC_C>, 2359 <&clkc CLKID_SD_EMMC_C_CLK0>, 2360 <&clkc CLKID_FCLK_DIV2>; 2361 clock-names = "core", "clkin0", "clkin1"; 2362 resets = <&reset RESET_SD_EMMC_C>; 2363 }; 2364 2365 usb: usb@ffe09000 { 2366 status = "disabled"; 2367 compatible = "amlogic,meson-g12a-usb-ctrl"; 2368 reg = <0x0 0xffe09000 0x0 0xa0>; 2369 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2370 #address-cells = <2>; 2371 #size-cells = <2>; 2372 ranges; 2373 2374 clocks = <&clkc CLKID_USB>; 2375 resets = <&reset RESET_USB>; 2376 2377 dr_mode = "otg"; 2378 2379 phys = <&usb2_phy0>, <&usb2_phy1>, 2380 <&usb3_pcie_phy PHY_TYPE_USB3>; 2381 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2382 2383 dwc2: usb@ff400000 { 2384 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2385 reg = <0x0 0xff400000 0x0 0x40000>; 2386 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2387 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2388 clock-names = "otg"; 2389 phys = <&usb2_phy1>; 2390 phy-names = "usb2-phy"; 2391 dr_mode = "peripheral"; 2392 g-rx-fifo-size = <192>; 2393 g-np-tx-fifo-size = <128>; 2394 g-tx-fifo-size = <128 128 16 16 16>; 2395 }; 2396 2397 dwc3: usb@ff500000 { 2398 compatible = "snps,dwc3"; 2399 reg = <0x0 0xff500000 0x0 0x100000>; 2400 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2401 dr_mode = "host"; 2402 snps,dis_u2_susphy_quirk; 2403 snps,quirk-frame-length-adjustment = <0x20>; 2404 snps,parkmode-disable-ss-quirk; 2405 }; 2406 }; 2407 2408 mali: gpu@ffe40000 { 2409 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2410 reg = <0x0 0xffe40000 0x0 0x40000>; 2411 interrupt-parent = <&gic>; 2412 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2413 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2414 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2415 interrupt-names = "job", "mmu", "gpu"; 2416 clocks = <&clkc CLKID_MALI>; 2417 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2418 operating-points-v2 = <&gpu_opp_table>; 2419 #cooling-cells = <2>; 2420 }; 2421 }; 2422 2423 timer { 2424 compatible = "arm,armv8-timer"; 2425 interrupts = <GIC_PPI 13 2426 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2427 <GIC_PPI 14 2428 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2429 <GIC_PPI 11 2430 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2431 <GIC_PPI 10 2432 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2433 arm,no-tick-in-suspend; 2434 }; 2435 2436 xtal: xtal-clk { 2437 compatible = "fixed-clock"; 2438 clock-frequency = <24000000>; 2439 clock-output-names = "xtal"; 2440 #clock-cells = <0>; 2441 }; 2442 2443}; 2444