1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10dma_subsys: bus@5a000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 15 16 dma_ipg_clk: clock-dma-ipg { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <120000000>; 20 clock-output-names = "dma_ipg_clk"; 21 }; 22 23 lpuart0: serial@5a060000 { 24 reg = <0x5a060000 0x1000>; 25 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 27 <&uart0_lpcg IMX_LPCG_CLK_0>; 28 clock-names = "ipg", "baud"; 29 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 30 assigned-clock-rates = <80000000>; 31 power-domains = <&pd IMX_SC_R_UART_0>; 32 status = "disabled"; 33 }; 34 35 lpuart1: serial@5a070000 { 36 reg = <0x5a070000 0x1000>; 37 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 39 <&uart1_lpcg IMX_LPCG_CLK_0>; 40 clock-names = "ipg", "baud"; 41 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 42 assigned-clock-rates = <80000000>; 43 power-domains = <&pd IMX_SC_R_UART_1>; 44 status = "disabled"; 45 }; 46 47 lpuart2: serial@5a080000 { 48 reg = <0x5a080000 0x1000>; 49 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 50 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 51 <&uart2_lpcg IMX_LPCG_CLK_0>; 52 clock-names = "ipg", "baud"; 53 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 54 assigned-clock-rates = <80000000>; 55 power-domains = <&pd IMX_SC_R_UART_2>; 56 status = "disabled"; 57 }; 58 59 lpuart3: serial@5a090000 { 60 reg = <0x5a090000 0x1000>; 61 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 63 <&uart3_lpcg IMX_LPCG_CLK_0>; 64 clock-names = "ipg", "baud"; 65 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 66 assigned-clock-rates = <80000000>; 67 power-domains = <&pd IMX_SC_R_UART_3>; 68 status = "disabled"; 69 }; 70 71 uart0_lpcg: clock-controller@5a460000 { 72 compatible = "fsl,imx8qxp-lpcg"; 73 reg = <0x5a460000 0x10000>; 74 #clock-cells = <1>; 75 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 76 <&dma_ipg_clk>; 77 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 78 clock-output-names = "uart0_lpcg_baud_clk", 79 "uart0_lpcg_ipg_clk"; 80 power-domains = <&pd IMX_SC_R_UART_0>; 81 }; 82 83 uart1_lpcg: clock-controller@5a470000 { 84 compatible = "fsl,imx8qxp-lpcg"; 85 reg = <0x5a470000 0x10000>; 86 #clock-cells = <1>; 87 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 88 <&dma_ipg_clk>; 89 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 90 clock-output-names = "uart1_lpcg_baud_clk", 91 "uart1_lpcg_ipg_clk"; 92 power-domains = <&pd IMX_SC_R_UART_1>; 93 }; 94 95 uart2_lpcg: clock-controller@5a480000 { 96 compatible = "fsl,imx8qxp-lpcg"; 97 reg = <0x5a480000 0x10000>; 98 #clock-cells = <1>; 99 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 100 <&dma_ipg_clk>; 101 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 102 clock-output-names = "uart2_lpcg_baud_clk", 103 "uart2_lpcg_ipg_clk"; 104 power-domains = <&pd IMX_SC_R_UART_2>; 105 }; 106 107 uart3_lpcg: clock-controller@5a490000 { 108 compatible = "fsl,imx8qxp-lpcg"; 109 reg = <0x5a490000 0x10000>; 110 #clock-cells = <1>; 111 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 112 <&dma_ipg_clk>; 113 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 114 clock-output-names = "uart3_lpcg_baud_clk", 115 "uart3_lpcg_ipg_clk"; 116 power-domains = <&pd IMX_SC_R_UART_3>; 117 }; 118 119 i2c0: i2c@5a800000 { 120 reg = <0x5a800000 0x4000>; 121 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>; 123 clock-names = "per"; 124 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 125 assigned-clock-rates = <24000000>; 126 power-domains = <&pd IMX_SC_R_I2C_0>; 127 status = "disabled"; 128 }; 129 130 i2c1: i2c@5a810000 { 131 reg = <0x5a810000 0x4000>; 132 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>; 134 clock-names = "per"; 135 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 136 assigned-clock-rates = <24000000>; 137 power-domains = <&pd IMX_SC_R_I2C_1>; 138 status = "disabled"; 139 }; 140 141 i2c2: i2c@5a820000 { 142 reg = <0x5a820000 0x4000>; 143 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>; 145 clock-names = "per"; 146 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 147 assigned-clock-rates = <24000000>; 148 power-domains = <&pd IMX_SC_R_I2C_2>; 149 status = "disabled"; 150 }; 151 152 i2c3: i2c@5a830000 { 153 reg = <0x5a830000 0x4000>; 154 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>; 156 clock-names = "per"; 157 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 158 assigned-clock-rates = <24000000>; 159 power-domains = <&pd IMX_SC_R_I2C_3>; 160 status = "disabled"; 161 }; 162 163 i2c0_lpcg: clock-controller@5ac00000 { 164 compatible = "fsl,imx8qxp-lpcg"; 165 reg = <0x5ac00000 0x10000>; 166 #clock-cells = <1>; 167 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 168 <&dma_ipg_clk>; 169 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 170 clock-output-names = "i2c0_lpcg_clk", 171 "i2c0_lpcg_ipg_clk"; 172 power-domains = <&pd IMX_SC_R_I2C_0>; 173 }; 174 175 i2c1_lpcg: clock-controller@5ac10000 { 176 compatible = "fsl,imx8qxp-lpcg"; 177 reg = <0x5ac10000 0x10000>; 178 #clock-cells = <1>; 179 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 180 <&dma_ipg_clk>; 181 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 182 clock-output-names = "i2c1_lpcg_clk", 183 "i2c1_lpcg_ipg_clk"; 184 power-domains = <&pd IMX_SC_R_I2C_1>; 185 }; 186 187 i2c2_lpcg: clock-controller@5ac20000 { 188 compatible = "fsl,imx8qxp-lpcg"; 189 reg = <0x5ac20000 0x10000>; 190 #clock-cells = <1>; 191 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 192 <&dma_ipg_clk>; 193 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 194 clock-output-names = "i2c2_lpcg_clk", 195 "i2c2_lpcg_ipg_clk"; 196 power-domains = <&pd IMX_SC_R_I2C_2>; 197 }; 198 199 i2c3_lpcg: clock-controller@5ac30000 { 200 compatible = "fsl,imx8qxp-lpcg"; 201 reg = <0x5ac30000 0x10000>; 202 #clock-cells = <1>; 203 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 204 <&dma_ipg_clk>; 205 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 206 clock-output-names = "i2c3_lpcg_clk", 207 "i2c3_lpcg_ipg_clk"; 208 power-domains = <&pd IMX_SC_R_I2C_3>; 209 }; 210}; 211