1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp_table10 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1200000000 { 59 opp-hz = /bits/ 64 <1200000000>; 60 clock-latency-ns = <300000>; 61 opp-suspend; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 a53_0: cpu@0 { 70 compatible = "arm,cortex-a53"; 71 reg = <0>; 72 device_type = "cpu"; 73 #cooling-cells = <2>; 74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 dynamic-power-coefficient = <277>; 78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 79 operating-points-v2 = <&cluster1_opp>; 80 }; 81 82 a53_1: cpu@1 { 83 compatible = "arm,cortex-a53"; 84 reg = <1>; 85 device_type = "cpu"; 86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 87 next-level-cache = <&L2_CA53>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 90 operating-points-v2 = <&cluster1_opp>; 91 }; 92 93 L2_CA53: cache-controller-0 { 94 compatible = "cache"; 95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 96 cache-unified; 97 cache-level = <2>; 98 }; 99 }; 100 101 extal_clk: extal { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 /* This value must be overridden by the board */ 105 clock-frequency = <0>; 106 }; 107 108 /* External PCIe clock - can be overridden by the board */ 109 pcie_bus_clk: pcie_bus { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 }; 114 115 pmu_a53 { 116 compatible = "arm,cortex-a53-pmu"; 117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 118 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-affinity = <&a53_0>, <&a53_1>; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0", "arm,psci-0.2"; 124 method = "smc"; 125 }; 126 127 /* External SCIF clock - to be overridden by boards that provide it */ 128 scif_clk: scif { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <0>; 132 }; 133 134 soc: soc { 135 compatible = "simple-bus"; 136 interrupt-parent = <&gic>; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges; 140 141 rwdt: watchdog@e6020000 { 142 compatible = "renesas,r8a774c0-wdt", 143 "renesas,rcar-gen3-wdt"; 144 reg = <0 0xe6020000 0 0x0c>; 145 clocks = <&cpg CPG_MOD 402>; 146 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 147 resets = <&cpg 402>; 148 status = "disabled"; 149 }; 150 151 gpio0: gpio@e6050000 { 152 compatible = "renesas,gpio-r8a774c0", 153 "renesas,rcar-gen3-gpio"; 154 reg = <0 0xe6050000 0 0x50>; 155 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 156 #gpio-cells = <2>; 157 gpio-controller; 158 gpio-ranges = <&pfc 0 0 18>; 159 #interrupt-cells = <2>; 160 interrupt-controller; 161 clocks = <&cpg CPG_MOD 912>; 162 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 163 resets = <&cpg 912>; 164 }; 165 166 gpio1: gpio@e6051000 { 167 compatible = "renesas,gpio-r8a774c0", 168 "renesas,rcar-gen3-gpio"; 169 reg = <0 0xe6051000 0 0x50>; 170 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 171 #gpio-cells = <2>; 172 gpio-controller; 173 gpio-ranges = <&pfc 0 32 23>; 174 #interrupt-cells = <2>; 175 interrupt-controller; 176 clocks = <&cpg CPG_MOD 911>; 177 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 178 resets = <&cpg 911>; 179 }; 180 181 gpio2: gpio@e6052000 { 182 compatible = "renesas,gpio-r8a774c0", 183 "renesas,rcar-gen3-gpio"; 184 reg = <0 0xe6052000 0 0x50>; 185 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 186 #gpio-cells = <2>; 187 gpio-controller; 188 gpio-ranges = <&pfc 0 64 26>; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 clocks = <&cpg CPG_MOD 910>; 192 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 193 resets = <&cpg 910>; 194 }; 195 196 gpio3: gpio@e6053000 { 197 compatible = "renesas,gpio-r8a774c0", 198 "renesas,rcar-gen3-gpio"; 199 reg = <0 0xe6053000 0 0x50>; 200 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 201 #gpio-cells = <2>; 202 gpio-controller; 203 gpio-ranges = <&pfc 0 96 16>; 204 #interrupt-cells = <2>; 205 interrupt-controller; 206 clocks = <&cpg CPG_MOD 909>; 207 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 208 resets = <&cpg 909>; 209 }; 210 211 gpio4: gpio@e6054000 { 212 compatible = "renesas,gpio-r8a774c0", 213 "renesas,rcar-gen3-gpio"; 214 reg = <0 0xe6054000 0 0x50>; 215 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 216 #gpio-cells = <2>; 217 gpio-controller; 218 gpio-ranges = <&pfc 0 128 11>; 219 #interrupt-cells = <2>; 220 interrupt-controller; 221 clocks = <&cpg CPG_MOD 908>; 222 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 223 resets = <&cpg 908>; 224 }; 225 226 gpio5: gpio@e6055000 { 227 compatible = "renesas,gpio-r8a774c0", 228 "renesas,rcar-gen3-gpio"; 229 reg = <0 0xe6055000 0 0x50>; 230 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 231 #gpio-cells = <2>; 232 gpio-controller; 233 gpio-ranges = <&pfc 0 160 20>; 234 #interrupt-cells = <2>; 235 interrupt-controller; 236 clocks = <&cpg CPG_MOD 907>; 237 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 238 resets = <&cpg 907>; 239 }; 240 241 gpio6: gpio@e6055400 { 242 compatible = "renesas,gpio-r8a774c0", 243 "renesas,rcar-gen3-gpio"; 244 reg = <0 0xe6055400 0 0x50>; 245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 246 #gpio-cells = <2>; 247 gpio-controller; 248 gpio-ranges = <&pfc 0 192 18>; 249 #interrupt-cells = <2>; 250 interrupt-controller; 251 clocks = <&cpg CPG_MOD 906>; 252 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 253 resets = <&cpg 906>; 254 }; 255 256 pfc: pinctrl@e6060000 { 257 compatible = "renesas,pfc-r8a774c0"; 258 reg = <0 0xe6060000 0 0x508>; 259 }; 260 261 cmt0: timer@e60f0000 { 262 compatible = "renesas,r8a774c0-cmt0", 263 "renesas,rcar-gen3-cmt0"; 264 reg = <0 0xe60f0000 0 0x1004>; 265 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 303>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 270 resets = <&cpg 303>; 271 status = "disabled"; 272 }; 273 274 cmt1: timer@e6130000 { 275 compatible = "renesas,r8a774c0-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6130000 0 0x1004>; 278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 302>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 289 resets = <&cpg 302>; 290 status = "disabled"; 291 }; 292 293 cmt2: timer@e6140000 { 294 compatible = "renesas,r8a774c0-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6140000 0 0x1004>; 297 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 301>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 308 resets = <&cpg 301>; 309 status = "disabled"; 310 }; 311 312 cmt3: timer@e6148000 { 313 compatible = "renesas,r8a774c0-cmt1", 314 "renesas,rcar-gen3-cmt1"; 315 reg = <0 0xe6148000 0 0x1004>; 316 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cpg CPG_MOD 300>; 325 clock-names = "fck"; 326 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 327 resets = <&cpg 300>; 328 status = "disabled"; 329 }; 330 331 cpg: clock-controller@e6150000 { 332 compatible = "renesas,r8a774c0-cpg-mssr"; 333 reg = <0 0xe6150000 0 0x1000>; 334 clocks = <&extal_clk>; 335 clock-names = "extal"; 336 #clock-cells = <2>; 337 #power-domain-cells = <0>; 338 #reset-cells = <1>; 339 }; 340 341 rst: reset-controller@e6160000 { 342 compatible = "renesas,r8a774c0-rst"; 343 reg = <0 0xe6160000 0 0x0200>; 344 }; 345 346 sysc: system-controller@e6180000 { 347 compatible = "renesas,r8a774c0-sysc"; 348 reg = <0 0xe6180000 0 0x0400>; 349 #power-domain-cells = <1>; 350 }; 351 352 thermal: thermal@e6190000 { 353 compatible = "renesas,thermal-r8a774c0"; 354 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 355 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 522>; 359 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 360 resets = <&cpg 522>; 361 #thermal-sensor-cells = <0>; 362 }; 363 364 intc_ex: interrupt-controller@e61c0000 { 365 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 366 #interrupt-cells = <2>; 367 interrupt-controller; 368 reg = <0 0xe61c0000 0 0x200>; 369 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 407>; 376 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 377 resets = <&cpg 407>; 378 }; 379 380 tmu0: timer@e61e0000 { 381 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 382 reg = <0 0xe61e0000 0 0x30>; 383 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cpg CPG_MOD 125>; 387 clock-names = "fck"; 388 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 389 resets = <&cpg 125>; 390 status = "disabled"; 391 }; 392 393 tmu1: timer@e6fc0000 { 394 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 395 reg = <0 0xe6fc0000 0 0x30>; 396 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 124>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 402 resets = <&cpg 124>; 403 status = "disabled"; 404 }; 405 406 tmu2: timer@e6fd0000 { 407 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 408 reg = <0 0xe6fd0000 0 0x30>; 409 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cpg CPG_MOD 123>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 415 resets = <&cpg 123>; 416 status = "disabled"; 417 }; 418 419 tmu3: timer@e6fe0000 { 420 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 421 reg = <0 0xe6fe0000 0 0x30>; 422 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 122>; 426 clock-names = "fck"; 427 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 428 resets = <&cpg 122>; 429 status = "disabled"; 430 }; 431 432 tmu4: timer@ffc00000 { 433 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 434 reg = <0 0xffc00000 0 0x30>; 435 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 121>; 439 clock-names = "fck"; 440 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 441 resets = <&cpg 121>; 442 status = "disabled"; 443 }; 444 445 i2c0: i2c@e6500000 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "renesas,i2c-r8a774c0", 449 "renesas,rcar-gen3-i2c"; 450 reg = <0 0xe6500000 0 0x40>; 451 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 931>; 453 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 454 resets = <&cpg 931>; 455 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 456 <&dmac2 0x91>, <&dmac2 0x90>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 i2c-scl-internal-delay-ns = <110>; 459 status = "disabled"; 460 }; 461 462 i2c1: i2c@e6508000 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "renesas,i2c-r8a774c0", 466 "renesas,rcar-gen3-i2c"; 467 reg = <0 0xe6508000 0 0x40>; 468 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 930>; 470 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 471 resets = <&cpg 930>; 472 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 473 <&dmac2 0x93>, <&dmac2 0x92>; 474 dma-names = "tx", "rx", "tx", "rx"; 475 i2c-scl-internal-delay-ns = <6>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@e6510000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,i2c-r8a774c0", 483 "renesas,rcar-gen3-i2c"; 484 reg = <0 0xe6510000 0 0x40>; 485 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 929>; 487 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 488 resets = <&cpg 929>; 489 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 490 <&dmac2 0x95>, <&dmac2 0x94>; 491 dma-names = "tx", "rx", "tx", "rx"; 492 i2c-scl-internal-delay-ns = <6>; 493 status = "disabled"; 494 }; 495 496 i2c3: i2c@e66d0000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "renesas,i2c-r8a774c0", 500 "renesas,rcar-gen3-i2c"; 501 reg = <0 0xe66d0000 0 0x40>; 502 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 928>; 504 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 505 resets = <&cpg 928>; 506 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 507 dma-names = "tx", "rx"; 508 i2c-scl-internal-delay-ns = <110>; 509 status = "disabled"; 510 }; 511 512 i2c4: i2c@e66d8000 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "renesas,i2c-r8a774c0", 516 "renesas,rcar-gen3-i2c"; 517 reg = <0 0xe66d8000 0 0x40>; 518 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 927>; 520 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 521 resets = <&cpg 927>; 522 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 523 dma-names = "tx", "rx"; 524 i2c-scl-internal-delay-ns = <6>; 525 status = "disabled"; 526 }; 527 528 i2c5: i2c@e66e0000 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 compatible = "renesas,i2c-r8a774c0", 532 "renesas,rcar-gen3-i2c"; 533 reg = <0 0xe66e0000 0 0x40>; 534 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cpg CPG_MOD 919>; 536 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 537 resets = <&cpg 919>; 538 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 539 dma-names = "tx", "rx"; 540 i2c-scl-internal-delay-ns = <6>; 541 status = "disabled"; 542 }; 543 544 i2c6: i2c@e66e8000 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "renesas,i2c-r8a774c0", 548 "renesas,rcar-gen3-i2c"; 549 reg = <0 0xe66e8000 0 0x40>; 550 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 918>; 552 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 553 resets = <&cpg 918>; 554 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 555 dma-names = "tx", "rx"; 556 i2c-scl-internal-delay-ns = <6>; 557 status = "disabled"; 558 }; 559 560 i2c7: i2c@e6690000 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "renesas,i2c-r8a774c0", 564 "renesas,rcar-gen3-i2c"; 565 reg = <0 0xe6690000 0 0x40>; 566 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cpg CPG_MOD 1003>; 568 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 569 resets = <&cpg 1003>; 570 i2c-scl-internal-delay-ns = <6>; 571 status = "disabled"; 572 }; 573 574 iic_pmic: i2c@e60b0000 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 compatible = "renesas,iic-r8a774c0", 578 "renesas,rcar-gen3-iic", 579 "renesas,rmobile-iic"; 580 reg = <0 0xe60b0000 0 0x425>; 581 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&cpg CPG_MOD 926>; 583 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 584 resets = <&cpg 926>; 585 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 586 dma-names = "tx", "rx"; 587 status = "disabled"; 588 }; 589 590 hscif0: serial@e6540000 { 591 compatible = "renesas,hscif-r8a774c0", 592 "renesas,rcar-gen3-hscif", 593 "renesas,hscif"; 594 reg = <0 0xe6540000 0 0x60>; 595 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cpg CPG_MOD 520>, 597 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 598 <&scif_clk>; 599 clock-names = "fck", "brg_int", "scif_clk"; 600 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 601 <&dmac2 0x31>, <&dmac2 0x30>; 602 dma-names = "tx", "rx", "tx", "rx"; 603 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 604 resets = <&cpg 520>; 605 status = "disabled"; 606 }; 607 608 hscif1: serial@e6550000 { 609 compatible = "renesas,hscif-r8a774c0", 610 "renesas,rcar-gen3-hscif", 611 "renesas,hscif"; 612 reg = <0 0xe6550000 0 0x60>; 613 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&cpg CPG_MOD 519>, 615 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 616 <&scif_clk>; 617 clock-names = "fck", "brg_int", "scif_clk"; 618 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 619 <&dmac2 0x33>, <&dmac2 0x32>; 620 dma-names = "tx", "rx", "tx", "rx"; 621 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 622 resets = <&cpg 519>; 623 status = "disabled"; 624 }; 625 626 hscif2: serial@e6560000 { 627 compatible = "renesas,hscif-r8a774c0", 628 "renesas,rcar-gen3-hscif", 629 "renesas,hscif"; 630 reg = <0 0xe6560000 0 0x60>; 631 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 518>, 633 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 634 <&scif_clk>; 635 clock-names = "fck", "brg_int", "scif_clk"; 636 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 637 <&dmac2 0x35>, <&dmac2 0x34>; 638 dma-names = "tx", "rx", "tx", "rx"; 639 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 640 resets = <&cpg 518>; 641 status = "disabled"; 642 }; 643 644 hscif3: serial@e66a0000 { 645 compatible = "renesas,hscif-r8a774c0", 646 "renesas,rcar-gen3-hscif", 647 "renesas,hscif"; 648 reg = <0 0xe66a0000 0 0x60>; 649 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 517>, 651 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 652 <&scif_clk>; 653 clock-names = "fck", "brg_int", "scif_clk"; 654 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 655 dma-names = "tx", "rx"; 656 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 657 resets = <&cpg 517>; 658 status = "disabled"; 659 }; 660 661 hscif4: serial@e66b0000 { 662 compatible = "renesas,hscif-r8a774c0", 663 "renesas,rcar-gen3-hscif", 664 "renesas,hscif"; 665 reg = <0 0xe66b0000 0 0x60>; 666 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 516>, 668 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 669 <&scif_clk>; 670 clock-names = "fck", "brg_int", "scif_clk"; 671 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 672 dma-names = "tx", "rx"; 673 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 674 resets = <&cpg 516>; 675 status = "disabled"; 676 }; 677 678 hsusb: usb@e6590000 { 679 compatible = "renesas,usbhs-r8a774c0", 680 "renesas,rcar-gen3-usbhs"; 681 reg = <0 0xe6590000 0 0x200>; 682 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 684 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 685 <&usb_dmac1 0>, <&usb_dmac1 1>; 686 dma-names = "ch0", "ch1", "ch2", "ch3"; 687 renesas,buswait = <11>; 688 phys = <&usb2_phy0 3>; 689 phy-names = "usb"; 690 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 691 resets = <&cpg 704>, <&cpg 703>; 692 status = "disabled"; 693 }; 694 695 usb_dmac0: dma-controller@e65a0000 { 696 compatible = "renesas,r8a774c0-usb-dmac", 697 "renesas,usb-dmac"; 698 reg = <0 0xe65a0000 0 0x100>; 699 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "ch0", "ch1"; 702 clocks = <&cpg CPG_MOD 330>; 703 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 704 resets = <&cpg 330>; 705 #dma-cells = <1>; 706 dma-channels = <2>; 707 }; 708 709 usb_dmac1: dma-controller@e65b0000 { 710 compatible = "renesas,r8a774c0-usb-dmac", 711 "renesas,usb-dmac"; 712 reg = <0 0xe65b0000 0 0x100>; 713 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "ch0", "ch1"; 716 clocks = <&cpg CPG_MOD 331>; 717 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 718 resets = <&cpg 331>; 719 #dma-cells = <1>; 720 dma-channels = <2>; 721 }; 722 723 dmac0: dma-controller@e6700000 { 724 compatible = "renesas,dmac-r8a774c0", 725 "renesas,rcar-dmac"; 726 reg = <0 0xe6700000 0 0x10000>; 727 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 744 interrupt-names = "error", 745 "ch0", "ch1", "ch2", "ch3", 746 "ch4", "ch5", "ch6", "ch7", 747 "ch8", "ch9", "ch10", "ch11", 748 "ch12", "ch13", "ch14", "ch15"; 749 clocks = <&cpg CPG_MOD 219>; 750 clock-names = "fck"; 751 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 752 resets = <&cpg 219>; 753 #dma-cells = <1>; 754 dma-channels = <16>; 755 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 756 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 757 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 758 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 759 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 760 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 761 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 762 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 763 }; 764 765 dmac1: dma-controller@e7300000 { 766 compatible = "renesas,dmac-r8a774c0", 767 "renesas,rcar-dmac"; 768 reg = <0 0xe7300000 0 0x10000>; 769 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "error", 787 "ch0", "ch1", "ch2", "ch3", 788 "ch4", "ch5", "ch6", "ch7", 789 "ch8", "ch9", "ch10", "ch11", 790 "ch12", "ch13", "ch14", "ch15"; 791 clocks = <&cpg CPG_MOD 218>; 792 clock-names = "fck"; 793 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 794 resets = <&cpg 218>; 795 #dma-cells = <1>; 796 dma-channels = <16>; 797 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 798 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 799 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 800 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 801 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 802 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 803 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 804 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 805 }; 806 807 dmac2: dma-controller@e7310000 { 808 compatible = "renesas,dmac-r8a774c0", 809 "renesas,rcar-dmac"; 810 reg = <0 0xe7310000 0 0x10000>; 811 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "error", 829 "ch0", "ch1", "ch2", "ch3", 830 "ch4", "ch5", "ch6", "ch7", 831 "ch8", "ch9", "ch10", "ch11", 832 "ch12", "ch13", "ch14", "ch15"; 833 clocks = <&cpg CPG_MOD 217>; 834 clock-names = "fck"; 835 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 836 resets = <&cpg 217>; 837 #dma-cells = <1>; 838 dma-channels = <16>; 839 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 840 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 841 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 842 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 843 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 844 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 845 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 846 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 847 }; 848 849 ipmmu_ds0: iommu@e6740000 { 850 compatible = "renesas,ipmmu-r8a774c0"; 851 reg = <0 0xe6740000 0 0x1000>; 852 renesas,ipmmu-main = <&ipmmu_mm 0>; 853 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 854 #iommu-cells = <1>; 855 }; 856 857 ipmmu_ds1: iommu@e7740000 { 858 compatible = "renesas,ipmmu-r8a774c0"; 859 reg = <0 0xe7740000 0 0x1000>; 860 renesas,ipmmu-main = <&ipmmu_mm 1>; 861 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 862 #iommu-cells = <1>; 863 }; 864 865 ipmmu_hc: iommu@e6570000 { 866 compatible = "renesas,ipmmu-r8a774c0"; 867 reg = <0 0xe6570000 0 0x1000>; 868 renesas,ipmmu-main = <&ipmmu_mm 2>; 869 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 870 #iommu-cells = <1>; 871 }; 872 873 ipmmu_mm: iommu@e67b0000 { 874 compatible = "renesas,ipmmu-r8a774c0"; 875 reg = <0 0xe67b0000 0 0x1000>; 876 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 879 #iommu-cells = <1>; 880 }; 881 882 ipmmu_mp: iommu@ec670000 { 883 compatible = "renesas,ipmmu-r8a774c0"; 884 reg = <0 0xec670000 0 0x1000>; 885 renesas,ipmmu-main = <&ipmmu_mm 4>; 886 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 887 #iommu-cells = <1>; 888 }; 889 890 ipmmu_pv0: iommu@fd800000 { 891 compatible = "renesas,ipmmu-r8a774c0"; 892 reg = <0 0xfd800000 0 0x1000>; 893 renesas,ipmmu-main = <&ipmmu_mm 6>; 894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 895 #iommu-cells = <1>; 896 }; 897 898 ipmmu_vc0: iommu@fe6b0000 { 899 compatible = "renesas,ipmmu-r8a774c0"; 900 reg = <0 0xfe6b0000 0 0x1000>; 901 renesas,ipmmu-main = <&ipmmu_mm 12>; 902 power-domains = <&sysc R8A774C0_PD_A3VC>; 903 #iommu-cells = <1>; 904 }; 905 906 ipmmu_vi0: iommu@febd0000 { 907 compatible = "renesas,ipmmu-r8a774c0"; 908 reg = <0 0xfebd0000 0 0x1000>; 909 renesas,ipmmu-main = <&ipmmu_mm 14>; 910 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 911 #iommu-cells = <1>; 912 }; 913 914 ipmmu_vp0: iommu@fe990000 { 915 compatible = "renesas,ipmmu-r8a774c0"; 916 reg = <0 0xfe990000 0 0x1000>; 917 renesas,ipmmu-main = <&ipmmu_mm 16>; 918 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 919 #iommu-cells = <1>; 920 }; 921 922 avb: ethernet@e6800000 { 923 compatible = "renesas,etheravb-r8a774c0", 924 "renesas,etheravb-rcar-gen3"; 925 reg = <0 0xe6800000 0 0x800>; 926 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "ch0", "ch1", "ch2", "ch3", 952 "ch4", "ch5", "ch6", "ch7", 953 "ch8", "ch9", "ch10", "ch11", 954 "ch12", "ch13", "ch14", "ch15", 955 "ch16", "ch17", "ch18", "ch19", 956 "ch20", "ch21", "ch22", "ch23", 957 "ch24"; 958 clocks = <&cpg CPG_MOD 812>; 959 clock-names = "fck"; 960 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 961 resets = <&cpg 812>; 962 phy-mode = "rgmii"; 963 rx-internal-delay-ps = <0>; 964 iommus = <&ipmmu_ds0 16>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 status = "disabled"; 968 }; 969 970 can0: can@e6c30000 { 971 compatible = "renesas,can-r8a774c0", 972 "renesas,rcar-gen3-can"; 973 reg = <0 0xe6c30000 0 0x1000>; 974 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&cpg CPG_MOD 916>, 976 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 977 <&can_clk>; 978 clock-names = "clkp1", "clkp2", "can_clk"; 979 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 980 assigned-clock-rates = <40000000>; 981 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 982 resets = <&cpg 916>; 983 status = "disabled"; 984 }; 985 986 can1: can@e6c38000 { 987 compatible = "renesas,can-r8a774c0", 988 "renesas,rcar-gen3-can"; 989 reg = <0 0xe6c38000 0 0x1000>; 990 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cpg CPG_MOD 915>, 992 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 993 <&can_clk>; 994 clock-names = "clkp1", "clkp2", "can_clk"; 995 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 996 assigned-clock-rates = <40000000>; 997 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 998 resets = <&cpg 915>; 999 status = "disabled"; 1000 }; 1001 1002 canfd: can@e66c0000 { 1003 compatible = "renesas,r8a774c0-canfd", 1004 "renesas,rcar-gen3-canfd"; 1005 reg = <0 0xe66c0000 0 0x8000>; 1006 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cpg CPG_MOD 914>, 1009 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1010 <&can_clk>; 1011 clock-names = "fck", "canfd", "can_clk"; 1012 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1013 assigned-clock-rates = <40000000>; 1014 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1015 resets = <&cpg 914>; 1016 status = "disabled"; 1017 1018 channel0 { 1019 status = "disabled"; 1020 }; 1021 1022 channel1 { 1023 status = "disabled"; 1024 }; 1025 }; 1026 1027 pwm0: pwm@e6e30000 { 1028 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1029 reg = <0 0xe6e30000 0 0x8>; 1030 clocks = <&cpg CPG_MOD 523>; 1031 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1032 resets = <&cpg 523>; 1033 #pwm-cells = <2>; 1034 status = "disabled"; 1035 }; 1036 1037 pwm1: pwm@e6e31000 { 1038 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1039 reg = <0 0xe6e31000 0 0x8>; 1040 clocks = <&cpg CPG_MOD 523>; 1041 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1042 resets = <&cpg 523>; 1043 #pwm-cells = <2>; 1044 status = "disabled"; 1045 }; 1046 1047 pwm2: pwm@e6e32000 { 1048 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1049 reg = <0 0xe6e32000 0 0x8>; 1050 clocks = <&cpg CPG_MOD 523>; 1051 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1052 resets = <&cpg 523>; 1053 #pwm-cells = <2>; 1054 status = "disabled"; 1055 }; 1056 1057 pwm3: pwm@e6e33000 { 1058 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1059 reg = <0 0xe6e33000 0 0x8>; 1060 clocks = <&cpg CPG_MOD 523>; 1061 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1062 resets = <&cpg 523>; 1063 #pwm-cells = <2>; 1064 status = "disabled"; 1065 }; 1066 1067 pwm4: pwm@e6e34000 { 1068 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1069 reg = <0 0xe6e34000 0 0x8>; 1070 clocks = <&cpg CPG_MOD 523>; 1071 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1072 resets = <&cpg 523>; 1073 #pwm-cells = <2>; 1074 status = "disabled"; 1075 }; 1076 1077 pwm5: pwm@e6e35000 { 1078 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1079 reg = <0 0xe6e35000 0 0x8>; 1080 clocks = <&cpg CPG_MOD 523>; 1081 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1082 resets = <&cpg 523>; 1083 #pwm-cells = <2>; 1084 status = "disabled"; 1085 }; 1086 1087 pwm6: pwm@e6e36000 { 1088 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1089 reg = <0 0xe6e36000 0 0x8>; 1090 clocks = <&cpg CPG_MOD 523>; 1091 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1092 resets = <&cpg 523>; 1093 #pwm-cells = <2>; 1094 status = "disabled"; 1095 }; 1096 1097 scif0: serial@e6e60000 { 1098 compatible = "renesas,scif-r8a774c0", 1099 "renesas,rcar-gen3-scif", "renesas,scif"; 1100 reg = <0 0xe6e60000 0 64>; 1101 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&cpg CPG_MOD 207>, 1103 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1104 <&scif_clk>; 1105 clock-names = "fck", "brg_int", "scif_clk"; 1106 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1107 <&dmac2 0x51>, <&dmac2 0x50>; 1108 dma-names = "tx", "rx", "tx", "rx"; 1109 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1110 resets = <&cpg 207>; 1111 status = "disabled"; 1112 }; 1113 1114 scif1: serial@e6e68000 { 1115 compatible = "renesas,scif-r8a774c0", 1116 "renesas,rcar-gen3-scif", "renesas,scif"; 1117 reg = <0 0xe6e68000 0 64>; 1118 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&cpg CPG_MOD 206>, 1120 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1121 <&scif_clk>; 1122 clock-names = "fck", "brg_int", "scif_clk"; 1123 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1124 <&dmac2 0x53>, <&dmac2 0x52>; 1125 dma-names = "tx", "rx", "tx", "rx"; 1126 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1127 resets = <&cpg 206>; 1128 status = "disabled"; 1129 }; 1130 1131 scif2: serial@e6e88000 { 1132 compatible = "renesas,scif-r8a774c0", 1133 "renesas,rcar-gen3-scif", "renesas,scif"; 1134 reg = <0 0xe6e88000 0 64>; 1135 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&cpg CPG_MOD 310>, 1137 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1138 <&scif_clk>; 1139 clock-names = "fck", "brg_int", "scif_clk"; 1140 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1141 <&dmac2 0x13>, <&dmac2 0x12>; 1142 dma-names = "tx", "rx", "tx", "rx"; 1143 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1144 resets = <&cpg 310>; 1145 status = "disabled"; 1146 }; 1147 1148 scif3: serial@e6c50000 { 1149 compatible = "renesas,scif-r8a774c0", 1150 "renesas,rcar-gen3-scif", "renesas,scif"; 1151 reg = <0 0xe6c50000 0 64>; 1152 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&cpg CPG_MOD 204>, 1154 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1155 <&scif_clk>; 1156 clock-names = "fck", "brg_int", "scif_clk"; 1157 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1158 dma-names = "tx", "rx"; 1159 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1160 resets = <&cpg 204>; 1161 status = "disabled"; 1162 }; 1163 1164 scif4: serial@e6c40000 { 1165 compatible = "renesas,scif-r8a774c0", 1166 "renesas,rcar-gen3-scif", "renesas,scif"; 1167 reg = <0 0xe6c40000 0 64>; 1168 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&cpg CPG_MOD 203>, 1170 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1171 <&scif_clk>; 1172 clock-names = "fck", "brg_int", "scif_clk"; 1173 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1174 dma-names = "tx", "rx"; 1175 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1176 resets = <&cpg 203>; 1177 status = "disabled"; 1178 }; 1179 1180 scif5: serial@e6f30000 { 1181 compatible = "renesas,scif-r8a774c0", 1182 "renesas,rcar-gen3-scif", "renesas,scif"; 1183 reg = <0 0xe6f30000 0 64>; 1184 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&cpg CPG_MOD 202>, 1186 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1187 <&scif_clk>; 1188 clock-names = "fck", "brg_int", "scif_clk"; 1189 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1190 dma-names = "tx", "rx"; 1191 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1192 resets = <&cpg 202>; 1193 status = "disabled"; 1194 }; 1195 1196 msiof0: spi@e6e90000 { 1197 compatible = "renesas,msiof-r8a774c0", 1198 "renesas,rcar-gen3-msiof"; 1199 reg = <0 0xe6e90000 0 0x0064>; 1200 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&cpg CPG_MOD 211>; 1202 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1203 <&dmac2 0x41>, <&dmac2 0x40>; 1204 dma-names = "tx", "rx", "tx", "rx"; 1205 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1206 resets = <&cpg 211>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 1212 msiof1: spi@e6ea0000 { 1213 compatible = "renesas,msiof-r8a774c0", 1214 "renesas,rcar-gen3-msiof"; 1215 reg = <0 0xe6ea0000 0 0x0064>; 1216 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&cpg CPG_MOD 210>; 1218 dmas = <&dmac0 0x43>, <&dmac0 0x42>; 1219 dma-names = "tx", "rx"; 1220 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1221 resets = <&cpg 210>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 msiof2: spi@e6c00000 { 1228 compatible = "renesas,msiof-r8a774c0", 1229 "renesas,rcar-gen3-msiof"; 1230 reg = <0 0xe6c00000 0 0x0064>; 1231 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cpg CPG_MOD 209>; 1233 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1234 dma-names = "tx", "rx"; 1235 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1236 resets = <&cpg 209>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 msiof3: spi@e6c10000 { 1243 compatible = "renesas,msiof-r8a774c0", 1244 "renesas,rcar-gen3-msiof"; 1245 reg = <0 0xe6c10000 0 0x0064>; 1246 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cpg CPG_MOD 208>; 1248 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1251 resets = <&cpg 208>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 vin4: video@e6ef4000 { 1258 compatible = "renesas,vin-r8a774c0"; 1259 reg = <0 0xe6ef4000 0 0x1000>; 1260 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&cpg CPG_MOD 807>; 1262 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1263 resets = <&cpg 807>; 1264 renesas,id = <4>; 1265 status = "disabled"; 1266 1267 ports { 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 1271 port@1 { 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 1275 reg = <1>; 1276 1277 vin4csi40: endpoint@2 { 1278 reg = <2>; 1279 remote-endpoint= <&csi40vin4>; 1280 }; 1281 }; 1282 }; 1283 }; 1284 1285 vin5: video@e6ef5000 { 1286 compatible = "renesas,vin-r8a774c0"; 1287 reg = <0 0xe6ef5000 0 0x1000>; 1288 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cpg CPG_MOD 806>; 1290 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1291 resets = <&cpg 806>; 1292 renesas,id = <5>; 1293 status = "disabled"; 1294 1295 ports { 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 1299 port@1 { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 1303 reg = <1>; 1304 1305 vin5csi40: endpoint@2 { 1306 reg = <2>; 1307 remote-endpoint= <&csi40vin5>; 1308 }; 1309 }; 1310 }; 1311 }; 1312 1313 rcar_sound: sound@ec500000 { 1314 /* 1315 * #sound-dai-cells is required 1316 * 1317 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1318 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1319 */ 1320 /* 1321 * #clock-cells is required for audio_clkout0/1/2/3 1322 * 1323 * clkout : #clock-cells = <0>; <&rcar_sound>; 1324 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1325 */ 1326 compatible = "renesas,rcar_sound-r8a774c0", 1327 "renesas,rcar_sound-gen3"; 1328 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1329 <0 0xec5a0000 0 0x100>, /* ADG */ 1330 <0 0xec540000 0 0x1000>, /* SSIU */ 1331 <0 0xec541000 0 0x280>, /* SSI */ 1332 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1333 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1334 1335 clocks = <&cpg CPG_MOD 1005>, 1336 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1337 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1338 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1339 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1340 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1341 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1342 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1343 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1344 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1345 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1346 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1347 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1348 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1349 <&audio_clk_a>, <&audio_clk_b>, 1350 <&audio_clk_c>, 1351 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1352 clock-names = "ssi-all", 1353 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1354 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1355 "ssi.1", "ssi.0", 1356 "src.9", "src.8", "src.7", "src.6", 1357 "src.5", "src.4", "src.3", "src.2", 1358 "src.1", "src.0", 1359 "mix.1", "mix.0", 1360 "ctu.1", "ctu.0", 1361 "dvc.0", "dvc.1", 1362 "clk_a", "clk_b", "clk_c", "clk_i"; 1363 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1364 resets = <&cpg 1005>, 1365 <&cpg 1006>, <&cpg 1007>, 1366 <&cpg 1008>, <&cpg 1009>, 1367 <&cpg 1010>, <&cpg 1011>, 1368 <&cpg 1012>, <&cpg 1013>, 1369 <&cpg 1014>, <&cpg 1015>; 1370 reset-names = "ssi-all", 1371 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1372 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1373 "ssi.1", "ssi.0"; 1374 status = "disabled"; 1375 1376 rcar_sound,ctu { 1377 ctu00: ctu-0 { }; 1378 ctu01: ctu-1 { }; 1379 ctu02: ctu-2 { }; 1380 ctu03: ctu-3 { }; 1381 ctu10: ctu-4 { }; 1382 ctu11: ctu-5 { }; 1383 ctu12: ctu-6 { }; 1384 ctu13: ctu-7 { }; 1385 }; 1386 1387 rcar_sound,dvc { 1388 dvc0: dvc-0 { 1389 dmas = <&audma0 0xbc>; 1390 dma-names = "tx"; 1391 }; 1392 dvc1: dvc-1 { 1393 dmas = <&audma0 0xbe>; 1394 dma-names = "tx"; 1395 }; 1396 }; 1397 1398 rcar_sound,mix { 1399 mix0: mix-0 { }; 1400 mix1: mix-1 { }; 1401 }; 1402 1403 rcar_sound,src { 1404 src0: src-0 { 1405 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1407 dma-names = "rx", "tx"; 1408 }; 1409 src1: src-1 { 1410 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1412 dma-names = "rx", "tx"; 1413 }; 1414 src2: src-2 { 1415 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1417 dma-names = "rx", "tx"; 1418 }; 1419 src3: src-3 { 1420 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1421 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 src4: src-4 { 1425 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1427 dma-names = "rx", "tx"; 1428 }; 1429 src5: src-5 { 1430 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1432 dma-names = "rx", "tx"; 1433 }; 1434 src6: src-6 { 1435 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1437 dma-names = "rx", "tx"; 1438 }; 1439 src7: src-7 { 1440 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 src8: src-8 { 1445 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1446 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1447 dma-names = "rx", "tx"; 1448 }; 1449 src9: src-9 { 1450 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1451 dmas = <&audma0 0x97>, <&audma0 0xba>; 1452 dma-names = "rx", "tx"; 1453 }; 1454 }; 1455 1456 rcar_sound,ssi { 1457 ssi0: ssi-0 { 1458 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1459 dmas = <&audma0 0x01>, <&audma0 0x02>, 1460 <&audma0 0x15>, <&audma0 0x16>; 1461 dma-names = "rx", "tx", "rxu", "txu"; 1462 }; 1463 ssi1: ssi-1 { 1464 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1465 dmas = <&audma0 0x03>, <&audma0 0x04>, 1466 <&audma0 0x49>, <&audma0 0x4a>; 1467 dma-names = "rx", "tx", "rxu", "txu"; 1468 }; 1469 ssi2: ssi-2 { 1470 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1471 dmas = <&audma0 0x05>, <&audma0 0x06>, 1472 <&audma0 0x63>, <&audma0 0x64>; 1473 dma-names = "rx", "tx", "rxu", "txu"; 1474 }; 1475 ssi3: ssi-3 { 1476 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1477 dmas = <&audma0 0x07>, <&audma0 0x08>, 1478 <&audma0 0x6f>, <&audma0 0x70>; 1479 dma-names = "rx", "tx", "rxu", "txu"; 1480 }; 1481 ssi4: ssi-4 { 1482 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1483 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1484 <&audma0 0x71>, <&audma0 0x72>; 1485 dma-names = "rx", "tx", "rxu", "txu"; 1486 }; 1487 ssi5: ssi-5 { 1488 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1489 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1490 <&audma0 0x73>, <&audma0 0x74>; 1491 dma-names = "rx", "tx", "rxu", "txu"; 1492 }; 1493 ssi6: ssi-6 { 1494 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1495 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1496 <&audma0 0x75>, <&audma0 0x76>; 1497 dma-names = "rx", "tx", "rxu", "txu"; 1498 }; 1499 ssi7: ssi-7 { 1500 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1501 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1502 <&audma0 0x79>, <&audma0 0x7a>; 1503 dma-names = "rx", "tx", "rxu", "txu"; 1504 }; 1505 ssi8: ssi-8 { 1506 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1507 dmas = <&audma0 0x11>, <&audma0 0x12>, 1508 <&audma0 0x7b>, <&audma0 0x7c>; 1509 dma-names = "rx", "tx", "rxu", "txu"; 1510 }; 1511 ssi9: ssi-9 { 1512 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1513 dmas = <&audma0 0x13>, <&audma0 0x14>, 1514 <&audma0 0x7d>, <&audma0 0x7e>; 1515 dma-names = "rx", "tx", "rxu", "txu"; 1516 }; 1517 }; 1518 }; 1519 1520 audma0: dma-controller@ec700000 { 1521 compatible = "renesas,dmac-r8a774c0", 1522 "renesas,rcar-dmac"; 1523 reg = <0 0xec700000 0 0x10000>; 1524 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1541 interrupt-names = "error", 1542 "ch0", "ch1", "ch2", "ch3", 1543 "ch4", "ch5", "ch6", "ch7", 1544 "ch8", "ch9", "ch10", "ch11", 1545 "ch12", "ch13", "ch14", "ch15"; 1546 clocks = <&cpg CPG_MOD 502>; 1547 clock-names = "fck"; 1548 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1549 resets = <&cpg 502>; 1550 #dma-cells = <1>; 1551 dma-channels = <16>; 1552 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1553 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1554 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1555 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1556 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1557 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1558 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1559 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1560 }; 1561 1562 xhci0: usb@ee000000 { 1563 compatible = "renesas,xhci-r8a774c0", 1564 "renesas,rcar-gen3-xhci"; 1565 reg = <0 0xee000000 0 0xc00>; 1566 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&cpg CPG_MOD 328>; 1568 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1569 resets = <&cpg 328>; 1570 status = "disabled"; 1571 }; 1572 1573 usb3_peri0: usb@ee020000 { 1574 compatible = "renesas,r8a774c0-usb3-peri", 1575 "renesas,rcar-gen3-usb3-peri"; 1576 reg = <0 0xee020000 0 0x400>; 1577 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&cpg CPG_MOD 328>; 1579 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1580 resets = <&cpg 328>; 1581 status = "disabled"; 1582 }; 1583 1584 ohci0: usb@ee080000 { 1585 compatible = "generic-ohci"; 1586 reg = <0 0xee080000 0 0x100>; 1587 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1589 phys = <&usb2_phy0 1>; 1590 phy-names = "usb"; 1591 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1592 resets = <&cpg 703>, <&cpg 704>; 1593 status = "disabled"; 1594 }; 1595 1596 ehci0: usb@ee080100 { 1597 compatible = "generic-ehci"; 1598 reg = <0 0xee080100 0 0x100>; 1599 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1601 phys = <&usb2_phy0 2>; 1602 phy-names = "usb"; 1603 companion = <&ohci0>; 1604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1605 resets = <&cpg 703>, <&cpg 704>; 1606 status = "disabled"; 1607 }; 1608 1609 usb2_phy0: usb-phy@ee080200 { 1610 compatible = "renesas,usb2-phy-r8a774c0", 1611 "renesas,rcar-gen3-usb2-phy"; 1612 reg = <0 0xee080200 0 0x700>; 1613 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1615 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1616 resets = <&cpg 703>, <&cpg 704>; 1617 #phy-cells = <1>; 1618 status = "disabled"; 1619 }; 1620 1621 sdhi0: mmc@ee100000 { 1622 compatible = "renesas,sdhi-r8a774c0", 1623 "renesas,rcar-gen3-sdhi"; 1624 reg = <0 0xee100000 0 0x2000>; 1625 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cpg CPG_MOD 314>; 1627 max-frequency = <200000000>; 1628 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1629 resets = <&cpg 314>; 1630 status = "disabled"; 1631 }; 1632 1633 sdhi1: mmc@ee120000 { 1634 compatible = "renesas,sdhi-r8a774c0", 1635 "renesas,rcar-gen3-sdhi"; 1636 reg = <0 0xee120000 0 0x2000>; 1637 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&cpg CPG_MOD 313>; 1639 max-frequency = <200000000>; 1640 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1641 resets = <&cpg 313>; 1642 status = "disabled"; 1643 }; 1644 1645 sdhi3: mmc@ee160000 { 1646 compatible = "renesas,sdhi-r8a774c0", 1647 "renesas,rcar-gen3-sdhi"; 1648 reg = <0 0xee160000 0 0x2000>; 1649 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&cpg CPG_MOD 311>; 1651 max-frequency = <200000000>; 1652 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1653 resets = <&cpg 311>; 1654 status = "disabled"; 1655 }; 1656 1657 rpc: spi@ee200000 { 1658 compatible = "renesas,r8a774c0-rpc-if", 1659 "renesas,rcar-gen3-rpc-if"; 1660 reg = <0 0xee200000 0 0x200>, 1661 <0 0x08000000 0 0x4000000>, 1662 <0 0xee208000 0 0x100>; 1663 reg-names = "regs", "dirmap", "wbuf"; 1664 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&cpg CPG_MOD 917>; 1666 clock-names = "rpc"; 1667 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1668 resets = <&cpg 917>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 status = "disabled"; 1672 }; 1673 1674 gic: interrupt-controller@f1010000 { 1675 compatible = "arm,gic-400"; 1676 #interrupt-cells = <3>; 1677 #address-cells = <0>; 1678 interrupt-controller; 1679 reg = <0x0 0xf1010000 0 0x1000>, 1680 <0x0 0xf1020000 0 0x20000>, 1681 <0x0 0xf1040000 0 0x20000>, 1682 <0x0 0xf1060000 0 0x20000>; 1683 interrupts = <GIC_PPI 9 1684 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1685 clocks = <&cpg CPG_MOD 408>; 1686 clock-names = "clk"; 1687 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1688 resets = <&cpg 408>; 1689 }; 1690 1691 pciec0: pcie@fe000000 { 1692 compatible = "renesas,pcie-r8a774c0", 1693 "renesas,pcie-rcar-gen3"; 1694 reg = <0 0xfe000000 0 0x80000>; 1695 #address-cells = <3>; 1696 #size-cells = <2>; 1697 bus-range = <0x00 0xff>; 1698 device_type = "pci"; 1699 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1700 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1701 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1702 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1703 /* Map all possible DDR as inbound ranges */ 1704 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1705 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1708 #interrupt-cells = <1>; 1709 interrupt-map-mask = <0 0 0 0>; 1710 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1712 clock-names = "pcie", "pcie_bus"; 1713 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1714 resets = <&cpg 319>; 1715 status = "disabled"; 1716 }; 1717 1718 pciec0_ep: pcie-ep@fe000000 { 1719 compatible = "renesas,r8a774c0-pcie-ep", 1720 "renesas,rcar-gen3-pcie-ep"; 1721 reg = <0x0 0xfe000000 0 0x80000>, 1722 <0x0 0xfe100000 0 0x100000>, 1723 <0x0 0xfe200000 0 0x200000>, 1724 <0x0 0x30000000 0 0x8000000>, 1725 <0x0 0x38000000 0 0x8000000>; 1726 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 1727 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&cpg CPG_MOD 319>; 1731 clock-names = "pcie"; 1732 resets = <&cpg 319>; 1733 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1734 status = "disabled"; 1735 }; 1736 1737 vspb0: vsp@fe960000 { 1738 compatible = "renesas,vsp2"; 1739 reg = <0 0xfe960000 0 0x8000>; 1740 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1741 clocks = <&cpg CPG_MOD 626>; 1742 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1743 resets = <&cpg 626>; 1744 renesas,fcp = <&fcpvb0>; 1745 }; 1746 1747 vspd0: vsp@fea20000 { 1748 compatible = "renesas,vsp2"; 1749 reg = <0 0xfea20000 0 0x7000>; 1750 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1751 clocks = <&cpg CPG_MOD 623>; 1752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1753 resets = <&cpg 623>; 1754 renesas,fcp = <&fcpvd0>; 1755 }; 1756 1757 vspd1: vsp@fea28000 { 1758 compatible = "renesas,vsp2"; 1759 reg = <0 0xfea28000 0 0x7000>; 1760 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&cpg CPG_MOD 622>; 1762 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1763 resets = <&cpg 622>; 1764 renesas,fcp = <&fcpvd1>; 1765 }; 1766 1767 vspi0: vsp@fe9a0000 { 1768 compatible = "renesas,vsp2"; 1769 reg = <0 0xfe9a0000 0 0x8000>; 1770 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1771 clocks = <&cpg CPG_MOD 631>; 1772 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1773 resets = <&cpg 631>; 1774 renesas,fcp = <&fcpvi0>; 1775 }; 1776 1777 fcpvb0: fcp@fe96f000 { 1778 compatible = "renesas,fcpv"; 1779 reg = <0 0xfe96f000 0 0x200>; 1780 clocks = <&cpg CPG_MOD 607>; 1781 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1782 resets = <&cpg 607>; 1783 iommus = <&ipmmu_vp0 5>; 1784 }; 1785 1786 fcpvd0: fcp@fea27000 { 1787 compatible = "renesas,fcpv"; 1788 reg = <0 0xfea27000 0 0x200>; 1789 clocks = <&cpg CPG_MOD 603>; 1790 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1791 resets = <&cpg 603>; 1792 iommus = <&ipmmu_vi0 8>; 1793 }; 1794 1795 fcpvd1: fcp@fea2f000 { 1796 compatible = "renesas,fcpv"; 1797 reg = <0 0xfea2f000 0 0x200>; 1798 clocks = <&cpg CPG_MOD 602>; 1799 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1800 resets = <&cpg 602>; 1801 iommus = <&ipmmu_vi0 9>; 1802 }; 1803 1804 fcpvi0: fcp@fe9af000 { 1805 compatible = "renesas,fcpv"; 1806 reg = <0 0xfe9af000 0 0x200>; 1807 clocks = <&cpg CPG_MOD 611>; 1808 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1809 resets = <&cpg 611>; 1810 iommus = <&ipmmu_vp0 8>; 1811 }; 1812 1813 csi40: csi2@feaa0000 { 1814 compatible = "renesas,r8a774c0-csi2"; 1815 reg = <0 0xfeaa0000 0 0x10000>; 1816 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&cpg CPG_MOD 716>; 1818 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1819 resets = <&cpg 716>; 1820 status = "disabled"; 1821 1822 ports { 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 port@0 { 1827 reg = <0>; 1828 }; 1829 1830 port@1 { 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 reg = <1>; 1835 1836 csi40vin4: endpoint@0 { 1837 reg = <0>; 1838 remote-endpoint = <&vin4csi40>; 1839 }; 1840 csi40vin5: endpoint@1 { 1841 reg = <1>; 1842 remote-endpoint = <&vin5csi40>; 1843 }; 1844 }; 1845 }; 1846 }; 1847 1848 du: display@feb00000 { 1849 compatible = "renesas,du-r8a774c0"; 1850 reg = <0 0xfeb00000 0 0x40000>; 1851 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1854 clock-names = "du.0", "du.1"; 1855 resets = <&cpg 724>; 1856 reset-names = "du.0"; 1857 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1858 1859 status = "disabled"; 1860 1861 ports { 1862 #address-cells = <1>; 1863 #size-cells = <0>; 1864 1865 port@0 { 1866 reg = <0>; 1867 du_out_rgb: endpoint { 1868 }; 1869 }; 1870 1871 port@1 { 1872 reg = <1>; 1873 du_out_lvds0: endpoint { 1874 remote-endpoint = <&lvds0_in>; 1875 }; 1876 }; 1877 1878 port@2 { 1879 reg = <2>; 1880 du_out_lvds1: endpoint { 1881 remote-endpoint = <&lvds1_in>; 1882 }; 1883 }; 1884 }; 1885 }; 1886 1887 lvds0: lvds-encoder@feb90000 { 1888 compatible = "renesas,r8a774c0-lvds"; 1889 reg = <0 0xfeb90000 0 0x20>; 1890 clocks = <&cpg CPG_MOD 727>; 1891 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1892 resets = <&cpg 727>; 1893 status = "disabled"; 1894 1895 renesas,companion = <&lvds1>; 1896 1897 ports { 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 port@0 { 1902 reg = <0>; 1903 lvds0_in: endpoint { 1904 remote-endpoint = <&du_out_lvds0>; 1905 }; 1906 }; 1907 1908 port@1 { 1909 reg = <1>; 1910 lvds0_out: endpoint { 1911 }; 1912 }; 1913 }; 1914 }; 1915 1916 lvds1: lvds-encoder@feb90100 { 1917 compatible = "renesas,r8a774c0-lvds"; 1918 reg = <0 0xfeb90100 0 0x20>; 1919 clocks = <&cpg CPG_MOD 727>; 1920 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1921 resets = <&cpg 726>; 1922 status = "disabled"; 1923 1924 ports { 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 1928 port@0 { 1929 reg = <0>; 1930 lvds1_in: endpoint { 1931 remote-endpoint = <&du_out_lvds1>; 1932 }; 1933 }; 1934 1935 port@1 { 1936 reg = <1>; 1937 lvds1_out: endpoint { 1938 }; 1939 }; 1940 }; 1941 }; 1942 1943 prr: chipid@fff00044 { 1944 compatible = "renesas,prr"; 1945 reg = <0 0xfff00044 0 4>; 1946 }; 1947 }; 1948 1949 thermal-zones { 1950 cpu-thermal { 1951 polling-delay-passive = <250>; 1952 polling-delay = <0>; 1953 thermal-sensors = <&thermal>; 1954 sustainable-power = <717>; 1955 1956 cooling-maps { 1957 map0 { 1958 trip = <&target>; 1959 cooling-device = <&a53_0 0 2>; 1960 contribution = <1024>; 1961 }; 1962 }; 1963 1964 trips { 1965 sensor1_crit: sensor1-crit { 1966 temperature = <120000>; 1967 hysteresis = <2000>; 1968 type = "critical"; 1969 }; 1970 1971 target: trip-point1 { 1972 temperature = <100000>; 1973 hysteresis = <2000>; 1974 type = "passive"; 1975 }; 1976 }; 1977 }; 1978 }; 1979 1980 timer { 1981 compatible = "arm,armv8-timer"; 1982 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1983 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1984 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1985 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1986 }; 1987 1988 /* External USB clocks - can be overridden by the board */ 1989 usb3s0_clk: usb3s0 { 1990 compatible = "fixed-clock"; 1991 #clock-cells = <0>; 1992 clock-frequency = <0>; 1993 }; 1994 1995 usb_extal_clk: usb_extal { 1996 compatible = "fixed-clock"; 1997 #clock-cells = <0>; 1998 clock-frequency = <0>; 1999 }; 2000}; 2001