1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 power-domain@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 #power-domain-cells = <0>; 254 }; 255 power-domain@PX30_PD_SDCARD { 256 reg = <PX30_PD_SDCARD>; 257 clocks = <&cru HCLK_SDMMC>, 258 <&cru SCLK_SDMMC>; 259 pm_qos = <&qos_sdmmc>; 260 #power-domain-cells = <0>; 261 }; 262 power-domain@PX30_PD_GMAC { 263 reg = <PX30_PD_GMAC>; 264 clocks = <&cru ACLK_GMAC>, 265 <&cru PCLK_GMAC>, 266 <&cru SCLK_MAC_REF>, 267 <&cru SCLK_GMAC_RX_TX>; 268 pm_qos = <&qos_gmac>; 269 #power-domain-cells = <0>; 270 }; 271 power-domain@PX30_PD_MMC_NAND { 272 reg = <PX30_PD_MMC_NAND>; 273 clocks = <&cru HCLK_NANDC>, 274 <&cru HCLK_EMMC>, 275 <&cru HCLK_SDIO>, 276 <&cru HCLK_SFC>, 277 <&cru SCLK_EMMC>, 278 <&cru SCLK_NANDC>, 279 <&cru SCLK_SDIO>, 280 <&cru SCLK_SFC>; 281 pm_qos = <&qos_emmc>, <&qos_nand>, 282 <&qos_sdio>, <&qos_sfc>; 283 #power-domain-cells = <0>; 284 }; 285 power-domain@PX30_PD_VPU { 286 reg = <PX30_PD_VPU>; 287 clocks = <&cru ACLK_VPU>, 288 <&cru HCLK_VPU>, 289 <&cru SCLK_CORE_VPU>; 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 291 #power-domain-cells = <0>; 292 }; 293 power-domain@PX30_PD_VO { 294 reg = <PX30_PD_VO>; 295 clocks = <&cru ACLK_RGA>, 296 <&cru ACLK_VOPB>, 297 <&cru ACLK_VOPL>, 298 <&cru DCLK_VOPB>, 299 <&cru DCLK_VOPL>, 300 <&cru HCLK_RGA>, 301 <&cru HCLK_VOPB>, 302 <&cru HCLK_VOPL>, 303 <&cru PCLK_MIPI_DSI>, 304 <&cru SCLK_RGA_CORE>, 305 <&cru SCLK_VOPB_PWM>; 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 307 <&qos_vop_m0>, <&qos_vop_m1>; 308 #power-domain-cells = <0>; 309 }; 310 power-domain@PX30_PD_VI { 311 reg = <PX30_PD_VI>; 312 clocks = <&cru ACLK_CIF>, 313 <&cru ACLK_ISP>, 314 <&cru HCLK_CIF>, 315 <&cru HCLK_ISP>, 316 <&cru SCLK_ISP>; 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 318 <&qos_isp_wr>, <&qos_isp_m1>, 319 <&qos_vip>; 320 #power-domain-cells = <0>; 321 }; 322 power-domain@PX30_PD_GPU { 323 reg = <PX30_PD_GPU>; 324 clocks = <&cru SCLK_GPU>; 325 pm_qos = <&qos_gpu>; 326 #power-domain-cells = <0>; 327 }; 328 }; 329 }; 330 331 pmugrf: syscon@ff010000 { 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 333 reg = <0x0 0xff010000 0x0 0x1000>; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 337 pmu_io_domains: io-domains { 338 compatible = "rockchip,px30-pmu-io-voltage-domain"; 339 status = "disabled"; 340 }; 341 342 reboot-mode { 343 compatible = "syscon-reboot-mode"; 344 offset = <0x200>; 345 mode-bootloader = <BOOT_BL_DOWNLOAD>; 346 mode-fastboot = <BOOT_FASTBOOT>; 347 mode-loader = <BOOT_BL_DOWNLOAD>; 348 mode-normal = <BOOT_NORMAL>; 349 mode-recovery = <BOOT_RECOVERY>; 350 }; 351 }; 352 353 uart0: serial@ff030000 { 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 355 reg = <0x0 0xff030000 0x0 0x100>; 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 358 clock-names = "baudclk", "apb_pclk"; 359 dmas = <&dmac 0>, <&dmac 1>; 360 dma-names = "tx", "rx"; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 365 status = "disabled"; 366 }; 367 368 i2s1_2ch: i2s@ff070000 { 369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 370 reg = <0x0 0xff070000 0x0 0x1000>; 371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 373 clock-names = "i2s_clk", "i2s_hclk"; 374 dmas = <&dmac 18>, <&dmac 19>; 375 dma-names = "tx", "rx"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 378 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 379 #sound-dai-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2s2_2ch: i2s@ff080000 { 384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 385 reg = <0x0 0xff080000 0x0 0x1000>; 386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 388 clock-names = "i2s_clk", "i2s_hclk"; 389 dmas = <&dmac 20>, <&dmac 21>; 390 dma-names = "tx", "rx"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 393 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 394 #sound-dai-cells = <0>; 395 status = "disabled"; 396 }; 397 398 gic: interrupt-controller@ff131000 { 399 compatible = "arm,gic-400"; 400 #interrupt-cells = <3>; 401 #address-cells = <0>; 402 interrupt-controller; 403 reg = <0x0 0xff131000 0 0x1000>, 404 <0x0 0xff132000 0 0x2000>, 405 <0x0 0xff134000 0 0x2000>, 406 <0x0 0xff136000 0 0x2000>; 407 interrupts = <GIC_PPI 9 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 409 }; 410 411 grf: syscon@ff140000 { 412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 413 reg = <0x0 0xff140000 0x0 0x1000>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 io_domains: io-domains { 418 compatible = "rockchip,px30-io-voltage-domain"; 419 status = "disabled"; 420 }; 421 422 lvds: lvds { 423 compatible = "rockchip,px30-lvds"; 424 phys = <&dsi_dphy>; 425 phy-names = "dphy"; 426 rockchip,grf = <&grf>; 427 rockchip,output = "lvds"; 428 status = "disabled"; 429 430 ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 439 lvds_vopb_in: endpoint@0 { 440 reg = <0>; 441 remote-endpoint = <&vopb_out_lvds>; 442 }; 443 444 lvds_vopl_in: endpoint@1 { 445 reg = <1>; 446 remote-endpoint = <&vopl_out_lvds>; 447 }; 448 }; 449 }; 450 }; 451 }; 452 453 uart1: serial@ff158000 { 454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 455 reg = <0x0 0xff158000 0x0 0x100>; 456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 458 clock-names = "baudclk", "apb_pclk"; 459 dmas = <&dmac 2>, <&dmac 3>; 460 dma-names = "tx", "rx"; 461 reg-shift = <2>; 462 reg-io-width = <4>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 465 status = "disabled"; 466 }; 467 468 uart2: serial@ff160000 { 469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 470 reg = <0x0 0xff160000 0x0 0x100>; 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 473 clock-names = "baudclk", "apb_pclk"; 474 dmas = <&dmac 4>, <&dmac 5>; 475 dma-names = "tx", "rx"; 476 reg-shift = <2>; 477 reg-io-width = <4>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&uart2m0_xfer>; 480 status = "disabled"; 481 }; 482 483 uart3: serial@ff168000 { 484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 485 reg = <0x0 0xff168000 0x0 0x100>; 486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 488 clock-names = "baudclk", "apb_pclk"; 489 dmas = <&dmac 6>, <&dmac 7>; 490 dma-names = "tx", "rx"; 491 reg-shift = <2>; 492 reg-io-width = <4>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 495 status = "disabled"; 496 }; 497 498 uart4: serial@ff170000 { 499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 500 reg = <0x0 0xff170000 0x0 0x100>; 501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 503 clock-names = "baudclk", "apb_pclk"; 504 dmas = <&dmac 8>, <&dmac 9>; 505 dma-names = "tx", "rx"; 506 reg-shift = <2>; 507 reg-io-width = <4>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 510 status = "disabled"; 511 }; 512 513 uart5: serial@ff178000 { 514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 515 reg = <0x0 0xff178000 0x0 0x100>; 516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 518 clock-names = "baudclk", "apb_pclk"; 519 dmas = <&dmac 10>, <&dmac 11>; 520 dma-names = "tx", "rx"; 521 reg-shift = <2>; 522 reg-io-width = <4>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 525 status = "disabled"; 526 }; 527 528 i2c0: i2c@ff180000 { 529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 530 reg = <0x0 0xff180000 0x0 0x1000>; 531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 532 clock-names = "i2c", "pclk"; 533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c0_xfer>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c1: i2c@ff190000 { 542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 543 reg = <0x0 0xff190000 0x0 0x1000>; 544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 545 clock-names = "i2c", "pclk"; 546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c1_xfer>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 i2c2: i2c@ff1a0000 { 555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 556 reg = <0x0 0xff1a0000 0x0 0x1000>; 557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 558 clock-names = "i2c", "pclk"; 559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c2_xfer>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 i2c3: i2c@ff1b0000 { 568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 569 reg = <0x0 0xff1b0000 0x0 0x1000>; 570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 571 clock-names = "i2c", "pclk"; 572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&i2c3_xfer>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 spi0: spi@ff1d0000 { 581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 582 reg = <0x0 0xff1d0000 0x0 0x1000>; 583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 585 clock-names = "spiclk", "apb_pclk"; 586 dmas = <&dmac 12>, <&dmac 13>; 587 dma-names = "tx", "rx"; 588 num-cs = <2>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 spi1: spi@ff1d8000 { 597 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 598 reg = <0x0 0xff1d8000 0x0 0x1000>; 599 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 601 clock-names = "spiclk", "apb_pclk"; 602 dmas = <&dmac 14>, <&dmac 15>; 603 dma-names = "tx", "rx"; 604 num-cs = <2>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 status = "disabled"; 610 }; 611 612 wdt: watchdog@ff1e0000 { 613 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 614 reg = <0x0 0xff1e0000 0x0 0x100>; 615 clocks = <&cru PCLK_WDT_NS>; 616 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 617 status = "disabled"; 618 }; 619 620 pwm0: pwm@ff200000 { 621 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 622 reg = <0x0 0xff200000 0x0 0x10>; 623 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 624 clock-names = "pwm", "pclk"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pwm0_pin>; 627 #pwm-cells = <3>; 628 status = "disabled"; 629 }; 630 631 pwm1: pwm@ff200010 { 632 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 633 reg = <0x0 0xff200010 0x0 0x10>; 634 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 635 clock-names = "pwm", "pclk"; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pwm1_pin>; 638 #pwm-cells = <3>; 639 status = "disabled"; 640 }; 641 642 pwm2: pwm@ff200020 { 643 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 644 reg = <0x0 0xff200020 0x0 0x10>; 645 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 646 clock-names = "pwm", "pclk"; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&pwm2_pin>; 649 #pwm-cells = <3>; 650 status = "disabled"; 651 }; 652 653 pwm3: pwm@ff200030 { 654 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 655 reg = <0x0 0xff200030 0x0 0x10>; 656 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 657 clock-names = "pwm", "pclk"; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pwm3_pin>; 660 #pwm-cells = <3>; 661 status = "disabled"; 662 }; 663 664 pwm4: pwm@ff208000 { 665 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 666 reg = <0x0 0xff208000 0x0 0x10>; 667 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 668 clock-names = "pwm", "pclk"; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&pwm4_pin>; 671 #pwm-cells = <3>; 672 status = "disabled"; 673 }; 674 675 pwm5: pwm@ff208010 { 676 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 677 reg = <0x0 0xff208010 0x0 0x10>; 678 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 679 clock-names = "pwm", "pclk"; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pwm5_pin>; 682 #pwm-cells = <3>; 683 status = "disabled"; 684 }; 685 686 pwm6: pwm@ff208020 { 687 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 688 reg = <0x0 0xff208020 0x0 0x10>; 689 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 690 clock-names = "pwm", "pclk"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pwm6_pin>; 693 #pwm-cells = <3>; 694 status = "disabled"; 695 }; 696 697 pwm7: pwm@ff208030 { 698 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 699 reg = <0x0 0xff208030 0x0 0x10>; 700 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 701 clock-names = "pwm", "pclk"; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pwm7_pin>; 704 #pwm-cells = <3>; 705 status = "disabled"; 706 }; 707 708 rktimer: timer@ff210000 { 709 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 710 reg = <0x0 0xff210000 0x0 0x1000>; 711 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 713 clock-names = "pclk", "timer"; 714 }; 715 716 dmac: dma-controller@ff240000 { 717 compatible = "arm,pl330", "arm,primecell"; 718 reg = <0x0 0xff240000 0x0 0x4000>; 719 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 721 arm,pl330-periph-burst; 722 clocks = <&cru ACLK_DMAC>; 723 clock-names = "apb_pclk"; 724 #dma-cells = <1>; 725 }; 726 727 tsadc: tsadc@ff280000 { 728 compatible = "rockchip,px30-tsadc"; 729 reg = <0x0 0xff280000 0x0 0x100>; 730 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 731 assigned-clocks = <&cru SCLK_TSADC>; 732 assigned-clock-rates = <50000>; 733 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 734 clock-names = "tsadc", "apb_pclk"; 735 resets = <&cru SRST_TSADC>; 736 reset-names = "tsadc-apb"; 737 rockchip,grf = <&grf>; 738 rockchip,hw-tshut-temp = <120000>; 739 pinctrl-names = "init", "default", "sleep"; 740 pinctrl-0 = <&tsadc_otp_pin>; 741 pinctrl-1 = <&tsadc_otp_out>; 742 pinctrl-2 = <&tsadc_otp_pin>; 743 #thermal-sensor-cells = <1>; 744 status = "disabled"; 745 }; 746 747 saradc: saradc@ff288000 { 748 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 749 reg = <0x0 0xff288000 0x0 0x100>; 750 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 751 #io-channel-cells = <1>; 752 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 753 clock-names = "saradc", "apb_pclk"; 754 resets = <&cru SRST_SARADC_P>; 755 reset-names = "saradc-apb"; 756 status = "disabled"; 757 }; 758 759 otp: nvmem@ff290000 { 760 compatible = "rockchip,px30-otp"; 761 reg = <0x0 0xff290000 0x0 0x4000>; 762 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 763 <&cru PCLK_OTP_PHY>; 764 clock-names = "otp", "apb_pclk", "phy"; 765 resets = <&cru SRST_OTP_PHY>; 766 reset-names = "phy"; 767 #address-cells = <1>; 768 #size-cells = <1>; 769 770 /* Data cells */ 771 cpu_id: id@7 { 772 reg = <0x07 0x10>; 773 }; 774 cpu_leakage: cpu-leakage@17 { 775 reg = <0x17 0x1>; 776 }; 777 performance: performance@1e { 778 reg = <0x1e 0x1>; 779 bits = <4 3>; 780 }; 781 }; 782 783 cru: clock-controller@ff2b0000 { 784 compatible = "rockchip,px30-cru"; 785 reg = <0x0 0xff2b0000 0x0 0x1000>; 786 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 787 clock-names = "xin24m", "gpll"; 788 rockchip,grf = <&grf>; 789 #clock-cells = <1>; 790 #reset-cells = <1>; 791 792 assigned-clocks = <&cru PLL_NPLL>, 793 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 794 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 795 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 796 797 assigned-clock-rates = <1188000000>, 798 <200000000>, <200000000>, 799 <150000000>, <150000000>, 800 <100000000>, <200000000>; 801 }; 802 803 pmucru: clock-controller@ff2bc000 { 804 compatible = "rockchip,px30-pmucru"; 805 reg = <0x0 0xff2bc000 0x0 0x1000>; 806 clocks = <&xin24m>; 807 clock-names = "xin24m"; 808 rockchip,grf = <&grf>; 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 812 assigned-clocks = 813 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 814 <&pmucru SCLK_WIFI_PMU>; 815 assigned-clock-rates = 816 <1200000000>, <100000000>, 817 <26000000>; 818 }; 819 820 usb2phy_grf: syscon@ff2c0000 { 821 compatible = "rockchip,px30-usb2phy-grf", "syscon", 822 "simple-mfd"; 823 reg = <0x0 0xff2c0000 0x0 0x10000>; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 827 u2phy: usb2phy@100 { 828 compatible = "rockchip,px30-usb2phy"; 829 reg = <0x100 0x20>; 830 clocks = <&pmucru SCLK_USBPHY_REF>; 831 clock-names = "phyclk"; 832 #clock-cells = <0>; 833 assigned-clocks = <&cru USB480M>; 834 assigned-clock-parents = <&u2phy>; 835 clock-output-names = "usb480m_phy"; 836 status = "disabled"; 837 838 u2phy_host: host-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "linestate"; 842 status = "disabled"; 843 }; 844 845 u2phy_otg: otg-port { 846 #phy-cells = <0>; 847 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "otg-bvalid", "otg-id", 851 "linestate"; 852 status = "disabled"; 853 }; 854 }; 855 }; 856 857 dsi_dphy: phy@ff2e0000 { 858 compatible = "rockchip,px30-dsi-dphy"; 859 reg = <0x0 0xff2e0000 0x0 0x10000>; 860 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 861 clock-names = "ref", "pclk"; 862 resets = <&cru SRST_MIPIDSIPHY_P>; 863 reset-names = "apb"; 864 #phy-cells = <0>; 865 power-domains = <&power PX30_PD_VO>; 866 status = "disabled"; 867 }; 868 869 usb20_otg: usb@ff300000 { 870 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 871 "snps,dwc2"; 872 reg = <0x0 0xff300000 0x0 0x40000>; 873 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&cru HCLK_OTG>; 875 clock-names = "otg"; 876 dr_mode = "otg"; 877 g-np-tx-fifo-size = <16>; 878 g-rx-fifo-size = <280>; 879 g-tx-fifo-size = <256 128 128 64 32 16>; 880 phys = <&u2phy_otg>; 881 phy-names = "usb2-phy"; 882 power-domains = <&power PX30_PD_USB>; 883 status = "disabled"; 884 }; 885 886 usb_host0_ehci: usb@ff340000 { 887 compatible = "generic-ehci"; 888 reg = <0x0 0xff340000 0x0 0x10000>; 889 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&cru HCLK_HOST>; 891 phys = <&u2phy_host>; 892 phy-names = "usb"; 893 power-domains = <&power PX30_PD_USB>; 894 status = "disabled"; 895 }; 896 897 usb_host0_ohci: usb@ff350000 { 898 compatible = "generic-ohci"; 899 reg = <0x0 0xff350000 0x0 0x10000>; 900 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cru HCLK_HOST>; 902 phys = <&u2phy_host>; 903 phy-names = "usb"; 904 power-domains = <&power PX30_PD_USB>; 905 status = "disabled"; 906 }; 907 908 gmac: ethernet@ff360000 { 909 compatible = "rockchip,px30-gmac"; 910 reg = <0x0 0xff360000 0x0 0x10000>; 911 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 912 interrupt-names = "macirq"; 913 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 914 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 915 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 916 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 917 clock-names = "stmmaceth", "mac_clk_rx", 918 "mac_clk_tx", "clk_mac_ref", 919 "clk_mac_refout", "aclk_mac", 920 "pclk_mac", "clk_mac_speed"; 921 rockchip,grf = <&grf>; 922 phy-mode = "rmii"; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 925 power-domains = <&power PX30_PD_GMAC>; 926 resets = <&cru SRST_GMAC_A>; 927 reset-names = "stmmaceth"; 928 status = "disabled"; 929 }; 930 931 sdmmc: mmc@ff370000 { 932 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 933 reg = <0x0 0xff370000 0x0 0x4000>; 934 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 936 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 937 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 938 bus-width = <4>; 939 fifo-depth = <0x100>; 940 max-frequency = <150000000>; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 943 power-domains = <&power PX30_PD_SDCARD>; 944 status = "disabled"; 945 }; 946 947 sdio: mmc@ff380000 { 948 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 949 reg = <0x0 0xff380000 0x0 0x4000>; 950 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 952 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 953 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 954 bus-width = <4>; 955 fifo-depth = <0x100>; 956 max-frequency = <150000000>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 959 power-domains = <&power PX30_PD_MMC_NAND>; 960 status = "disabled"; 961 }; 962 963 emmc: mmc@ff390000 { 964 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 965 reg = <0x0 0xff390000 0x0 0x4000>; 966 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 968 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 969 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 970 bus-width = <8>; 971 fifo-depth = <0x100>; 972 max-frequency = <150000000>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 975 power-domains = <&power PX30_PD_MMC_NAND>; 976 status = "disabled"; 977 }; 978 979 nfc: nand-controller@ff3b0000 { 980 compatible = "rockchip,px30-nfc"; 981 reg = <0x0 0xff3b0000 0x0 0x4000>; 982 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 984 clock-names = "ahb", "nfc"; 985 assigned-clocks = <&cru SCLK_NANDC>; 986 assigned-clock-rates = <150000000>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 989 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 990 power-domains = <&power PX30_PD_MMC_NAND>; 991 status = "disabled"; 992 }; 993 994 gpu_opp_table: opp-table2 { 995 compatible = "operating-points-v2"; 996 997 opp-200000000 { 998 opp-hz = /bits/ 64 <200000000>; 999 opp-microvolt = <950000>; 1000 }; 1001 opp-300000000 { 1002 opp-hz = /bits/ 64 <300000000>; 1003 opp-microvolt = <975000>; 1004 }; 1005 opp-400000000 { 1006 opp-hz = /bits/ 64 <400000000>; 1007 opp-microvolt = <1050000>; 1008 }; 1009 opp-480000000 { 1010 opp-hz = /bits/ 64 <480000000>; 1011 opp-microvolt = <1125000>; 1012 }; 1013 }; 1014 1015 gpu: gpu@ff400000 { 1016 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1017 reg = <0x0 0xff400000 0x0 0x4000>; 1018 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1021 interrupt-names = "job", "mmu", "gpu"; 1022 clocks = <&cru SCLK_GPU>; 1023 #cooling-cells = <2>; 1024 power-domains = <&power PX30_PD_GPU>; 1025 operating-points-v2 = <&gpu_opp_table>; 1026 status = "disabled"; 1027 }; 1028 1029 dsi: dsi@ff450000 { 1030 compatible = "rockchip,px30-mipi-dsi"; 1031 reg = <0x0 0xff450000 0x0 0x10000>; 1032 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cru PCLK_MIPI_DSI>; 1034 clock-names = "pclk"; 1035 phys = <&dsi_dphy>; 1036 phy-names = "dphy"; 1037 power-domains = <&power PX30_PD_VO>; 1038 resets = <&cru SRST_MIPIDSI_HOST_P>; 1039 reset-names = "apb"; 1040 rockchip,grf = <&grf>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 port@0 { 1050 reg = <0>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 dsi_in_vopb: endpoint@0 { 1055 reg = <0>; 1056 remote-endpoint = <&vopb_out_dsi>; 1057 }; 1058 1059 dsi_in_vopl: endpoint@1 { 1060 reg = <1>; 1061 remote-endpoint = <&vopl_out_dsi>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 vopb: vop@ff460000 { 1068 compatible = "rockchip,px30-vop-big"; 1069 reg = <0x0 0xff460000 0x0 0xefc>; 1070 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1072 <&cru HCLK_VOPB>; 1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1074 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1075 reset-names = "axi", "ahb", "dclk"; 1076 iommus = <&vopb_mmu>; 1077 power-domains = <&power PX30_PD_VO>; 1078 status = "disabled"; 1079 1080 vopb_out: port { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 vopb_out_dsi: endpoint@0 { 1085 reg = <0>; 1086 remote-endpoint = <&dsi_in_vopb>; 1087 }; 1088 1089 vopb_out_lvds: endpoint@1 { 1090 reg = <1>; 1091 remote-endpoint = <&lvds_vopb_in>; 1092 }; 1093 }; 1094 }; 1095 1096 vopb_mmu: iommu@ff460f00 { 1097 compatible = "rockchip,iommu"; 1098 reg = <0x0 0xff460f00 0x0 0x100>; 1099 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1101 clock-names = "aclk", "iface"; 1102 power-domains = <&power PX30_PD_VO>; 1103 #iommu-cells = <0>; 1104 status = "disabled"; 1105 }; 1106 1107 vopl: vop@ff470000 { 1108 compatible = "rockchip,px30-vop-lit"; 1109 reg = <0x0 0xff470000 0x0 0xefc>; 1110 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1112 <&cru HCLK_VOPL>; 1113 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1114 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1115 reset-names = "axi", "ahb", "dclk"; 1116 iommus = <&vopl_mmu>; 1117 power-domains = <&power PX30_PD_VO>; 1118 status = "disabled"; 1119 1120 vopl_out: port { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 vopl_out_dsi: endpoint@0 { 1125 reg = <0>; 1126 remote-endpoint = <&dsi_in_vopl>; 1127 }; 1128 1129 vopl_out_lvds: endpoint@1 { 1130 reg = <1>; 1131 remote-endpoint = <&lvds_vopl_in>; 1132 }; 1133 }; 1134 }; 1135 1136 vopl_mmu: iommu@ff470f00 { 1137 compatible = "rockchip,iommu"; 1138 reg = <0x0 0xff470f00 0x0 0x100>; 1139 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1141 clock-names = "aclk", "iface"; 1142 power-domains = <&power PX30_PD_VO>; 1143 #iommu-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 qos_gmac: qos@ff518000 { 1148 compatible = "rockchip,px30-qos", "syscon"; 1149 reg = <0x0 0xff518000 0x0 0x20>; 1150 }; 1151 1152 qos_gpu: qos@ff520000 { 1153 compatible = "rockchip,px30-qos", "syscon"; 1154 reg = <0x0 0xff520000 0x0 0x20>; 1155 }; 1156 1157 qos_sdmmc: qos@ff52c000 { 1158 compatible = "rockchip,px30-qos", "syscon"; 1159 reg = <0x0 0xff52c000 0x0 0x20>; 1160 }; 1161 1162 qos_emmc: qos@ff538000 { 1163 compatible = "rockchip,px30-qos", "syscon"; 1164 reg = <0x0 0xff538000 0x0 0x20>; 1165 }; 1166 1167 qos_nand: qos@ff538080 { 1168 compatible = "rockchip,px30-qos", "syscon"; 1169 reg = <0x0 0xff538080 0x0 0x20>; 1170 }; 1171 1172 qos_sdio: qos@ff538100 { 1173 compatible = "rockchip,px30-qos", "syscon"; 1174 reg = <0x0 0xff538100 0x0 0x20>; 1175 }; 1176 1177 qos_sfc: qos@ff538180 { 1178 compatible = "rockchip,px30-qos", "syscon"; 1179 reg = <0x0 0xff538180 0x0 0x20>; 1180 }; 1181 1182 qos_usb_host: qos@ff540000 { 1183 compatible = "rockchip,px30-qos", "syscon"; 1184 reg = <0x0 0xff540000 0x0 0x20>; 1185 }; 1186 1187 qos_usb_otg: qos@ff540080 { 1188 compatible = "rockchip,px30-qos", "syscon"; 1189 reg = <0x0 0xff540080 0x0 0x20>; 1190 }; 1191 1192 qos_isp_128: qos@ff548000 { 1193 compatible = "rockchip,px30-qos", "syscon"; 1194 reg = <0x0 0xff548000 0x0 0x20>; 1195 }; 1196 1197 qos_isp_rd: qos@ff548080 { 1198 compatible = "rockchip,px30-qos", "syscon"; 1199 reg = <0x0 0xff548080 0x0 0x20>; 1200 }; 1201 1202 qos_isp_wr: qos@ff548100 { 1203 compatible = "rockchip,px30-qos", "syscon"; 1204 reg = <0x0 0xff548100 0x0 0x20>; 1205 }; 1206 1207 qos_isp_m1: qos@ff548180 { 1208 compatible = "rockchip,px30-qos", "syscon"; 1209 reg = <0x0 0xff548180 0x0 0x20>; 1210 }; 1211 1212 qos_vip: qos@ff548200 { 1213 compatible = "rockchip,px30-qos", "syscon"; 1214 reg = <0x0 0xff548200 0x0 0x20>; 1215 }; 1216 1217 qos_rga_rd: qos@ff550000 { 1218 compatible = "rockchip,px30-qos", "syscon"; 1219 reg = <0x0 0xff550000 0x0 0x20>; 1220 }; 1221 1222 qos_rga_wr: qos@ff550080 { 1223 compatible = "rockchip,px30-qos", "syscon"; 1224 reg = <0x0 0xff550080 0x0 0x20>; 1225 }; 1226 1227 qos_vop_m0: qos@ff550100 { 1228 compatible = "rockchip,px30-qos", "syscon"; 1229 reg = <0x0 0xff550100 0x0 0x20>; 1230 }; 1231 1232 qos_vop_m1: qos@ff550180 { 1233 compatible = "rockchip,px30-qos", "syscon"; 1234 reg = <0x0 0xff550180 0x0 0x20>; 1235 }; 1236 1237 qos_vpu: qos@ff558000 { 1238 compatible = "rockchip,px30-qos", "syscon"; 1239 reg = <0x0 0xff558000 0x0 0x20>; 1240 }; 1241 1242 qos_vpu_r128: qos@ff558080 { 1243 compatible = "rockchip,px30-qos", "syscon"; 1244 reg = <0x0 0xff558080 0x0 0x20>; 1245 }; 1246 1247 pinctrl: pinctrl { 1248 compatible = "rockchip,px30-pinctrl"; 1249 rockchip,grf = <&grf>; 1250 rockchip,pmu = <&pmugrf>; 1251 #address-cells = <2>; 1252 #size-cells = <2>; 1253 ranges; 1254 1255 gpio0: gpio0@ff040000 { 1256 compatible = "rockchip,gpio-bank"; 1257 reg = <0x0 0xff040000 0x0 0x100>; 1258 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&pmucru PCLK_GPIO0_PMU>; 1260 gpio-controller; 1261 #gpio-cells = <2>; 1262 1263 interrupt-controller; 1264 #interrupt-cells = <2>; 1265 }; 1266 1267 gpio1: gpio1@ff250000 { 1268 compatible = "rockchip,gpio-bank"; 1269 reg = <0x0 0xff250000 0x0 0x100>; 1270 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&cru PCLK_GPIO1>; 1272 gpio-controller; 1273 #gpio-cells = <2>; 1274 1275 interrupt-controller; 1276 #interrupt-cells = <2>; 1277 }; 1278 1279 gpio2: gpio2@ff260000 { 1280 compatible = "rockchip,gpio-bank"; 1281 reg = <0x0 0xff260000 0x0 0x100>; 1282 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cru PCLK_GPIO2>; 1284 gpio-controller; 1285 #gpio-cells = <2>; 1286 1287 interrupt-controller; 1288 #interrupt-cells = <2>; 1289 }; 1290 1291 gpio3: gpio3@ff270000 { 1292 compatible = "rockchip,gpio-bank"; 1293 reg = <0x0 0xff270000 0x0 0x100>; 1294 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&cru PCLK_GPIO3>; 1296 gpio-controller; 1297 #gpio-cells = <2>; 1298 1299 interrupt-controller; 1300 #interrupt-cells = <2>; 1301 }; 1302 1303 pcfg_pull_up: pcfg-pull-up { 1304 bias-pull-up; 1305 }; 1306 1307 pcfg_pull_down: pcfg-pull-down { 1308 bias-pull-down; 1309 }; 1310 1311 pcfg_pull_none: pcfg-pull-none { 1312 bias-disable; 1313 }; 1314 1315 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1316 bias-disable; 1317 drive-strength = <2>; 1318 }; 1319 1320 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1321 bias-pull-up; 1322 drive-strength = <2>; 1323 }; 1324 1325 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1326 bias-pull-up; 1327 drive-strength = <4>; 1328 }; 1329 1330 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1331 bias-disable; 1332 drive-strength = <4>; 1333 }; 1334 1335 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1336 bias-pull-down; 1337 drive-strength = <4>; 1338 }; 1339 1340 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1341 bias-disable; 1342 drive-strength = <8>; 1343 }; 1344 1345 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1346 bias-pull-up; 1347 drive-strength = <8>; 1348 }; 1349 1350 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1351 bias-disable; 1352 drive-strength = <12>; 1353 }; 1354 1355 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1356 bias-pull-up; 1357 drive-strength = <12>; 1358 }; 1359 1360 pcfg_pull_none_smt: pcfg-pull-none-smt { 1361 bias-disable; 1362 input-schmitt-enable; 1363 }; 1364 1365 pcfg_output_high: pcfg-output-high { 1366 output-high; 1367 }; 1368 1369 pcfg_output_low: pcfg-output-low { 1370 output-low; 1371 }; 1372 1373 pcfg_input_high: pcfg-input-high { 1374 bias-pull-up; 1375 input-enable; 1376 }; 1377 1378 pcfg_input: pcfg-input { 1379 input-enable; 1380 }; 1381 1382 i2c0 { 1383 i2c0_xfer: i2c0-xfer { 1384 rockchip,pins = 1385 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1386 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1387 }; 1388 }; 1389 1390 i2c1 { 1391 i2c1_xfer: i2c1-xfer { 1392 rockchip,pins = 1393 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1394 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1395 }; 1396 }; 1397 1398 i2c2 { 1399 i2c2_xfer: i2c2-xfer { 1400 rockchip,pins = 1401 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1402 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1403 }; 1404 }; 1405 1406 i2c3 { 1407 i2c3_xfer: i2c3-xfer { 1408 rockchip,pins = 1409 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1410 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1411 }; 1412 }; 1413 1414 tsadc { 1415 tsadc_otp_pin: tsadc-otp-pin { 1416 rockchip,pins = 1417 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1418 }; 1419 1420 tsadc_otp_out: tsadc-otp-out { 1421 rockchip,pins = 1422 <0 RK_PA6 1 &pcfg_pull_none>; 1423 }; 1424 }; 1425 1426 uart0 { 1427 uart0_xfer: uart0-xfer { 1428 rockchip,pins = 1429 <0 RK_PB2 1 &pcfg_pull_up>, 1430 <0 RK_PB3 1 &pcfg_pull_up>; 1431 }; 1432 1433 uart0_cts: uart0-cts { 1434 rockchip,pins = 1435 <0 RK_PB4 1 &pcfg_pull_none>; 1436 }; 1437 1438 uart0_rts: uart0-rts { 1439 rockchip,pins = 1440 <0 RK_PB5 1 &pcfg_pull_none>; 1441 }; 1442 }; 1443 1444 uart1 { 1445 uart1_xfer: uart1-xfer { 1446 rockchip,pins = 1447 <1 RK_PC1 1 &pcfg_pull_up>, 1448 <1 RK_PC0 1 &pcfg_pull_up>; 1449 }; 1450 1451 uart1_cts: uart1-cts { 1452 rockchip,pins = 1453 <1 RK_PC2 1 &pcfg_pull_none>; 1454 }; 1455 1456 uart1_rts: uart1-rts { 1457 rockchip,pins = 1458 <1 RK_PC3 1 &pcfg_pull_none>; 1459 }; 1460 }; 1461 1462 uart2-m0 { 1463 uart2m0_xfer: uart2m0-xfer { 1464 rockchip,pins = 1465 <1 RK_PD2 2 &pcfg_pull_up>, 1466 <1 RK_PD3 2 &pcfg_pull_up>; 1467 }; 1468 }; 1469 1470 uart2-m1 { 1471 uart2m1_xfer: uart2m1-xfer { 1472 rockchip,pins = 1473 <2 RK_PB4 2 &pcfg_pull_up>, 1474 <2 RK_PB6 2 &pcfg_pull_up>; 1475 }; 1476 }; 1477 1478 uart3-m0 { 1479 uart3m0_xfer: uart3m0-xfer { 1480 rockchip,pins = 1481 <0 RK_PC0 2 &pcfg_pull_up>, 1482 <0 RK_PC1 2 &pcfg_pull_up>; 1483 }; 1484 1485 uart3m0_cts: uart3m0-cts { 1486 rockchip,pins = 1487 <0 RK_PC2 2 &pcfg_pull_none>; 1488 }; 1489 1490 uart3m0_rts: uart3m0-rts { 1491 rockchip,pins = 1492 <0 RK_PC3 2 &pcfg_pull_none>; 1493 }; 1494 }; 1495 1496 uart3-m1 { 1497 uart3m1_xfer: uart3m1-xfer { 1498 rockchip,pins = 1499 <1 RK_PB6 2 &pcfg_pull_up>, 1500 <1 RK_PB7 2 &pcfg_pull_up>; 1501 }; 1502 1503 uart3m1_cts: uart3m1-cts { 1504 rockchip,pins = 1505 <1 RK_PB4 2 &pcfg_pull_none>; 1506 }; 1507 1508 uart3m1_rts: uart3m1-rts { 1509 rockchip,pins = 1510 <1 RK_PB5 2 &pcfg_pull_none>; 1511 }; 1512 }; 1513 1514 uart4 { 1515 uart4_xfer: uart4-xfer { 1516 rockchip,pins = 1517 <1 RK_PD4 2 &pcfg_pull_up>, 1518 <1 RK_PD5 2 &pcfg_pull_up>; 1519 }; 1520 1521 uart4_cts: uart4-cts { 1522 rockchip,pins = 1523 <1 RK_PD6 2 &pcfg_pull_none>; 1524 }; 1525 1526 uart4_rts: uart4-rts { 1527 rockchip,pins = 1528 <1 RK_PD7 2 &pcfg_pull_none>; 1529 }; 1530 }; 1531 1532 uart5 { 1533 uart5_xfer: uart5-xfer { 1534 rockchip,pins = 1535 <3 RK_PA2 4 &pcfg_pull_up>, 1536 <3 RK_PA1 4 &pcfg_pull_up>; 1537 }; 1538 1539 uart5_cts: uart5-cts { 1540 rockchip,pins = 1541 <3 RK_PA3 4 &pcfg_pull_none>; 1542 }; 1543 1544 uart5_rts: uart5-rts { 1545 rockchip,pins = 1546 <3 RK_PA5 4 &pcfg_pull_none>; 1547 }; 1548 }; 1549 1550 spi0 { 1551 spi0_clk: spi0-clk { 1552 rockchip,pins = 1553 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1554 }; 1555 1556 spi0_csn: spi0-csn { 1557 rockchip,pins = 1558 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1559 }; 1560 1561 spi0_miso: spi0-miso { 1562 rockchip,pins = 1563 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1564 }; 1565 1566 spi0_mosi: spi0-mosi { 1567 rockchip,pins = 1568 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1569 }; 1570 1571 spi0_clk_hs: spi0-clk-hs { 1572 rockchip,pins = 1573 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1574 }; 1575 1576 spi0_miso_hs: spi0-miso-hs { 1577 rockchip,pins = 1578 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1579 }; 1580 1581 spi0_mosi_hs: spi0-mosi-hs { 1582 rockchip,pins = 1583 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1584 }; 1585 }; 1586 1587 spi1 { 1588 spi1_clk: spi1-clk { 1589 rockchip,pins = 1590 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1591 }; 1592 1593 spi1_csn0: spi1-csn0 { 1594 rockchip,pins = 1595 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1596 }; 1597 1598 spi1_csn1: spi1-csn1 { 1599 rockchip,pins = 1600 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1601 }; 1602 1603 spi1_miso: spi1-miso { 1604 rockchip,pins = 1605 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1606 }; 1607 1608 spi1_mosi: spi1-mosi { 1609 rockchip,pins = 1610 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1611 }; 1612 1613 spi1_clk_hs: spi1-clk-hs { 1614 rockchip,pins = 1615 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1616 }; 1617 1618 spi1_miso_hs: spi1-miso-hs { 1619 rockchip,pins = 1620 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1621 }; 1622 1623 spi1_mosi_hs: spi1-mosi-hs { 1624 rockchip,pins = 1625 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1626 }; 1627 }; 1628 1629 pdm { 1630 pdm_clk0m0: pdm-clk0m0 { 1631 rockchip,pins = 1632 <3 RK_PC6 2 &pcfg_pull_none>; 1633 }; 1634 1635 pdm_clk0m1: pdm-clk0m1 { 1636 rockchip,pins = 1637 <2 RK_PC6 1 &pcfg_pull_none>; 1638 }; 1639 1640 pdm_clk1: pdm-clk1 { 1641 rockchip,pins = 1642 <3 RK_PC7 2 &pcfg_pull_none>; 1643 }; 1644 1645 pdm_sdi0m0: pdm-sdi0m0 { 1646 rockchip,pins = 1647 <3 RK_PD3 2 &pcfg_pull_none>; 1648 }; 1649 1650 pdm_sdi0m1: pdm-sdi0m1 { 1651 rockchip,pins = 1652 <2 RK_PC5 2 &pcfg_pull_none>; 1653 }; 1654 1655 pdm_sdi1: pdm-sdi1 { 1656 rockchip,pins = 1657 <3 RK_PD0 2 &pcfg_pull_none>; 1658 }; 1659 1660 pdm_sdi2: pdm-sdi2 { 1661 rockchip,pins = 1662 <3 RK_PD1 2 &pcfg_pull_none>; 1663 }; 1664 1665 pdm_sdi3: pdm-sdi3 { 1666 rockchip,pins = 1667 <3 RK_PD2 2 &pcfg_pull_none>; 1668 }; 1669 1670 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1671 rockchip,pins = 1672 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1673 }; 1674 1675 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1676 rockchip,pins = 1677 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1678 }; 1679 1680 pdm_clk1_sleep: pdm-clk1-sleep { 1681 rockchip,pins = 1682 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1683 }; 1684 1685 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1686 rockchip,pins = 1687 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1688 }; 1689 1690 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1691 rockchip,pins = 1692 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1693 }; 1694 1695 pdm_sdi1_sleep: pdm-sdi1-sleep { 1696 rockchip,pins = 1697 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1698 }; 1699 1700 pdm_sdi2_sleep: pdm-sdi2-sleep { 1701 rockchip,pins = 1702 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1703 }; 1704 1705 pdm_sdi3_sleep: pdm-sdi3-sleep { 1706 rockchip,pins = 1707 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1708 }; 1709 }; 1710 1711 i2s0 { 1712 i2s0_8ch_mclk: i2s0-8ch-mclk { 1713 rockchip,pins = 1714 <3 RK_PC1 2 &pcfg_pull_none>; 1715 }; 1716 1717 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1718 rockchip,pins = 1719 <3 RK_PC3 2 &pcfg_pull_none>; 1720 }; 1721 1722 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1723 rockchip,pins = 1724 <3 RK_PB4 2 &pcfg_pull_none>; 1725 }; 1726 1727 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1728 rockchip,pins = 1729 <3 RK_PC2 2 &pcfg_pull_none>; 1730 }; 1731 1732 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1733 rockchip,pins = 1734 <3 RK_PB5 2 &pcfg_pull_none>; 1735 }; 1736 1737 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1738 rockchip,pins = 1739 <3 RK_PC4 2 &pcfg_pull_none>; 1740 }; 1741 1742 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1743 rockchip,pins = 1744 <3 RK_PC0 2 &pcfg_pull_none>; 1745 }; 1746 1747 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1748 rockchip,pins = 1749 <3 RK_PB7 2 &pcfg_pull_none>; 1750 }; 1751 1752 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1753 rockchip,pins = 1754 <3 RK_PB6 2 &pcfg_pull_none>; 1755 }; 1756 1757 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1758 rockchip,pins = 1759 <3 RK_PC5 2 &pcfg_pull_none>; 1760 }; 1761 1762 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1763 rockchip,pins = 1764 <3 RK_PB3 2 &pcfg_pull_none>; 1765 }; 1766 1767 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1768 rockchip,pins = 1769 <3 RK_PB1 2 &pcfg_pull_none>; 1770 }; 1771 1772 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1773 rockchip,pins = 1774 <3 RK_PB0 2 &pcfg_pull_none>; 1775 }; 1776 }; 1777 1778 i2s1 { 1779 i2s1_2ch_mclk: i2s1-2ch-mclk { 1780 rockchip,pins = 1781 <2 RK_PC3 1 &pcfg_pull_none>; 1782 }; 1783 1784 i2s1_2ch_sclk: i2s1-2ch-sclk { 1785 rockchip,pins = 1786 <2 RK_PC2 1 &pcfg_pull_none>; 1787 }; 1788 1789 i2s1_2ch_lrck: i2s1-2ch-lrck { 1790 rockchip,pins = 1791 <2 RK_PC1 1 &pcfg_pull_none>; 1792 }; 1793 1794 i2s1_2ch_sdi: i2s1-2ch-sdi { 1795 rockchip,pins = 1796 <2 RK_PC5 1 &pcfg_pull_none>; 1797 }; 1798 1799 i2s1_2ch_sdo: i2s1-2ch-sdo { 1800 rockchip,pins = 1801 <2 RK_PC4 1 &pcfg_pull_none>; 1802 }; 1803 }; 1804 1805 i2s2 { 1806 i2s2_2ch_mclk: i2s2-2ch-mclk { 1807 rockchip,pins = 1808 <3 RK_PA1 2 &pcfg_pull_none>; 1809 }; 1810 1811 i2s2_2ch_sclk: i2s2-2ch-sclk { 1812 rockchip,pins = 1813 <3 RK_PA2 2 &pcfg_pull_none>; 1814 }; 1815 1816 i2s2_2ch_lrck: i2s2-2ch-lrck { 1817 rockchip,pins = 1818 <3 RK_PA3 2 &pcfg_pull_none>; 1819 }; 1820 1821 i2s2_2ch_sdi: i2s2-2ch-sdi { 1822 rockchip,pins = 1823 <3 RK_PA5 2 &pcfg_pull_none>; 1824 }; 1825 1826 i2s2_2ch_sdo: i2s2-2ch-sdo { 1827 rockchip,pins = 1828 <3 RK_PA7 2 &pcfg_pull_none>; 1829 }; 1830 }; 1831 1832 sdmmc { 1833 sdmmc_clk: sdmmc-clk { 1834 rockchip,pins = 1835 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1836 }; 1837 1838 sdmmc_cmd: sdmmc-cmd { 1839 rockchip,pins = 1840 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1841 }; 1842 1843 sdmmc_det: sdmmc-det { 1844 rockchip,pins = 1845 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1846 }; 1847 1848 sdmmc_bus1: sdmmc-bus1 { 1849 rockchip,pins = 1850 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1851 }; 1852 1853 sdmmc_bus4: sdmmc-bus4 { 1854 rockchip,pins = 1855 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1856 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1857 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1858 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1859 }; 1860 }; 1861 1862 sdio { 1863 sdio_clk: sdio-clk { 1864 rockchip,pins = 1865 <1 RK_PC5 1 &pcfg_pull_none>; 1866 }; 1867 1868 sdio_cmd: sdio-cmd { 1869 rockchip,pins = 1870 <1 RK_PC4 1 &pcfg_pull_up>; 1871 }; 1872 1873 sdio_bus4: sdio-bus4 { 1874 rockchip,pins = 1875 <1 RK_PC6 1 &pcfg_pull_up>, 1876 <1 RK_PC7 1 &pcfg_pull_up>, 1877 <1 RK_PD0 1 &pcfg_pull_up>, 1878 <1 RK_PD1 1 &pcfg_pull_up>; 1879 }; 1880 }; 1881 1882 emmc { 1883 emmc_clk: emmc-clk { 1884 rockchip,pins = 1885 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1886 }; 1887 1888 emmc_cmd: emmc-cmd { 1889 rockchip,pins = 1890 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1891 }; 1892 1893 emmc_rstnout: emmc-rstnout { 1894 rockchip,pins = 1895 <1 RK_PB3 2 &pcfg_pull_none>; 1896 }; 1897 1898 emmc_bus1: emmc-bus1 { 1899 rockchip,pins = 1900 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1901 }; 1902 1903 emmc_bus4: emmc-bus4 { 1904 rockchip,pins = 1905 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1906 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1907 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1908 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1909 }; 1910 1911 emmc_bus8: emmc-bus8 { 1912 rockchip,pins = 1913 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1914 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1915 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1916 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1917 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1918 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1919 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1920 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1921 }; 1922 }; 1923 1924 flash { 1925 flash_cs0: flash-cs0 { 1926 rockchip,pins = 1927 <1 RK_PB0 1 &pcfg_pull_none>; 1928 }; 1929 1930 flash_rdy: flash-rdy { 1931 rockchip,pins = 1932 <1 RK_PB1 1 &pcfg_pull_none>; 1933 }; 1934 1935 flash_dqs: flash-dqs { 1936 rockchip,pins = 1937 <1 RK_PB2 1 &pcfg_pull_none>; 1938 }; 1939 1940 flash_ale: flash-ale { 1941 rockchip,pins = 1942 <1 RK_PB3 1 &pcfg_pull_none>; 1943 }; 1944 1945 flash_cle: flash-cle { 1946 rockchip,pins = 1947 <1 RK_PB4 1 &pcfg_pull_none>; 1948 }; 1949 1950 flash_wrn: flash-wrn { 1951 rockchip,pins = 1952 <1 RK_PB5 1 &pcfg_pull_none>; 1953 }; 1954 1955 flash_csl: flash-csl { 1956 rockchip,pins = 1957 <1 RK_PB6 1 &pcfg_pull_none>; 1958 }; 1959 1960 flash_rdn: flash-rdn { 1961 rockchip,pins = 1962 <1 RK_PB7 1 &pcfg_pull_none>; 1963 }; 1964 1965 flash_bus8: flash-bus8 { 1966 rockchip,pins = 1967 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1968 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1969 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1970 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1971 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1972 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1973 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1974 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1975 }; 1976 }; 1977 1978 lcdc { 1979 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1980 rockchip,pins = 1981 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1982 }; 1983 1984 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1985 rockchip,pins = 1986 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1987 }; 1988 1989 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1990 rockchip,pins = 1991 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1992 }; 1993 1994 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1995 rockchip,pins = 1996 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1997 }; 1998 1999 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 2000 rockchip,pins = 2001 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2002 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2003 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2004 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2005 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2006 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2007 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2008 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2009 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2010 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2011 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2012 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2013 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2014 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2015 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2016 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2017 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2018 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2019 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2020 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2021 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2022 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2023 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2024 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2025 }; 2026 2027 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2028 rockchip,pins = 2029 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2030 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2031 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2032 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2033 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2034 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2035 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2036 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2037 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2038 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2039 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2040 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2041 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2042 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2043 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2044 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2045 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2046 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2047 }; 2048 2049 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2050 rockchip,pins = 2051 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2052 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2053 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2054 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2055 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2056 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2057 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2058 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2059 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2060 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2061 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2062 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2063 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2064 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2065 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2066 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2067 }; 2068 2069 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2070 rockchip,pins = 2071 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2072 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2073 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2074 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2075 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2076 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2077 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2078 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2079 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2080 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2081 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2082 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2083 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2084 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2085 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2086 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2087 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2088 }; 2089 2090 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2091 rockchip,pins = 2092 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2093 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2094 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2095 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2096 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2097 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2098 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2099 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2100 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2101 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2102 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2103 }; 2104 2105 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2106 rockchip,pins = 2107 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2108 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2109 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2110 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2111 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2112 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2113 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2114 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2115 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2116 }; 2117 }; 2118 2119 pwm0 { 2120 pwm0_pin: pwm0-pin { 2121 rockchip,pins = 2122 <0 RK_PB7 1 &pcfg_pull_none>; 2123 }; 2124 }; 2125 2126 pwm1 { 2127 pwm1_pin: pwm1-pin { 2128 rockchip,pins = 2129 <0 RK_PC0 1 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 pwm2 { 2134 pwm2_pin: pwm2-pin { 2135 rockchip,pins = 2136 <2 RK_PB5 1 &pcfg_pull_none>; 2137 }; 2138 }; 2139 2140 pwm3 { 2141 pwm3_pin: pwm3-pin { 2142 rockchip,pins = 2143 <0 RK_PC1 1 &pcfg_pull_none>; 2144 }; 2145 }; 2146 2147 pwm4 { 2148 pwm4_pin: pwm4-pin { 2149 rockchip,pins = 2150 <3 RK_PC2 3 &pcfg_pull_none>; 2151 }; 2152 }; 2153 2154 pwm5 { 2155 pwm5_pin: pwm5-pin { 2156 rockchip,pins = 2157 <3 RK_PC3 3 &pcfg_pull_none>; 2158 }; 2159 }; 2160 2161 pwm6 { 2162 pwm6_pin: pwm6-pin { 2163 rockchip,pins = 2164 <3 RK_PC4 3 &pcfg_pull_none>; 2165 }; 2166 }; 2167 2168 pwm7 { 2169 pwm7_pin: pwm7-pin { 2170 rockchip,pins = 2171 <3 RK_PC5 3 &pcfg_pull_none>; 2172 }; 2173 }; 2174 2175 gmac { 2176 rmii_pins: rmii-pins { 2177 rockchip,pins = 2178 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2179 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2180 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2181 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2182 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2183 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2184 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2185 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2186 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2187 }; 2188 2189 mac_refclk_12ma: mac-refclk-12ma { 2190 rockchip,pins = 2191 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2192 }; 2193 2194 mac_refclk: mac-refclk { 2195 rockchip,pins = 2196 <2 RK_PB2 2 &pcfg_pull_none>; 2197 }; 2198 }; 2199 2200 cif-m0 { 2201 cif_clkout_m0: cif-clkout-m0 { 2202 rockchip,pins = 2203 <2 RK_PB3 1 &pcfg_pull_none>; 2204 }; 2205 2206 dvp_d2d9_m0: dvp-d2d9-m0 { 2207 rockchip,pins = 2208 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2209 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2210 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2211 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2212 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2213 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2214 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2215 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2216 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2217 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2218 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2219 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2220 }; 2221 2222 dvp_d0d1_m0: dvp-d0d1-m0 { 2223 rockchip,pins = 2224 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2225 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2226 }; 2227 2228 dvp_d10d11_m0:d10-d11-m0 { 2229 rockchip,pins = 2230 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2231 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2232 }; 2233 }; 2234 2235 cif-m1 { 2236 cif_clkout_m1: cif-clkout-m1 { 2237 rockchip,pins = 2238 <3 RK_PD0 3 &pcfg_pull_none>; 2239 }; 2240 2241 dvp_d2d9_m1: dvp-d2d9-m1 { 2242 rockchip,pins = 2243 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2244 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2245 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2246 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2247 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2248 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2249 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2250 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2251 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2252 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2253 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2254 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2255 }; 2256 2257 dvp_d0d1_m1: dvp-d0d1-m1 { 2258 rockchip,pins = 2259 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2260 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2261 }; 2262 2263 dvp_d10d11_m1:d10-d11-m1 { 2264 rockchip,pins = 2265 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2266 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2267 }; 2268 }; 2269 2270 isp { 2271 isp_prelight: isp-prelight { 2272 rockchip,pins = 2273 <3 RK_PD1 4 &pcfg_pull_none>; 2274 }; 2275 }; 2276 }; 2277}; 2278