1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/types.h>
10 #include <linux/cpu.h>
11 #include <asm/cpu.h>
12 #include <asm/cputype.h>
13 #include <asm/cpufeature.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/smp_plat.h>
16
17 static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities * entry,int scope)18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
19 {
20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
24 if (!is_midr_in_range(midr, &entry->midr_range))
25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
34 }
35
36 static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities * entry,int scope)37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
39 {
40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
42 }
43
44 static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities * entry,int scope)45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46 {
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
55 return model == entry->midr_range.model;
56 }
57
58 static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities * entry,int scope)59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
61 {
62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
65
66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
88 }
89
90 static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities * cap)91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
92 {
93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
94 bool enable_uct_trap = false;
95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
107 }
108
109 #ifdef CONFIG_ARM64_ERRATUM_1463225
110 static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities * entry,int scope)111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
112 int scope)
113 {
114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
115 }
116 #endif
117
118 static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities * __unused)119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
120 {
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
122 }
123
124 static DEFINE_RAW_SPINLOCK(reg_user_mask_modification);
125 static void __maybe_unused
cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities * __unused)126 cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused)
127 {
128 struct arm64_ftr_reg *regp;
129
130 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
131 if (!regp)
132 return;
133
134 raw_spin_lock(®_user_mask_modification);
135 if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK)
136 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
137 raw_spin_unlock(®_user_mask_modification);
138 }
139
140 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
141 .matches = is_affected_midr_range, \
142 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
143
144 #define CAP_MIDR_ALL_VERSIONS(model) \
145 .matches = is_affected_midr_range, \
146 .midr_range = MIDR_ALL_VERSIONS(model)
147
148 #define MIDR_FIXED(rev, revidr_mask) \
149 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
150
151 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
152 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
153 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
154
155 #define CAP_MIDR_RANGE_LIST(list) \
156 .matches = is_affected_midr_range_list, \
157 .midr_range_list = list
158
159 /* Errata affecting a range of revisions of given model variant */
160 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
161 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
162
163 /* Errata affecting a single variant/revision of a model */
164 #define ERRATA_MIDR_REV(model, var, rev) \
165 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
166
167 /* Errata affecting all variants/revisions of a given a model */
168 #define ERRATA_MIDR_ALL_VERSIONS(model) \
169 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
170 CAP_MIDR_ALL_VERSIONS(model)
171
172 /* Errata affecting a list of midr ranges, with same work around */
173 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
174 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
175 CAP_MIDR_RANGE_LIST(midr_list)
176
177 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
178 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
179 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
180 {},
181 };
182
183 static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities * entry,int scope)184 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
185 int scope)
186 {
187 int i;
188
189 if (!is_affected_midr_range_list(entry, scope) ||
190 !is_hyp_mode_available())
191 return false;
192
193 for_each_possible_cpu(i) {
194 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
195 return true;
196 }
197
198 return false;
199 }
200
201 static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities * entry,int scope)202 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
203 int scope)
204 {
205 u32 midr = read_cpuid_id();
206 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
207 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
208
209 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
210 return is_midr_in_range(midr, &range) && has_dic;
211 }
212
213 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
214 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
215 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
216 {
217 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
218 },
219 {
220 .midr_range.model = MIDR_QCOM_KRYO,
221 .matches = is_kryo_midr,
222 },
223 #endif
224 #ifdef CONFIG_ARM64_ERRATUM_1286807
225 {
226 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
227 },
228 {
229 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
230 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
231 },
232 #endif
233 #ifdef CONFIG_ARM64_ERRATUM_2441007
234 {
235 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
236 },
237 #endif
238 #ifdef CONFIG_ARM64_ERRATUM_2441009
239 {
240 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
241 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
242 },
243 #endif
244 {},
245 };
246 #endif
247
248 #ifdef CONFIG_CAVIUM_ERRATUM_27456
249 const struct midr_range cavium_erratum_27456_cpus[] = {
250 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
251 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
252 /* Cavium ThunderX, T81 pass 1.0 */
253 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
254 {},
255 };
256 #endif
257
258 #ifdef CONFIG_CAVIUM_ERRATUM_30115
259 static const struct midr_range cavium_erratum_30115_cpus[] = {
260 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
261 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
262 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
263 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
264 /* Cavium ThunderX, T83 pass 1.0 */
265 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
266 {},
267 };
268 #endif
269
270 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
271 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
272 {
273 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
274 },
275 {
276 .midr_range.model = MIDR_QCOM_KRYO,
277 .matches = is_kryo_midr,
278 },
279 {},
280 };
281 #endif
282
283 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
284 static const struct midr_range workaround_clean_cache[] = {
285 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
286 defined(CONFIG_ARM64_ERRATUM_827319) || \
287 defined(CONFIG_ARM64_ERRATUM_824069)
288 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
289 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
290 #endif
291 #ifdef CONFIG_ARM64_ERRATUM_819472
292 /* Cortex-A53 r0p[01] : ARM errata 819472 */
293 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
294 #endif
295 {},
296 };
297 #endif
298
299 #ifdef CONFIG_ARM64_ERRATUM_1418040
300 /*
301 * - 1188873 affects r0p0 to r2p0
302 * - 1418040 affects r0p0 to r3p1
303 */
304 static const struct midr_range erratum_1418040_list[] = {
305 /* Cortex-A76 r0p0 to r3p1 */
306 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
307 /* Neoverse-N1 r0p0 to r3p1 */
308 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
309 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
310 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
311 {},
312 };
313 #endif
314
315 #ifdef CONFIG_ARM64_ERRATUM_845719
316 static const struct midr_range erratum_845719_list[] = {
317 /* Cortex-A53 r0p[01234] */
318 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
319 /* Brahma-B53 r0p[0] */
320 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
321 /* Kryo2XX Silver rAp4 */
322 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
323 {},
324 };
325 #endif
326
327 #ifdef CONFIG_ARM64_ERRATUM_843419
328 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
329 {
330 /* Cortex-A53 r0p[01234] */
331 .matches = is_affected_midr_range,
332 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
333 MIDR_FIXED(0x4, BIT(8)),
334 },
335 {
336 /* Brahma-B53 r0p[0] */
337 .matches = is_affected_midr_range,
338 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
339 },
340 {},
341 };
342 #endif
343
344 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
345 static const struct midr_range erratum_speculative_at_list[] = {
346 #ifdef CONFIG_ARM64_ERRATUM_1165522
347 /* Cortex A76 r0p0 to r2p0 */
348 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
349 #endif
350 #ifdef CONFIG_ARM64_ERRATUM_1319367
351 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
352 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
353 #endif
354 #ifdef CONFIG_ARM64_ERRATUM_1530923
355 /* Cortex A55 r0p0 to r2p0 */
356 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
357 /* Kryo4xx Silver (rdpe => r1p0) */
358 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
359 #endif
360 {},
361 };
362 #endif
363
364 #ifdef CONFIG_ARM64_ERRATUM_1463225
365 static const struct midr_range erratum_1463225[] = {
366 /* Cortex-A76 r0p0 - r3p1 */
367 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
368 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
369 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
370 {},
371 };
372 #endif
373
374 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
375 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
376 #ifdef CONFIG_ARM64_ERRATUM_2139208
377 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
378 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
379 #endif
380 #ifdef CONFIG_ARM64_ERRATUM_2119858
381 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
382 #endif
383 {},
384 };
385 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
386
387 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
388 static const struct midr_range tsb_flush_fail_cpus[] = {
389 #ifdef CONFIG_ARM64_ERRATUM_2067961
390 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
391 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
392 #endif
393 #ifdef CONFIG_ARM64_ERRATUM_2054223
394 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
395 #endif
396 {},
397 };
398 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
399
400 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
401 static struct midr_range trbe_write_out_of_range_cpus[] = {
402 #ifdef CONFIG_ARM64_ERRATUM_2253138
403 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
404 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
405 #endif
406 #ifdef CONFIG_ARM64_ERRATUM_2224489
407 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
408 #endif
409 {},
410 };
411 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
412
413 #ifdef CONFIG_ARM64_ERRATUM_1742098
414 static struct midr_range broken_aarch32_aes[] = {
415 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
416 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
417 {},
418 };
419 #endif
420
421 const struct arm64_cpu_capabilities arm64_errata[] = {
422 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
423 {
424 .desc = "ARM errata 826319, 827319, 824069, or 819472",
425 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
426 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
427 .cpu_enable = cpu_enable_cache_maint_trap,
428 },
429 #endif
430 #ifdef CONFIG_ARM64_ERRATUM_832075
431 {
432 /* Cortex-A57 r0p0 - r1p2 */
433 .desc = "ARM erratum 832075",
434 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
435 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
436 0, 0,
437 1, 2),
438 },
439 #endif
440 #ifdef CONFIG_ARM64_ERRATUM_834220
441 {
442 /* Cortex-A57 r0p0 - r1p2 */
443 .desc = "ARM erratum 834220",
444 .capability = ARM64_WORKAROUND_834220,
445 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
446 0, 0,
447 1, 2),
448 },
449 #endif
450 #ifdef CONFIG_ARM64_ERRATUM_843419
451 {
452 .desc = "ARM erratum 843419",
453 .capability = ARM64_WORKAROUND_843419,
454 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
455 .matches = cpucap_multi_entry_cap_matches,
456 .match_list = erratum_843419_list,
457 },
458 #endif
459 #ifdef CONFIG_ARM64_ERRATUM_845719
460 {
461 .desc = "ARM erratum 845719",
462 .capability = ARM64_WORKAROUND_845719,
463 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
464 },
465 #endif
466 #ifdef CONFIG_CAVIUM_ERRATUM_23154
467 {
468 /* Cavium ThunderX, pass 1.x */
469 .desc = "Cavium erratum 23154",
470 .capability = ARM64_WORKAROUND_CAVIUM_23154,
471 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
472 },
473 #endif
474 #ifdef CONFIG_CAVIUM_ERRATUM_27456
475 {
476 .desc = "Cavium erratum 27456",
477 .capability = ARM64_WORKAROUND_CAVIUM_27456,
478 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
479 },
480 #endif
481 #ifdef CONFIG_CAVIUM_ERRATUM_30115
482 {
483 .desc = "Cavium erratum 30115",
484 .capability = ARM64_WORKAROUND_CAVIUM_30115,
485 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
486 },
487 #endif
488 {
489 .desc = "Mismatched cache type (CTR_EL0)",
490 .capability = ARM64_MISMATCHED_CACHE_TYPE,
491 .matches = has_mismatched_cache_type,
492 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
493 .cpu_enable = cpu_enable_trap_ctr_access,
494 },
495 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
496 {
497 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
498 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
499 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
500 .matches = cpucap_multi_entry_cap_matches,
501 .match_list = qcom_erratum_1003_list,
502 },
503 #endif
504 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
505 {
506 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
507 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
508 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
509 .matches = cpucap_multi_entry_cap_matches,
510 .match_list = arm64_repeat_tlbi_list,
511 },
512 #endif
513 #ifdef CONFIG_ARM64_ERRATUM_858921
514 {
515 /* Cortex-A73 all versions */
516 .desc = "ARM erratum 858921",
517 .capability = ARM64_WORKAROUND_858921,
518 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
519 },
520 #endif
521 {
522 .desc = "Spectre-v2",
523 .capability = ARM64_SPECTRE_V2,
524 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
525 .matches = has_spectre_v2,
526 .cpu_enable = spectre_v2_enable_mitigation,
527 },
528 #ifdef CONFIG_RANDOMIZE_BASE
529 {
530 /* Must come after the Spectre-v2 entry */
531 .desc = "Spectre-v3a",
532 .capability = ARM64_SPECTRE_V3A,
533 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
534 .matches = has_spectre_v3a,
535 .cpu_enable = spectre_v3a_enable_mitigation,
536 },
537 #endif
538 {
539 .desc = "Spectre-v4",
540 .capability = ARM64_SPECTRE_V4,
541 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
542 .matches = has_spectre_v4,
543 .cpu_enable = spectre_v4_enable_mitigation,
544 },
545 {
546 .desc = "Spectre-BHB",
547 .capability = ARM64_SPECTRE_BHB,
548 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
549 .matches = is_spectre_bhb_affected,
550 .cpu_enable = spectre_bhb_enable_mitigation,
551 },
552 #ifdef CONFIG_ARM64_ERRATUM_1418040
553 {
554 .desc = "ARM erratum 1418040",
555 .capability = ARM64_WORKAROUND_1418040,
556 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
557 /*
558 * We need to allow affected CPUs to come in late, but
559 * also need the non-affected CPUs to be able to come
560 * in at any point in time. Wonderful.
561 */
562 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
563 },
564 #endif
565 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
566 {
567 .desc = "ARM errata 1165522, 1319367, or 1530923",
568 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
569 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
570 },
571 #endif
572 #ifdef CONFIG_ARM64_ERRATUM_1463225
573 {
574 .desc = "ARM erratum 1463225",
575 .capability = ARM64_WORKAROUND_1463225,
576 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
577 .matches = has_cortex_a76_erratum_1463225,
578 .midr_range_list = erratum_1463225,
579 },
580 #endif
581 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
582 {
583 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
584 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
585 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
586 .matches = needs_tx2_tvm_workaround,
587 },
588 {
589 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
590 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
591 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
592 },
593 #endif
594 #ifdef CONFIG_ARM64_ERRATUM_1542419
595 {
596 /* we depend on the firmware portion for correctness */
597 .desc = "ARM erratum 1542419 (kernel portion)",
598 .capability = ARM64_WORKAROUND_1542419,
599 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
600 .matches = has_neoverse_n1_erratum_1542419,
601 .cpu_enable = cpu_enable_trap_ctr_access,
602 },
603 #endif
604 #ifdef CONFIG_ARM64_ERRATUM_1508412
605 {
606 /* we depend on the firmware portion for correctness */
607 .desc = "ARM erratum 1508412 (kernel portion)",
608 .capability = ARM64_WORKAROUND_1508412,
609 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
610 0, 0,
611 1, 0),
612 },
613 #endif
614 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
615 {
616 /* NVIDIA Carmel */
617 .desc = "NVIDIA Carmel CNP erratum",
618 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
619 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
620 },
621 #endif
622 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
623 {
624 /*
625 * The erratum work around is handled within the TRBE
626 * driver and can be applied per-cpu. So, we can allow
627 * a late CPU to come online with this erratum.
628 */
629 .desc = "ARM erratum 2119858 or 2139208",
630 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
631 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
632 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
633 },
634 #endif
635 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
636 {
637 .desc = "ARM erratum 2067961 or 2054223",
638 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
639 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
640 },
641 #endif
642 #ifdef CONFIG_ARM64_ERRATUM_2457168
643 {
644 .desc = "ARM erratum 2457168",
645 .capability = ARM64_WORKAROUND_2457168,
646 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
647 /* Cortex-A510 r0p0-r1p1 */
648 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
649 },
650 #endif
651 #ifdef CONFIG_ARM64_ERRATUM_1742098
652 {
653 .desc = "ARM erratum 1742098",
654 .capability = ARM64_WORKAROUND_1742098,
655 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
656 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
657 },
658 #endif
659 #ifdef CONFIG_ARM64_ERRATUM_2658417
660 {
661 .desc = "ARM erratum 2658417",
662 .capability = ARM64_WORKAROUND_2658417,
663 /* Cortex-A510 r0p0 - r1p1 */
664 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
665 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
666 .cpu_enable = cpu_clear_bf16_from_user_emulation,
667 },
668 #endif
669 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
670 {
671 .desc = "ARM erratum 2253138 or 2224489",
672 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
673 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
674 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
675 },
676 #endif
677 {
678 }
679 };
680