1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32 .macro clear_gp_regs 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 34 mov x\n, xzr 35 .endr 36 .endm 37 38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 39 .align 7 40.Lventry_start\@: 41 .if \el == 0 42 /* 43 * This must be the first instruction of the EL0 vector entries. It is 44 * skipped by the trampoline vectors, to trigger the cleanup. 45 */ 46 b .Lskip_tramp_vectors_cleanup\@ 47 .if \regsize == 64 48 mrs x30, tpidrro_el0 49 msr tpidrro_el0, xzr 50 .else 51 mov x30, xzr 52 .endif 53.Lskip_tramp_vectors_cleanup\@: 54 .endif 55 56 sub sp, sp, #PT_REGS_SIZE 57#ifdef CONFIG_VMAP_STACK 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99#endif 100 b el\el\ht\()_\regsize\()_\label 101.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 102 .endm 103 104 .macro tramp_alias, dst, sym, tmp 105 mov_q \dst, TRAMP_VALIAS 106 adr_l \tmp, \sym 107 add \dst, \dst, \tmp 108 adr_l \tmp, .entry.tramp.text 109 sub \dst, \dst, \tmp 110 .endm 111 112 /* 113 * This macro corrupts x0-x3. It is the caller's duty to save/restore 114 * them if required. 115 */ 116 .macro apply_ssbd, state, tmp1, tmp2 117alternative_cb spectre_v4_patch_fw_mitigation_enable 118 b .L__asm_ssbd_skip\@ // Patched to NOP 119alternative_cb_end 120 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 121 cbz \tmp2, .L__asm_ssbd_skip\@ 122 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 123 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 124 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 125 mov w1, #\state 126alternative_cb smccc_patch_fw_mitigation_conduit 127 nop // Patched to SMC/HVC #0 128alternative_cb_end 129.L__asm_ssbd_skip\@: 130 .endm 131 132 /* Check for MTE asynchronous tag check faults */ 133 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 134#ifdef CONFIG_ARM64_MTE 135 .arch_extension lse 136alternative_if_not ARM64_MTE 137 b 1f 138alternative_else_nop_endif 139 /* 140 * Asynchronous tag check faults are only possible in ASYNC (2) or 141 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 142 * set, so skip the check if it is unset. 143 */ 144 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 145 mrs_s \tmp, SYS_TFSRE0_EL1 146 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 147 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 148 mov \tmp, #_TIF_MTE_ASYNC_FAULT 149 add \ti_flags, tsk, #TSK_TI_FLAGS 150 stset \tmp, [\ti_flags] 1511: 152#endif 153 .endm 154 155 /* Clear the MTE asynchronous tag check faults */ 156 .macro clear_mte_async_tcf thread_sctlr 157#ifdef CONFIG_ARM64_MTE 158alternative_if ARM64_MTE 159 /* See comment in check_mte_async_tcf above. */ 160 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 161 dsb ish 162 msr_s SYS_TFSRE0_EL1, xzr 1631: 164alternative_else_nop_endif 165#endif 166 .endm 167 168 .macro mte_set_gcr, mte_ctrl, tmp 169#ifdef CONFIG_ARM64_MTE 170 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 171 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 172 msr_s SYS_GCR_EL1, \tmp 173#endif 174 .endm 175 176 .macro mte_set_kernel_gcr, tmp, tmp2 177#ifdef CONFIG_KASAN_HW_TAGS 178alternative_cb kasan_hw_tags_enable 179 b 1f 180alternative_cb_end 181 mov \tmp, KERNEL_GCR_EL1 182 msr_s SYS_GCR_EL1, \tmp 1831: 184#endif 185 .endm 186 187 .macro mte_set_user_gcr, tsk, tmp, tmp2 188#ifdef CONFIG_KASAN_HW_TAGS 189alternative_cb kasan_hw_tags_enable 190 b 1f 191alternative_cb_end 192 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 193 194 mte_set_gcr \tmp, \tmp2 1951: 196#endif 197 .endm 198 199 .macro kernel_entry, el, regsize = 64 200 .if \regsize == 32 201 mov w0, w0 // zero upper 32 bits of x0 202 .endif 203 stp x0, x1, [sp, #16 * 0] 204 stp x2, x3, [sp, #16 * 1] 205 stp x4, x5, [sp, #16 * 2] 206 stp x6, x7, [sp, #16 * 3] 207 stp x8, x9, [sp, #16 * 4] 208 stp x10, x11, [sp, #16 * 5] 209 stp x12, x13, [sp, #16 * 6] 210 stp x14, x15, [sp, #16 * 7] 211 stp x16, x17, [sp, #16 * 8] 212 stp x18, x19, [sp, #16 * 9] 213 stp x20, x21, [sp, #16 * 10] 214 stp x22, x23, [sp, #16 * 11] 215 stp x24, x25, [sp, #16 * 12] 216 stp x26, x27, [sp, #16 * 13] 217 stp x28, x29, [sp, #16 * 14] 218 219 .if \el == 0 220 clear_gp_regs 221 mrs x21, sp_el0 222 ldr_this_cpu tsk, __entry_task, x20 223 msr sp_el0, tsk 224 225 /* 226 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 227 * when scheduling. 228 */ 229 ldr x19, [tsk, #TSK_TI_FLAGS] 230 disable_step_tsk x19, x20 231 232 /* Check for asynchronous tag check faults in user space */ 233 ldr x0, [tsk, THREAD_SCTLR_USER] 234 check_mte_async_tcf x22, x23, x0 235 236#ifdef CONFIG_ARM64_PTR_AUTH 237alternative_if ARM64_HAS_ADDRESS_AUTH 238 /* 239 * Enable IA for in-kernel PAC if the task had it disabled. Although 240 * this could be implemented with an unconditional MRS which would avoid 241 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 242 * 243 * Install the kernel IA key only if IA was enabled in the task. If IA 244 * was disabled on kernel exit then we would have left the kernel IA 245 * installed so there is no need to install it again. 246 */ 247 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 248 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 249 b 2f 2501: 251 mrs x0, sctlr_el1 252 orr x0, x0, SCTLR_ELx_ENIA 253 msr sctlr_el1, x0 2542: 255alternative_else_nop_endif 256#endif 257 258 apply_ssbd 1, x22, x23 259 260 mte_set_kernel_gcr x22, x23 261 262 /* 263 * Any non-self-synchronizing system register updates required for 264 * kernel entry should be placed before this point. 265 */ 266alternative_if ARM64_MTE 267 isb 268 b 1f 269alternative_else_nop_endif 270alternative_if ARM64_HAS_ADDRESS_AUTH 271 isb 272alternative_else_nop_endif 2731: 274 275 scs_load_current 276 .else 277 add x21, sp, #PT_REGS_SIZE 278 get_current_task tsk 279 .endif /* \el == 0 */ 280 mrs x22, elr_el1 281 mrs x23, spsr_el1 282 stp lr, x21, [sp, #S_LR] 283 284 /* 285 * For exceptions from EL0, create a final frame record. 286 * For exceptions from EL1, create a synthetic frame record so the 287 * interrupted code shows up in the backtrace. 288 */ 289 .if \el == 0 290 stp xzr, xzr, [sp, #S_STACKFRAME] 291 .else 292 stp x29, x22, [sp, #S_STACKFRAME] 293 .endif 294 add x29, sp, #S_STACKFRAME 295 296#ifdef CONFIG_ARM64_SW_TTBR0_PAN 297alternative_if_not ARM64_HAS_PAN 298 bl __swpan_entry_el\el 299alternative_else_nop_endif 300#endif 301 302 stp x22, x23, [sp, #S_PC] 303 304 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 305 .if \el == 0 306 mov w21, #NO_SYSCALL 307 str w21, [sp, #S_SYSCALLNO] 308 .endif 309 310 /* Save pmr */ 311alternative_if ARM64_HAS_IRQ_PRIO_MASKING 312 mrs_s x20, SYS_ICC_PMR_EL1 313 str x20, [sp, #S_PMR_SAVE] 314 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 315 msr_s SYS_ICC_PMR_EL1, x20 316alternative_else_nop_endif 317 318 /* 319 * Registers that may be useful after this macro is invoked: 320 * 321 * x20 - ICC_PMR_EL1 322 * x21 - aborted SP 323 * x22 - aborted PC 324 * x23 - aborted PSTATE 325 */ 326 .endm 327 328 .macro kernel_exit, el 329 .if \el != 0 330 disable_daif 331 .endif 332 333 /* Restore pmr */ 334alternative_if ARM64_HAS_IRQ_PRIO_MASKING 335 ldr x20, [sp, #S_PMR_SAVE] 336 msr_s SYS_ICC_PMR_EL1, x20 337 mrs_s x21, SYS_ICC_CTLR_EL1 338 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 339 dsb sy // Ensure priority change is seen by redistributor 340.L__skip_pmr_sync\@: 341alternative_else_nop_endif 342 343 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 344 345#ifdef CONFIG_ARM64_SW_TTBR0_PAN 346alternative_if_not ARM64_HAS_PAN 347 bl __swpan_exit_el\el 348alternative_else_nop_endif 349#endif 350 351 .if \el == 0 352 ldr x23, [sp, #S_SP] // load return stack pointer 353 msr sp_el0, x23 354 tst x22, #PSR_MODE32_BIT // native task? 355 b.eq 3f 356 357#ifdef CONFIG_ARM64_ERRATUM_845719 358alternative_if ARM64_WORKAROUND_845719 359#ifdef CONFIG_PID_IN_CONTEXTIDR 360 mrs x29, contextidr_el1 361 msr contextidr_el1, x29 362#else 363 msr contextidr_el1, xzr 364#endif 365alternative_else_nop_endif 366#endif 3673: 368 scs_save tsk 369 370 /* Ignore asynchronous tag check faults in the uaccess routines */ 371 ldr x0, [tsk, THREAD_SCTLR_USER] 372 clear_mte_async_tcf x0 373 374#ifdef CONFIG_ARM64_PTR_AUTH 375alternative_if ARM64_HAS_ADDRESS_AUTH 376 /* 377 * IA was enabled for in-kernel PAC. Disable it now if needed, or 378 * alternatively install the user's IA. All other per-task keys and 379 * SCTLR bits were updated on task switch. 380 * 381 * No kernel C function calls after this. 382 */ 383 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 384 __ptrauth_keys_install_user tsk, x0, x1, x2 385 b 2f 3861: 387 mrs x0, sctlr_el1 388 bic x0, x0, SCTLR_ELx_ENIA 389 msr sctlr_el1, x0 3902: 391alternative_else_nop_endif 392#endif 393 394 mte_set_user_gcr tsk, x0, x1 395 396 apply_ssbd 0, x0, x1 397 .endif 398 399 msr elr_el1, x21 // set up the return data 400 msr spsr_el1, x22 401 ldp x0, x1, [sp, #16 * 0] 402 ldp x2, x3, [sp, #16 * 1] 403 ldp x4, x5, [sp, #16 * 2] 404 ldp x6, x7, [sp, #16 * 3] 405 ldp x8, x9, [sp, #16 * 4] 406 ldp x10, x11, [sp, #16 * 5] 407 ldp x12, x13, [sp, #16 * 6] 408 ldp x14, x15, [sp, #16 * 7] 409 ldp x16, x17, [sp, #16 * 8] 410 ldp x18, x19, [sp, #16 * 9] 411 ldp x20, x21, [sp, #16 * 10] 412 ldp x22, x23, [sp, #16 * 11] 413 ldp x24, x25, [sp, #16 * 12] 414 ldp x26, x27, [sp, #16 * 13] 415 ldp x28, x29, [sp, #16 * 14] 416 417 .if \el == 0 418alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 419 ldr lr, [sp, #S_LR] 420 add sp, sp, #PT_REGS_SIZE // restore sp 421 eret 422alternative_else_nop_endif 423#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 424 bne 4f 425 msr far_el1, x29 426 tramp_alias x30, tramp_exit_native, x29 427 br x30 4284: 429 tramp_alias x30, tramp_exit_compat, x29 430 br x30 431#endif 432 .else 433 ldr lr, [sp, #S_LR] 434 add sp, sp, #PT_REGS_SIZE // restore sp 435 436 /* Ensure any device/NC reads complete */ 437 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 438 439 eret 440 .endif 441 sb 442 .endm 443 444#ifdef CONFIG_ARM64_SW_TTBR0_PAN 445 /* 446 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 447 * EL0, there is no need to check the state of TTBR0_EL1 since 448 * accesses are always enabled. 449 * Note that the meaning of this bit differs from the ARMv8.1 PAN 450 * feature as all TTBR0_EL1 accesses are disabled, not just those to 451 * user mappings. 452 */ 453SYM_CODE_START_LOCAL(__swpan_entry_el1) 454 mrs x21, ttbr0_el1 455 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 456 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 457 b.eq 1f // TTBR0 access already disabled 458 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 459SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 460 __uaccess_ttbr0_disable x21 4611: ret 462SYM_CODE_END(__swpan_entry_el1) 463 464 /* 465 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 466 * PAN bit checking. 467 */ 468SYM_CODE_START_LOCAL(__swpan_exit_el1) 469 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 470 __uaccess_ttbr0_enable x0, x1 4711: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 472 ret 473SYM_CODE_END(__swpan_exit_el1) 474 475SYM_CODE_START_LOCAL(__swpan_exit_el0) 476 __uaccess_ttbr0_enable x0, x1 477 /* 478 * Enable errata workarounds only if returning to user. The only 479 * workaround currently required for TTBR0_EL1 changes are for the 480 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 481 * corruption). 482 */ 483 b post_ttbr_update_workaround 484SYM_CODE_END(__swpan_exit_el0) 485#endif 486 487/* GPRs used by entry code */ 488tsk .req x28 // current thread_info 489 490 .text 491 492/* 493 * Exception vectors. 494 */ 495 .pushsection ".entry.text", "ax" 496 497 .align 11 498SYM_CODE_START(vectors) 499 kernel_ventry 1, t, 64, sync // Synchronous EL1t 500 kernel_ventry 1, t, 64, irq // IRQ EL1t 501 kernel_ventry 1, t, 64, fiq // FIQ EL1h 502 kernel_ventry 1, t, 64, error // Error EL1t 503 504 kernel_ventry 1, h, 64, sync // Synchronous EL1h 505 kernel_ventry 1, h, 64, irq // IRQ EL1h 506 kernel_ventry 1, h, 64, fiq // FIQ EL1h 507 kernel_ventry 1, h, 64, error // Error EL1h 508 509 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 510 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 511 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 512 kernel_ventry 0, t, 64, error // Error 64-bit EL0 513 514 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 515 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 516 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 517 kernel_ventry 0, t, 32, error // Error 32-bit EL0 518SYM_CODE_END(vectors) 519 520#ifdef CONFIG_VMAP_STACK 521SYM_CODE_START_LOCAL(__bad_stack) 522 /* 523 * We detected an overflow in kernel_ventry, which switched to the 524 * overflow stack. Stash the exception regs, and head to our overflow 525 * handler. 526 */ 527 528 /* Restore the original x0 value */ 529 mrs x0, tpidrro_el0 530 531 /* 532 * Store the original GPRs to the new stack. The orginal SP (minus 533 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 534 */ 535 sub sp, sp, #PT_REGS_SIZE 536 kernel_entry 1 537 mrs x0, tpidr_el0 538 add x0, x0, #PT_REGS_SIZE 539 str x0, [sp, #S_SP] 540 541 /* Stash the regs for handle_bad_stack */ 542 mov x0, sp 543 544 /* Time to die */ 545 bl handle_bad_stack 546 ASM_BUG() 547SYM_CODE_END(__bad_stack) 548#endif /* CONFIG_VMAP_STACK */ 549 550 551 .macro entry_handler el:req, ht:req, regsize:req, label:req 552SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 553 kernel_entry \el, \regsize 554 mov x0, sp 555 bl el\el\ht\()_\regsize\()_\label\()_handler 556 .if \el == 0 557 b ret_to_user 558 .else 559 b ret_to_kernel 560 .endif 561SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 562 .endm 563 564/* 565 * Early exception handlers 566 */ 567 entry_handler 1, t, 64, sync 568 entry_handler 1, t, 64, irq 569 entry_handler 1, t, 64, fiq 570 entry_handler 1, t, 64, error 571 572 entry_handler 1, h, 64, sync 573 entry_handler 1, h, 64, irq 574 entry_handler 1, h, 64, fiq 575 entry_handler 1, h, 64, error 576 577 entry_handler 0, t, 64, sync 578 entry_handler 0, t, 64, irq 579 entry_handler 0, t, 64, fiq 580 entry_handler 0, t, 64, error 581 582 entry_handler 0, t, 32, sync 583 entry_handler 0, t, 32, irq 584 entry_handler 0, t, 32, fiq 585 entry_handler 0, t, 32, error 586 587SYM_CODE_START_LOCAL(ret_to_kernel) 588 kernel_exit 1 589SYM_CODE_END(ret_to_kernel) 590 591SYM_CODE_START_LOCAL(ret_to_user) 592 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 593 enable_step_tsk x19, x2 594#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 595 bl stackleak_erase 596#endif 597 kernel_exit 0 598SYM_CODE_END(ret_to_user) 599 600 .popsection // .entry.text 601 602 // Move from tramp_pg_dir to swapper_pg_dir 603 .macro tramp_map_kernel, tmp 604 mrs \tmp, ttbr1_el1 605 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 606 bic \tmp, \tmp, #USER_ASID_FLAG 607 msr ttbr1_el1, \tmp 608#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 609alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 610 /* ASID already in \tmp[63:48] */ 611 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 612 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 613 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 614 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 615 isb 616 tlbi vae1, \tmp 617 dsb nsh 618alternative_else_nop_endif 619#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 620 .endm 621 622 // Move from swapper_pg_dir to tramp_pg_dir 623 .macro tramp_unmap_kernel, tmp 624 mrs \tmp, ttbr1_el1 625 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 626 orr \tmp, \tmp, #USER_ASID_FLAG 627 msr ttbr1_el1, \tmp 628 /* 629 * We avoid running the post_ttbr_update_workaround here because 630 * it's only needed by Cavium ThunderX, which requires KPTI to be 631 * disabled. 632 */ 633 .endm 634 635 .macro tramp_data_page dst 636 adr_l \dst, .entry.tramp.text 637 sub \dst, \dst, PAGE_SIZE 638 .endm 639 640 .macro tramp_data_read_var dst, var 641#ifdef CONFIG_RANDOMIZE_BASE 642 tramp_data_page \dst 643 add \dst, \dst, #:lo12:__entry_tramp_data_\var 644 ldr \dst, [\dst] 645#else 646 ldr \dst, =\var 647#endif 648 .endm 649 650#define BHB_MITIGATION_NONE 0 651#define BHB_MITIGATION_LOOP 1 652#define BHB_MITIGATION_FW 2 653#define BHB_MITIGATION_INSN 3 654 655 .macro tramp_ventry, vector_start, regsize, kpti, bhb 656 .align 7 6571: 658 .if \regsize == 64 659 msr tpidrro_el0, x30 // Restored in kernel_ventry 660 .endif 661 662 .if \bhb == BHB_MITIGATION_LOOP 663 /* 664 * This sequence must appear before the first indirect branch. i.e. the 665 * ret out of tramp_ventry. It appears here because x30 is free. 666 */ 667 __mitigate_spectre_bhb_loop x30 668 .endif // \bhb == BHB_MITIGATION_LOOP 669 670 .if \bhb == BHB_MITIGATION_INSN 671 clearbhb 672 isb 673 .endif // \bhb == BHB_MITIGATION_INSN 674 675 .if \kpti == 1 676 /* 677 * Defend against branch aliasing attacks by pushing a dummy 678 * entry onto the return stack and using a RET instruction to 679 * enter the full-fat kernel vectors. 680 */ 681 bl 2f 682 b . 6832: 684 tramp_map_kernel x30 685alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 686 tramp_data_read_var x30, vectors 687alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 688 prfm plil1strm, [x30, #(1b - \vector_start)] 689alternative_else_nop_endif 690 691 msr vbar_el1, x30 692 isb 693 .else 694 ldr x30, =vectors 695 .endif // \kpti == 1 696 697 .if \bhb == BHB_MITIGATION_FW 698 /* 699 * The firmware sequence must appear before the first indirect branch. 700 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 701 * mapped to save/restore the registers the SMC clobbers. 702 */ 703 __mitigate_spectre_bhb_fw 704 .endif // \bhb == BHB_MITIGATION_FW 705 706 add x30, x30, #(1b - \vector_start + 4) 707 ret 708.org 1b + 128 // Did we overflow the ventry slot? 709 .endm 710 711 .macro tramp_exit, regsize = 64 712 tramp_data_read_var x30, this_cpu_vector 713 get_this_cpu_offset x29 714 ldr x30, [x30, x29] 715 716 msr vbar_el1, x30 717 ldr lr, [sp, #S_LR] 718 tramp_unmap_kernel x29 719 .if \regsize == 64 720 mrs x29, far_el1 721 .endif 722 add sp, sp, #PT_REGS_SIZE // restore sp 723 eret 724 sb 725 .endm 726 727 .macro generate_tramp_vector, kpti, bhb 728.Lvector_start\@: 729 .space 0x400 730 731 .rept 4 732 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 733 .endr 734 .rept 4 735 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 736 .endr 737 .endm 738 739#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 740/* 741 * Exception vectors trampoline. 742 * The order must match __bp_harden_el1_vectors and the 743 * arm64_bp_harden_el1_vectors enum. 744 */ 745 .pushsection ".entry.tramp.text", "ax" 746 .align 11 747SYM_CODE_START_NOALIGN(tramp_vectors) 748#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 749 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 750 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 751 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 752#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 753 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 754SYM_CODE_END(tramp_vectors) 755 756SYM_CODE_START(tramp_exit_native) 757 tramp_exit 758SYM_CODE_END(tramp_exit_native) 759 760SYM_CODE_START(tramp_exit_compat) 761 tramp_exit 32 762SYM_CODE_END(tramp_exit_compat) 763 764 .ltorg 765 .popsection // .entry.tramp.text 766#ifdef CONFIG_RANDOMIZE_BASE 767 .pushsection ".rodata", "a" 768 .align PAGE_SHIFT 769SYM_DATA_START(__entry_tramp_data_start) 770__entry_tramp_data_vectors: 771 .quad vectors 772#ifdef CONFIG_ARM_SDE_INTERFACE 773__entry_tramp_data___sdei_asm_handler: 774 .quad __sdei_asm_handler 775#endif /* CONFIG_ARM_SDE_INTERFACE */ 776__entry_tramp_data_this_cpu_vector: 777 .quad this_cpu_vector 778SYM_DATA_END(__entry_tramp_data_start) 779 .popsection // .rodata 780#endif /* CONFIG_RANDOMIZE_BASE */ 781#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 782 783/* 784 * Exception vectors for spectre mitigations on entry from EL1 when 785 * kpti is not in use. 786 */ 787 .macro generate_el1_vector, bhb 788.Lvector_start\@: 789 kernel_ventry 1, t, 64, sync // Synchronous EL1t 790 kernel_ventry 1, t, 64, irq // IRQ EL1t 791 kernel_ventry 1, t, 64, fiq // FIQ EL1h 792 kernel_ventry 1, t, 64, error // Error EL1t 793 794 kernel_ventry 1, h, 64, sync // Synchronous EL1h 795 kernel_ventry 1, h, 64, irq // IRQ EL1h 796 kernel_ventry 1, h, 64, fiq // FIQ EL1h 797 kernel_ventry 1, h, 64, error // Error EL1h 798 799 .rept 4 800 tramp_ventry .Lvector_start\@, 64, 0, \bhb 801 .endr 802 .rept 4 803 tramp_ventry .Lvector_start\@, 32, 0, \bhb 804 .endr 805 .endm 806 807/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 808 .pushsection ".entry.text", "ax" 809 .align 11 810SYM_CODE_START(__bp_harden_el1_vectors) 811#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 812 generate_el1_vector bhb=BHB_MITIGATION_LOOP 813 generate_el1_vector bhb=BHB_MITIGATION_FW 814 generate_el1_vector bhb=BHB_MITIGATION_INSN 815#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 816SYM_CODE_END(__bp_harden_el1_vectors) 817 .popsection 818 819 820/* 821 * Register switch for AArch64. The callee-saved registers need to be saved 822 * and restored. On entry: 823 * x0 = previous task_struct (must be preserved across the switch) 824 * x1 = next task_struct 825 * Previous and next are guaranteed not to be the same. 826 * 827 */ 828SYM_FUNC_START(cpu_switch_to) 829 mov x10, #THREAD_CPU_CONTEXT 830 add x8, x0, x10 831 mov x9, sp 832 stp x19, x20, [x8], #16 // store callee-saved registers 833 stp x21, x22, [x8], #16 834 stp x23, x24, [x8], #16 835 stp x25, x26, [x8], #16 836 stp x27, x28, [x8], #16 837 stp x29, x9, [x8], #16 838 str lr, [x8] 839 add x8, x1, x10 840 ldp x19, x20, [x8], #16 // restore callee-saved registers 841 ldp x21, x22, [x8], #16 842 ldp x23, x24, [x8], #16 843 ldp x25, x26, [x8], #16 844 ldp x27, x28, [x8], #16 845 ldp x29, x9, [x8], #16 846 ldr lr, [x8] 847 mov sp, x9 848 msr sp_el0, x1 849 ptrauth_keys_install_kernel x1, x8, x9, x10 850 scs_save x0 851 scs_load_current 852 ret 853SYM_FUNC_END(cpu_switch_to) 854NOKPROBE(cpu_switch_to) 855 856/* 857 * This is how we return from a fork. 858 */ 859SYM_CODE_START(ret_from_fork) 860 bl schedule_tail 861 cbz x19, 1f // not a kernel thread 862 mov x0, x20 863 blr x19 8641: get_current_task tsk 865 mov x0, sp 866 bl asm_exit_to_user_mode 867 b ret_to_user 868SYM_CODE_END(ret_from_fork) 869NOKPROBE(ret_from_fork) 870 871/* 872 * void call_on_irq_stack(struct pt_regs *regs, 873 * void (*func)(struct pt_regs *)); 874 * 875 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 876 */ 877SYM_FUNC_START(call_on_irq_stack) 878#ifdef CONFIG_SHADOW_CALL_STACK 879 get_current_task x16 880 scs_save x16 881 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 882#endif 883 884 /* Create a frame record to save our LR and SP (implicit in FP) */ 885 stp x29, x30, [sp, #-16]! 886 mov x29, sp 887 888 ldr_this_cpu x16, irq_stack_ptr, x17 889 890 /* Move to the new stack and call the function there */ 891 add sp, x16, #IRQ_STACK_SIZE 892 blr x1 893 894 /* 895 * Restore the SP from the FP, and restore the FP and LR from the frame 896 * record. 897 */ 898 mov sp, x29 899 ldp x29, x30, [sp], #16 900 scs_load_current 901 ret 902SYM_FUNC_END(call_on_irq_stack) 903NOKPROBE(call_on_irq_stack) 904 905#ifdef CONFIG_ARM_SDE_INTERFACE 906 907#include <asm/sdei.h> 908#include <uapi/linux/arm_sdei.h> 909 910.macro sdei_handler_exit exit_mode 911 /* On success, this call never returns... */ 912 cmp \exit_mode, #SDEI_EXIT_SMC 913 b.ne 99f 914 smc #0 915 b . 91699: hvc #0 917 b . 918.endm 919 920#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 921/* 922 * The regular SDEI entry point may have been unmapped along with the rest of 923 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 924 * argument accessible. 925 * 926 * This clobbers x4, __sdei_handler() will restore this from firmware's 927 * copy. 928 */ 929.ltorg 930.pushsection ".entry.tramp.text", "ax" 931SYM_CODE_START(__sdei_asm_entry_trampoline) 932 mrs x4, ttbr1_el1 933 tbz x4, #USER_ASID_BIT, 1f 934 935 tramp_map_kernel tmp=x4 936 isb 937 mov x4, xzr 938 939 /* 940 * Remember whether to unmap the kernel on exit. 941 */ 9421: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 943 tramp_data_read_var x4, __sdei_asm_handler 944 br x4 945SYM_CODE_END(__sdei_asm_entry_trampoline) 946NOKPROBE(__sdei_asm_entry_trampoline) 947 948/* 949 * Make the exit call and restore the original ttbr1_el1 950 * 951 * x0 & x1: setup for the exit API call 952 * x2: exit_mode 953 * x4: struct sdei_registered_event argument from registration time. 954 */ 955SYM_CODE_START(__sdei_asm_exit_trampoline) 956 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 957 cbnz x4, 1f 958 959 tramp_unmap_kernel tmp=x4 960 9611: sdei_handler_exit exit_mode=x2 962SYM_CODE_END(__sdei_asm_exit_trampoline) 963NOKPROBE(__sdei_asm_exit_trampoline) 964 .ltorg 965.popsection // .entry.tramp.text 966#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 967 968/* 969 * Software Delegated Exception entry point. 970 * 971 * x0: Event number 972 * x1: struct sdei_registered_event argument from registration time. 973 * x2: interrupted PC 974 * x3: interrupted PSTATE 975 * x4: maybe clobbered by the trampoline 976 * 977 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 978 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 979 * want them. 980 */ 981SYM_CODE_START(__sdei_asm_handler) 982 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 983 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 984 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 985 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 986 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 987 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 988 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 989 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 990 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 991 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 992 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 993 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 994 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 995 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 996 mov x4, sp 997 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 998 999 mov x19, x1 1000 1001 /* Store the registered-event for crash_smp_send_stop() */ 1002 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1003 cbnz w4, 1f 1004 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1005 b 2f 10061: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10072: str x19, [x5] 1008 1009#ifdef CONFIG_VMAP_STACK 1010 /* 1011 * entry.S may have been using sp as a scratch register, find whether 1012 * this is a normal or critical event and switch to the appropriate 1013 * stack for this CPU. 1014 */ 1015 cbnz w4, 1f 1016 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1017 b 2f 10181: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10192: mov x6, #SDEI_STACK_SIZE 1020 add x5, x5, x6 1021 mov sp, x5 1022#endif 1023 1024#ifdef CONFIG_SHADOW_CALL_STACK 1025 /* Use a separate shadow call stack for normal and critical events */ 1026 cbnz w4, 3f 1027 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1028 b 4f 10293: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10304: 1031#endif 1032 1033 /* 1034 * We may have interrupted userspace, or a guest, or exit-from or 1035 * return-to either of these. We can't trust sp_el0, restore it. 1036 */ 1037 mrs x28, sp_el0 1038 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1039 msr sp_el0, x0 1040 1041 /* If we interrupted the kernel point to the previous stack/frame. */ 1042 and x0, x3, #0xc 1043 mrs x1, CurrentEL 1044 cmp x0, x1 1045 csel x29, x29, xzr, eq // fp, or zero 1046 csel x4, x2, xzr, eq // elr, or zero 1047 1048 stp x29, x4, [sp, #-16]! 1049 mov x29, sp 1050 1051 add x0, x19, #SDEI_EVENT_INTREGS 1052 mov x1, x19 1053 bl __sdei_handler 1054 1055 msr sp_el0, x28 1056 /* restore regs >x17 that we clobbered */ 1057 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1058 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1059 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1060 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1061 mov sp, x1 1062 1063 mov x1, x0 // address to complete_and_resume 1064 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1065 cmp x0, #1 1066 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1067 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1068 csel x0, x2, x3, ls 1069 1070 ldr_l x2, sdei_exit_mode 1071 1072 /* Clear the registered-event seen by crash_smp_send_stop() */ 1073 ldrb w3, [x4, #SDEI_EVENT_PRIORITY] 1074 cbnz w3, 1f 1075 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1076 b 2f 10771: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10782: str xzr, [x5] 1079 1080alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1081 sdei_handler_exit exit_mode=x2 1082alternative_else_nop_endif 1083 1084#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1085 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3 1086 br x5 1087#endif 1088SYM_CODE_END(__sdei_asm_handler) 1089NOKPROBE(__sdei_asm_handler) 1090 1091SYM_CODE_START(__sdei_handler_abort) 1092 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1093 adr x1, 1f 1094 ldr_l x2, sdei_exit_mode 1095 sdei_handler_exit exit_mode=x2 1096 // exit the handler and jump to the next instruction. 1097 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx. 10981: ret 1099SYM_CODE_END(__sdei_handler_abort) 1100NOKPROBE(__sdei_handler_abort) 1101#endif /* CONFIG_ARM_SDE_INTERFACE */ 1102