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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <linux/pgtable.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/asm_pointer_auth.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/cpufeature.h>
19#include <asm/alternative.h>
20#include <asm/smp.h>
21#include <asm/sysreg.h>
22
23#ifdef CONFIG_ARM64_64K_PAGES
24#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
25#elif defined(CONFIG_ARM64_16K_PAGES)
26#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
27#else /* CONFIG_ARM64_4K_PAGES */
28#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
29#endif
30
31#ifdef CONFIG_RANDOMIZE_BASE
32#define TCR_KASLR_FLAGS	TCR_NFD1
33#else
34#define TCR_KASLR_FLAGS	0
35#endif
36
37#define TCR_SMP_FLAGS	TCR_SHARED
38
39/* PTWs cacheable, inner/outer WBWA */
40#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
41
42#ifdef CONFIG_KASAN_SW_TAGS
43#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
44#else
45#define TCR_KASAN_SW_FLAGS 0
46#endif
47
48#ifdef CONFIG_KASAN_HW_TAGS
49#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
50#elif defined(CONFIG_ARM64_MTE)
51/*
52 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
53 * TBI being enabled at EL1.
54 */
55#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
56#else
57#define TCR_MTE_FLAGS 0
58#endif
59
60/*
61 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
62 * changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
63 */
64#define MAIR_EL1_SET							\
65	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
66	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
67	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
68	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
69	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED) |		\
70	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_iNC_oWB, MT_NORMAL_iNC_oWB))
71
72#ifdef CONFIG_CPU_PM
73/**
74 * cpu_do_suspend - save CPU registers context
75 *
76 * x0: virtual address of context pointer
77 *
78 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
79 */
80SYM_FUNC_START(cpu_do_suspend)
81	mrs	x2, tpidr_el0
82	mrs	x3, tpidrro_el0
83	mrs	x4, contextidr_el1
84	mrs	x5, osdlr_el1
85	mrs	x6, cpacr_el1
86	mrs	x7, tcr_el1
87	mrs	x8, vbar_el1
88	mrs	x9, mdscr_el1
89	mrs	x10, oslsr_el1
90	mrs	x11, sctlr_el1
91	get_this_cpu_offset x12
92	mrs	x13, sp_el0
93	stp	x2, x3, [x0]
94	stp	x4, x5, [x0, #16]
95	stp	x6, x7, [x0, #32]
96	stp	x8, x9, [x0, #48]
97	stp	x10, x11, [x0, #64]
98	stp	x12, x13, [x0, #80]
99	/*
100	 * Save x18 as it may be used as a platform register, e.g. by shadow
101	 * call stack.
102	 */
103	str	x18, [x0, #96]
104	ret
105SYM_FUNC_END(cpu_do_suspend)
106
107/**
108 * cpu_do_resume - restore CPU register context
109 *
110 * x0: Address of context pointer
111 */
112	.pushsection ".idmap.text", "awx"
113SYM_FUNC_START(cpu_do_resume)
114	ldp	x2, x3, [x0]
115	ldp	x4, x5, [x0, #16]
116	ldp	x6, x8, [x0, #32]
117	ldp	x9, x10, [x0, #48]
118	ldp	x11, x12, [x0, #64]
119	ldp	x13, x14, [x0, #80]
120	/*
121	 * Restore x18, as it may be used as a platform register, and clear
122	 * the buffer to minimize the risk of exposure when used for shadow
123	 * call stack.
124	 */
125	ldr	x18, [x0, #96]
126	str	xzr, [x0, #96]
127	msr	tpidr_el0, x2
128	msr	tpidrro_el0, x3
129	msr	contextidr_el1, x4
130	msr	cpacr_el1, x6
131
132	/* Don't change t0sz here, mask those bits when restoring */
133	mrs	x7, tcr_el1
134	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
135
136	msr	tcr_el1, x8
137	msr	vbar_el1, x9
138
139	/*
140	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
141	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
142	 * exception. Mask them until local_daif_restore() in cpu_suspend()
143	 * resets them.
144	 */
145	disable_daif
146	msr	mdscr_el1, x10
147
148	msr	sctlr_el1, x12
149	set_this_cpu_offset x13
150	msr	sp_el0, x14
151	/*
152	 * Restore oslsr_el1 by writing oslar_el1
153	 */
154	msr	osdlr_el1, x5
155	ubfx	x11, x11, #1, #1
156	msr	oslar_el1, x11
157	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
158	reset_amuserenr_el0 x0			// Disable AMU access from EL0
159
160alternative_if ARM64_HAS_RAS_EXTN
161	msr_s	SYS_DISR_EL1, xzr
162alternative_else_nop_endif
163
164	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
165	isb
166	ret
167SYM_FUNC_END(cpu_do_resume)
168	.popsection
169#endif
170
171	.pushsection ".idmap.text", "awx"
172
173.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
174	adrp	\tmp1, reserved_pg_dir
175	phys_to_ttbr \tmp2, \tmp1
176	offset_ttbr1 \tmp2, \tmp1
177	msr	ttbr1_el1, \tmp2
178	isb
179	tlbi	vmalle1
180	dsb	nsh
181	isb
182.endm
183
184/*
185 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
186 *
187 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
188 * called by anything else. It can only be executed from a TTBR0 mapping.
189 */
190SYM_FUNC_START(idmap_cpu_replace_ttbr1)
191	save_and_disable_daif flags=x2
192
193	__idmap_cpu_set_reserved_ttbr1 x1, x3
194
195	offset_ttbr1 x0, x3
196	msr	ttbr1_el1, x0
197	isb
198
199	restore_daif x2
200
201	ret
202SYM_FUNC_END(idmap_cpu_replace_ttbr1)
203	.popsection
204
205#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
206	.pushsection ".idmap.text", "awx"
207
208	.macro	__idmap_kpti_get_pgtable_ent, type
209	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
210	dmb	sy				// lines are written back before
211	ldr	\type, [cur_\()\type\()p]	// loading the entry
212	tbz	\type, #0, skip_\()\type	// Skip invalid and
213	tbnz	\type, #11, skip_\()\type	// non-global entries
214	.endm
215
216	.macro __idmap_kpti_put_pgtable_ent_ng, type
217	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
218	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
219	dmb	sy				// that it is visible to all
220	dc	civac, cur_\()\type\()p		// CPUs.
221	.endm
222
223/*
224 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
225 *
226 * Called exactly once from stop_machine context by each CPU found during boot.
227 */
228__idmap_kpti_flag:
229	.long	1
230SYM_FUNC_START(idmap_kpti_install_ng_mappings)
231	cpu		.req	w0
232	num_cpus	.req	w1
233	swapper_pa	.req	x2
234	swapper_ttb	.req	x3
235	flag_ptr	.req	x4
236	cur_pgdp	.req	x5
237	end_pgdp	.req	x6
238	pgd		.req	x7
239	cur_pudp	.req	x8
240	end_pudp	.req	x9
241	pud		.req	x10
242	cur_pmdp	.req	x11
243	end_pmdp	.req	x12
244	pmd		.req	x13
245	cur_ptep	.req	x14
246	end_ptep	.req	x15
247	pte		.req	x16
248
249	mrs	swapper_ttb, ttbr1_el1
250	restore_ttbr1	swapper_ttb
251	adr	flag_ptr, __idmap_kpti_flag
252
253	cbnz	cpu, __idmap_kpti_secondary
254
255	/* We're the boot CPU. Wait for the others to catch up */
256	sevl
2571:	wfe
258	ldaxr	w17, [flag_ptr]
259	eor	w17, w17, num_cpus
260	cbnz	w17, 1b
261
262	/* We need to walk swapper, so turn off the MMU. */
263	pre_disable_mmu_workaround
264	mrs	x17, sctlr_el1
265	bic	x17, x17, #SCTLR_ELx_M
266	msr	sctlr_el1, x17
267	isb
268
269	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
270	/* PGD */
271	mov	cur_pgdp, swapper_pa
272	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
273do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
274	tbnz	pgd, #1, walk_puds
275next_pgd:
276	__idmap_kpti_put_pgtable_ent_ng	pgd
277skip_pgd:
278	add	cur_pgdp, cur_pgdp, #8
279	cmp	cur_pgdp, end_pgdp
280	b.ne	do_pgd
281
282	/* Publish the updated tables and nuke all the TLBs */
283	dsb	sy
284	tlbi	vmalle1is
285	dsb	ish
286	isb
287
288	/* We're done: fire up the MMU again */
289	mrs	x17, sctlr_el1
290	orr	x17, x17, #SCTLR_ELx_M
291	set_sctlr_el1	x17
292
293	/* Set the flag to zero to indicate that we're all done */
294	str	wzr, [flag_ptr]
295	ret
296
297	/* PUD */
298walk_puds:
299	.if CONFIG_PGTABLE_LEVELS > 3
300	pte_to_phys	cur_pudp, pgd
301	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
302do_pud:	__idmap_kpti_get_pgtable_ent	pud
303	tbnz	pud, #1, walk_pmds
304next_pud:
305	__idmap_kpti_put_pgtable_ent_ng	pud
306skip_pud:
307	add	cur_pudp, cur_pudp, 8
308	cmp	cur_pudp, end_pudp
309	b.ne	do_pud
310	b	next_pgd
311	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
312	mov	pud, pgd
313	b	walk_pmds
314next_pud:
315	b	next_pgd
316	.endif
317
318	/* PMD */
319walk_pmds:
320	.if CONFIG_PGTABLE_LEVELS > 2
321	pte_to_phys	cur_pmdp, pud
322	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
323do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
324	tbnz	pmd, #1, walk_ptes
325next_pmd:
326	__idmap_kpti_put_pgtable_ent_ng	pmd
327skip_pmd:
328	add	cur_pmdp, cur_pmdp, #8
329	cmp	cur_pmdp, end_pmdp
330	b.ne	do_pmd
331	b	next_pud
332	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
333	mov	pmd, pud
334	b	walk_ptes
335next_pmd:
336	b	next_pud
337	.endif
338
339	/* PTE */
340walk_ptes:
341	pte_to_phys	cur_ptep, pmd
342	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
343do_pte:	__idmap_kpti_get_pgtable_ent	pte
344	__idmap_kpti_put_pgtable_ent_ng	pte
345skip_pte:
346	add	cur_ptep, cur_ptep, #8
347	cmp	cur_ptep, end_ptep
348	b.ne	do_pte
349	b	next_pmd
350
351	.unreq	cpu
352	.unreq	num_cpus
353	.unreq	swapper_pa
354	.unreq	cur_pgdp
355	.unreq	end_pgdp
356	.unreq	pgd
357	.unreq	cur_pudp
358	.unreq	end_pudp
359	.unreq	pud
360	.unreq	cur_pmdp
361	.unreq	end_pmdp
362	.unreq	pmd
363	.unreq	cur_ptep
364	.unreq	end_ptep
365	.unreq	pte
366
367	/* Secondary CPUs end up here */
368__idmap_kpti_secondary:
369	/* Uninstall swapper before surgery begins */
370	__idmap_cpu_set_reserved_ttbr1 x16, x17
371
372	/* Increment the flag to let the boot CPU we're ready */
3731:	ldxr	w16, [flag_ptr]
374	add	w16, w16, #1
375	stxr	w17, w16, [flag_ptr]
376	cbnz	w17, 1b
377
378	/* Wait for the boot CPU to finish messing around with swapper */
379	sevl
3801:	wfe
381	ldxr	w16, [flag_ptr]
382	cbnz	w16, 1b
383
384	/* All done, act like nothing happened */
385	offset_ttbr1 swapper_ttb, x16
386	msr	ttbr1_el1, swapper_ttb
387	isb
388	ret
389
390	.unreq	swapper_ttb
391	.unreq	flag_ptr
392SYM_FUNC_END(idmap_kpti_install_ng_mappings)
393	.popsection
394#endif
395
396/*
397 *	__cpu_setup
398 *
399 *	Initialise the processor for turning the MMU on.
400 *
401 * Output:
402 *	Return in x0 the value of the SCTLR_EL1 register.
403 */
404	.pushsection ".idmap.text", "awx"
405SYM_FUNC_START(__cpu_setup)
406	tlbi	vmalle1				// Invalidate local TLB
407	dsb	nsh
408
409	mov	x1, #3 << 20
410	msr	cpacr_el1, x1			// Enable FP/ASIMD
411	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
412	msr	mdscr_el1, x1			// access to the DCC from EL0
413	isb					// Unmask debug exceptions now,
414	enable_dbg				// since this is per-cpu
415	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
416	reset_amuserenr_el0 x1			// Disable AMU access from EL0
417
418	/*
419	 * Default values for VMSA control registers. These will be adjusted
420	 * below depending on detected CPU features.
421	 */
422	mair	.req	x17
423	tcr	.req	x16
424	mov_q	mair, MAIR_EL1_SET
425	mov_q	tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
426			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
427			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
428
429	tcr_clear_errata_bits tcr, x9, x5
430
431#ifdef CONFIG_ARM64_VA_BITS_52
432	ldr_l		x9, vabits_actual
433	sub		x9, xzr, x9
434	add		x9, x9, #64
435	tcr_set_t1sz	tcr, x9
436#else
437	ldr_l		x9, idmap_t0sz
438#endif
439	tcr_set_t0sz	tcr, x9
440
441	/*
442	 * Set the IPS bits in TCR_EL1.
443	 */
444	tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
445#ifdef CONFIG_ARM64_HW_AFDBM
446	/*
447	 * Enable hardware update of the Access Flags bit.
448	 * Hardware dirty bit management is enabled later,
449	 * via capabilities.
450	 */
451	mrs	x9, ID_AA64MMFR1_EL1
452	and	x9, x9, #0xf
453	cbz	x9, 1f
454	orr	tcr, tcr, #TCR_HA		// hardware Access flag update
4551:
456#endif	/* CONFIG_ARM64_HW_AFDBM */
457	msr	mair_el1, mair
458	msr	tcr_el1, tcr
459	/*
460	 * Prepare SCTLR
461	 */
462	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
463	ret					// return to head.S
464
465	.unreq	mair
466	.unreq	tcr
467SYM_FUNC_END(__cpu_setup)
468