1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10 #include <linux/compiler.h>
11 #include <linux/vmalloc.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/console.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/memblock.h>
20 #include <linux/serial.h>
21 #include <linux/smp.h>
22 #include <linux/types.h>
23 #include <linux/string.h> /* for memset */
24 #include <linux/tty.h>
25 #include <linux/time.h>
26 #include <linux/platform_device.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial_8250.h>
29 #include <linux/of_fdt.h>
30 #include <linux/libfdt.h>
31 #include <linux/kexec.h>
32
33 #include <asm/processor.h>
34 #include <asm/reboot.h>
35 #include <asm/smp-ops.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/mipsregs.h>
38 #include <asm/bootinfo.h>
39 #include <asm/sections.h>
40 #include <asm/fw/fw.h>
41 #include <asm/setup.h>
42 #include <asm/prom.h>
43 #include <asm/time.h>
44
45 #include <asm/octeon/octeon.h>
46 #include <asm/octeon/pci-octeon.h>
47 #include <asm/octeon/cvmx-rst-defs.h>
48
49 /*
50 * TRUE for devices having registers with little-endian byte
51 * order, FALSE for registers with native-endian byte order.
52 * PCI mandates little-endian, USB and SATA are configuraable,
53 * but we chose little-endian for these.
54 */
55 const bool octeon_should_swizzle_table[256] = {
56 [0x00] = true, /* bootbus/CF */
57 [0x1b] = true, /* PCI mmio window */
58 [0x1c] = true, /* PCI mmio window */
59 [0x1d] = true, /* PCI mmio window */
60 [0x1e] = true, /* PCI mmio window */
61 [0x68] = true, /* OCTEON III USB */
62 [0x69] = true, /* OCTEON III USB */
63 [0x6c] = true, /* OCTEON III SATA */
64 [0x6f] = true, /* OCTEON II USB */
65 };
66 EXPORT_SYMBOL(octeon_should_swizzle_table);
67
68 #ifdef CONFIG_PCI
69 extern void pci_console_init(const char *arg);
70 #endif
71
72 static unsigned long long max_memory = ULLONG_MAX;
73 static unsigned long long reserve_low_mem;
74
75 DEFINE_SEMAPHORE(octeon_bootbus_sem);
76 EXPORT_SYMBOL(octeon_bootbus_sem);
77
78 static struct octeon_boot_descriptor *octeon_boot_desc_ptr;
79
80 struct cvmx_bootinfo *octeon_bootinfo;
81 EXPORT_SYMBOL(octeon_bootinfo);
82
83 #ifdef CONFIG_KEXEC
84 #ifdef CONFIG_SMP
85 /*
86 * Wait for relocation code is prepared and send
87 * secondary CPUs to spin until kernel is relocated.
88 */
octeon_kexec_smp_down(void * ignored)89 static void octeon_kexec_smp_down(void *ignored)
90 {
91 int cpu = smp_processor_id();
92
93 local_irq_disable();
94 set_cpu_online(cpu, false);
95 while (!atomic_read(&kexec_ready_to_reboot))
96 cpu_relax();
97
98 asm volatile (
99 " sync \n"
100 " synci ($0) \n");
101
102 kexec_reboot();
103 }
104 #endif
105
106 #define OCTEON_DDR0_BASE (0x0ULL)
107 #define OCTEON_DDR0_SIZE (0x010000000ULL)
108 #define OCTEON_DDR1_BASE (0x410000000ULL)
109 #define OCTEON_DDR1_SIZE (0x010000000ULL)
110 #define OCTEON_DDR2_BASE (0x020000000ULL)
111 #define OCTEON_DDR2_SIZE (0x3e0000000ULL)
112 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
113
114 static struct kimage *kimage_ptr;
115
kexec_bootmem_init(uint64_t mem_size,uint32_t low_reserved_bytes)116 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
117 {
118 int64_t addr;
119 struct cvmx_bootmem_desc *bootmem_desc;
120
121 bootmem_desc = cvmx_bootmem_get_desc();
122
123 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
124 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
125 pr_err("Error: requested memory too large,"
126 "truncating to maximum size\n");
127 }
128
129 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
130 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
131
132 addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
133 bootmem_desc->head_addr = 0;
134
135 if (mem_size <= OCTEON_DDR0_SIZE) {
136 __cvmx_bootmem_phy_free(addr,
137 mem_size - reserve_low_mem -
138 low_reserved_bytes, 0);
139 return;
140 }
141
142 __cvmx_bootmem_phy_free(addr,
143 OCTEON_DDR0_SIZE - reserve_low_mem -
144 low_reserved_bytes, 0);
145
146 mem_size -= OCTEON_DDR0_SIZE;
147
148 if (mem_size > OCTEON_DDR1_SIZE) {
149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
150 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
151 mem_size - OCTEON_DDR1_SIZE, 0);
152 } else
153 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
154 }
155
octeon_kexec_prepare(struct kimage * image)156 static int octeon_kexec_prepare(struct kimage *image)
157 {
158 int i;
159 char *bootloader = "kexec";
160
161 octeon_boot_desc_ptr->argc = 0;
162 for (i = 0; i < image->nr_segments; i++) {
163 if (!strncmp(bootloader, (char *)image->segment[i].buf,
164 strlen(bootloader))) {
165 /*
166 * convert command line string to array
167 * of parameters (as bootloader does).
168 */
169 int argc = 0, offt;
170 char *str = (char *)image->segment[i].buf;
171 char *ptr = strchr(str, ' ');
172 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
173 *ptr = '\0';
174 if (ptr[1] != ' ') {
175 offt = (int)(ptr - str + 1);
176 octeon_boot_desc_ptr->argv[argc] =
177 image->segment[i].mem + offt;
178 argc++;
179 }
180 ptr = strchr(ptr + 1, ' ');
181 }
182 octeon_boot_desc_ptr->argc = argc;
183 break;
184 }
185 }
186
187 /*
188 * Information about segments will be needed during pre-boot memory
189 * initialization.
190 */
191 kimage_ptr = image;
192 return 0;
193 }
194
octeon_generic_shutdown(void)195 static void octeon_generic_shutdown(void)
196 {
197 int i;
198 #ifdef CONFIG_SMP
199 int cpu;
200 #endif
201 struct cvmx_bootmem_desc *bootmem_desc;
202 void *named_block_array_ptr;
203
204 bootmem_desc = cvmx_bootmem_get_desc();
205 named_block_array_ptr =
206 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
207
208 #ifdef CONFIG_SMP
209 /* disable watchdogs */
210 for_each_online_cpu(cpu)
211 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
212 #else
213 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
214 #endif
215 if (kimage_ptr != kexec_crash_image) {
216 memset(named_block_array_ptr,
217 0x0,
218 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
219 sizeof(struct cvmx_bootmem_named_block_desc));
220 /*
221 * Mark all memory (except low 0x100000 bytes) as free.
222 * It is the same thing that bootloader does.
223 */
224 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
225 0x100000);
226 /*
227 * Allocate all segments to avoid their corruption during boot.
228 */
229 for (i = 0; i < kimage_ptr->nr_segments; i++)
230 cvmx_bootmem_alloc_address(
231 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
232 kimage_ptr->segment[i].mem - PAGE_SIZE,
233 PAGE_SIZE);
234 } else {
235 /*
236 * Do not mark all memory as free. Free only named sections
237 * leaving the rest of memory unchanged.
238 */
239 struct cvmx_bootmem_named_block_desc *ptr =
240 (struct cvmx_bootmem_named_block_desc *)
241 named_block_array_ptr;
242
243 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
244 if (ptr[i].size)
245 cvmx_bootmem_free_named(ptr[i].name);
246 }
247 kexec_args[2] = 1UL; /* running on octeon_main_processor */
248 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
249 #ifdef CONFIG_SMP
250 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
251 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
252 #endif
253 }
254
octeon_shutdown(void)255 static void octeon_shutdown(void)
256 {
257 octeon_generic_shutdown();
258 #ifdef CONFIG_SMP
259 smp_call_function(octeon_kexec_smp_down, NULL, 0);
260 smp_wmb();
261 while (num_online_cpus() > 1) {
262 cpu_relax();
263 mdelay(1);
264 }
265 #endif
266 }
267
octeon_crash_shutdown(struct pt_regs * regs)268 static void octeon_crash_shutdown(struct pt_regs *regs)
269 {
270 octeon_generic_shutdown();
271 default_machine_crash_shutdown(regs);
272 }
273
274 #ifdef CONFIG_SMP
octeon_crash_smp_send_stop(void)275 void octeon_crash_smp_send_stop(void)
276 {
277 int cpu;
278
279 /* disable watchdogs */
280 for_each_online_cpu(cpu)
281 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
282 }
283 #endif
284
285 #endif /* CONFIG_KEXEC */
286
287 #ifdef CONFIG_KEXEC
288 /* crashkernel cmdline parameter is parsed _after_ memory setup
289 * we also parse it here (workaround for EHB5200) */
290 static uint64_t crashk_size, crashk_base;
291 #endif
292
293 static int octeon_uart;
294
295 extern asmlinkage void handle_int(void);
296
297 /**
298 * octeon_is_simulation - Return non-zero if we are currently running
299 * in the Octeon simulator
300 *
301 * Return: non-0 if running in the Octeon simulator, 0 otherwise
302 */
octeon_is_simulation(void)303 int octeon_is_simulation(void)
304 {
305 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
306 }
307 EXPORT_SYMBOL(octeon_is_simulation);
308
309 /**
310 * octeon_is_pci_host - Return true if Octeon is in PCI Host mode. This means
311 * Linux can control the PCI bus.
312 *
313 * Return: Non-zero if Octeon is in host mode.
314 */
octeon_is_pci_host(void)315 int octeon_is_pci_host(void)
316 {
317 #ifdef CONFIG_PCI
318 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
319 #else
320 return 0;
321 #endif
322 }
323
324 /**
325 * octeon_get_clock_rate - Get the clock rate of Octeon
326 *
327 * Return: Clock rate in HZ
328 */
octeon_get_clock_rate(void)329 uint64_t octeon_get_clock_rate(void)
330 {
331 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
332
333 return sysinfo->cpu_clock_hz;
334 }
335 EXPORT_SYMBOL(octeon_get_clock_rate);
336
337 static u64 octeon_io_clock_rate;
338
octeon_get_io_clock_rate(void)339 u64 octeon_get_io_clock_rate(void)
340 {
341 return octeon_io_clock_rate;
342 }
343 EXPORT_SYMBOL(octeon_get_io_clock_rate);
344
345
346 /**
347 * octeon_write_lcd - Write to the LCD display connected to the bootbus.
348 * @s: String to write
349 *
350 * This display exists on most Cavium evaluation boards. If it doesn't exist,
351 * then this function doesn't do anything.
352 */
octeon_write_lcd(const char * s)353 static void octeon_write_lcd(const char *s)
354 {
355 if (octeon_bootinfo->led_display_base_addr) {
356 void __iomem *lcd_address =
357 ioremap(octeon_bootinfo->led_display_base_addr,
358 8);
359 int i;
360 for (i = 0; i < 8; i++, s++) {
361 if (*s)
362 iowrite8(*s, lcd_address + i);
363 else
364 iowrite8(' ', lcd_address + i);
365 }
366 iounmap(lcd_address);
367 }
368 }
369
370 /**
371 * octeon_get_boot_uart - Return the console uart passed by the bootloader
372 *
373 * Return: uart number (0 or 1)
374 */
octeon_get_boot_uart(void)375 static int octeon_get_boot_uart(void)
376 {
377 return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
378 1 : 0;
379 }
380
381 /**
382 * octeon_get_boot_coremask - Get the coremask Linux was booted on.
383 *
384 * Return: Core mask
385 */
octeon_get_boot_coremask(void)386 int octeon_get_boot_coremask(void)
387 {
388 return octeon_boot_desc_ptr->core_mask;
389 }
390
391 /**
392 * octeon_check_cpu_bist - Check the hardware BIST results for a CPU
393 */
octeon_check_cpu_bist(void)394 void octeon_check_cpu_bist(void)
395 {
396 const int coreid = cvmx_get_core_num();
397 unsigned long long mask;
398 unsigned long long bist_val;
399
400 /* Check BIST results for COP0 registers */
401 mask = 0x1f00000000ull;
402 bist_val = read_octeon_c0_icacheerr();
403 if (bist_val & mask)
404 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
405 coreid, bist_val);
406
407 bist_val = read_octeon_c0_dcacheerr();
408 if (bist_val & 1)
409 pr_err("Core%d L1 Dcache parity error: "
410 "CacheErr(dcache) = 0x%llx\n",
411 coreid, bist_val);
412
413 mask = 0xfc00000000000000ull;
414 bist_val = read_c0_cvmmemctl();
415 if (bist_val & mask)
416 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
417 coreid, bist_val);
418
419 write_octeon_c0_dcacheerr(0);
420 }
421
422 /**
423 * octeon_restart - Reboot Octeon
424 *
425 * @command: Command to pass to the bootloader. Currently ignored.
426 */
octeon_restart(char * command)427 static void octeon_restart(char *command)
428 {
429 /* Disable all watchdogs before soft reset. They don't get cleared */
430 #ifdef CONFIG_SMP
431 int cpu;
432 for_each_online_cpu(cpu)
433 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
434 #else
435 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
436 #endif
437
438 mb();
439 while (1)
440 if (OCTEON_IS_OCTEON3())
441 cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
442 else
443 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
444 }
445
446
447 /**
448 * octeon_kill_core - Permanently stop a core.
449 *
450 * @arg: Ignored.
451 */
octeon_kill_core(void * arg)452 static void octeon_kill_core(void *arg)
453 {
454 if (octeon_is_simulation())
455 /* A break instruction causes the simulator stop a core */
456 asm volatile ("break" ::: "memory");
457
458 local_irq_disable();
459 /* Disable watchdog on this core. */
460 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
461 /* Spin in a low power mode. */
462 while (true)
463 asm volatile ("wait" ::: "memory");
464 }
465
466
467 /**
468 * octeon_halt - Halt the system
469 */
octeon_halt(void)470 static void octeon_halt(void)
471 {
472 smp_call_function(octeon_kill_core, NULL, 0);
473
474 switch (octeon_bootinfo->board_type) {
475 case CVMX_BOARD_TYPE_NAO38:
476 /* Driving a 1 to GPIO 12 shuts off this board */
477 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
478 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
479 break;
480 default:
481 octeon_write_lcd("PowerOff");
482 break;
483 }
484
485 octeon_kill_core(NULL);
486 }
487
488 static char __read_mostly octeon_system_type[80];
489
init_octeon_system_type(void)490 static void __init init_octeon_system_type(void)
491 {
492 char const *board_type;
493
494 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type);
495 if (board_type == NULL) {
496 struct device_node *root;
497 int ret;
498
499 root = of_find_node_by_path("/");
500 ret = of_property_read_string(root, "model", &board_type);
501 of_node_put(root);
502 if (ret)
503 board_type = "Unsupported Board";
504 }
505
506 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
507 board_type, octeon_model_get_string(read_c0_prid()));
508 }
509
510 /**
511 * octeon_board_type_string - Return a string representing the system type
512 *
513 * Return: system type string
514 */
octeon_board_type_string(void)515 const char *octeon_board_type_string(void)
516 {
517 return octeon_system_type;
518 }
519
520 const char *get_system_type(void)
521 __attribute__ ((alias("octeon_board_type_string")));
522
octeon_user_io_init(void)523 void octeon_user_io_init(void)
524 {
525 union octeon_cvmemctl cvmmemctl;
526
527 /* Get the current settings for CP0_CVMMEMCTL_REG */
528 cvmmemctl.u64 = read_c0_cvmmemctl();
529 /* R/W If set, marked write-buffer entries time out the same
530 * as as other entries; if clear, marked write-buffer entries
531 * use the maximum timeout. */
532 cvmmemctl.s.dismarkwblongto = 1;
533 /* R/W If set, a merged store does not clear the write-buffer
534 * entry timeout state. */
535 cvmmemctl.s.dismrgclrwbto = 0;
536 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
537 * word location for an IOBDMA. The other 8 bits come from the
538 * SCRADDR field of the IOBDMA. */
539 cvmmemctl.s.iobdmascrmsb = 0;
540 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
541 * clear, SYNCWS and SYNCS only order unmarked
542 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
543 * set. */
544 cvmmemctl.s.syncwsmarked = 0;
545 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
546 cvmmemctl.s.dissyncws = 0;
547 /* R/W If set, no stall happens on write buffer full. */
548 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
549 cvmmemctl.s.diswbfst = 1;
550 else
551 cvmmemctl.s.diswbfst = 0;
552 /* R/W If set (and SX set), supervisor-level loads/stores can
553 * use XKPHYS addresses with <48>==0 */
554 cvmmemctl.s.xkmemenas = 0;
555
556 /* R/W If set (and UX set), user-level loads/stores can use
557 * XKPHYS addresses with VA<48>==0 */
558 cvmmemctl.s.xkmemenau = 0;
559
560 /* R/W If set (and SX set), supervisor-level loads/stores can
561 * use XKPHYS addresses with VA<48>==1 */
562 cvmmemctl.s.xkioenas = 0;
563
564 /* R/W If set (and UX set), user-level loads/stores can use
565 * XKPHYS addresses with VA<48>==1 */
566 cvmmemctl.s.xkioenau = 0;
567
568 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
569 * when this is set) RW, reset to 0. */
570 cvmmemctl.s.allsyncw = 0;
571
572 /* R/W If set, no stores merge, and all stores reach the
573 * coherent bus in order. */
574 cvmmemctl.s.nomerge = 0;
575 /* R/W Selects the bit in the counter used for DID time-outs 0
576 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
577 * between 1x and 2x this interval. For example, with
578 * DIDTTO=3, expiration interval is between 16K and 32K. */
579 cvmmemctl.s.didtto = 0;
580 /* R/W If set, the (mem) CSR clock never turns off. */
581 cvmmemctl.s.csrckalwys = 0;
582 /* R/W If set, mclk never turns off. */
583 cvmmemctl.s.mclkalwys = 0;
584 /* R/W Selects the bit in the counter used for write buffer
585 * flush time-outs (WBFLT+11) is the bit position in an
586 * internal counter used to determine expiration. The write
587 * buffer expires between 1x and 2x this interval. For
588 * example, with WBFLT = 0, a write buffer expires between 2K
589 * and 4K cycles after the write buffer entry is allocated. */
590 cvmmemctl.s.wbfltime = 0;
591 /* R/W If set, do not put Istream in the L2 cache. */
592 cvmmemctl.s.istrnol2 = 0;
593
594 /*
595 * R/W The write buffer threshold. As per erratum Core-14752
596 * for CN63XX, a sc/scd might fail if the write buffer is
597 * full. Lowering WBTHRESH greatly lowers the chances of the
598 * write buffer ever being full and triggering the erratum.
599 */
600 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
601 cvmmemctl.s.wbthresh = 4;
602 else
603 cvmmemctl.s.wbthresh = 10;
604
605 /* R/W If set, CVMSEG is available for loads/stores in
606 * kernel/debug mode. */
607 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
608 cvmmemctl.s.cvmsegenak = 1;
609 #else
610 cvmmemctl.s.cvmsegenak = 0;
611 #endif
612 /* R/W If set, CVMSEG is available for loads/stores in
613 * supervisor mode. */
614 cvmmemctl.s.cvmsegenas = 0;
615 /* R/W If set, CVMSEG is available for loads/stores in user
616 * mode. */
617 cvmmemctl.s.cvmsegenau = 0;
618
619 write_c0_cvmmemctl(cvmmemctl.u64);
620
621 /* Setup of CVMSEG is done in kernel-entry-init.h */
622 if (smp_processor_id() == 0)
623 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
624 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
625 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
626
627 if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
628 union cvmx_iob_fau_timeout fau_timeout;
629
630 /* Set a default for the hardware timeouts */
631 fau_timeout.u64 = 0;
632 fau_timeout.s.tout_val = 0xfff;
633 /* Disable tagwait FAU timeout */
634 fau_timeout.s.tout_enb = 0;
635 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
636 }
637
638 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
639 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) ||
640 OCTEON_IS_MODEL(OCTEON_CN70XX)) {
641 union cvmx_pow_nw_tim nm_tim;
642
643 nm_tim.u64 = 0;
644 /* 4096 cycles */
645 nm_tim.s.nw_tim = 3;
646 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
647 }
648
649 write_octeon_c0_icacheerr(0);
650 write_c0_derraddr1(0);
651 }
652
653 /**
654 * prom_init - Early entry point for arch setup
655 */
prom_init(void)656 void __init prom_init(void)
657 {
658 struct cvmx_sysinfo *sysinfo;
659 const char *arg;
660 char *p;
661 int i;
662 u64 t;
663 int argc;
664
665 /*
666 * The bootloader passes a pointer to the boot descriptor in
667 * $a3, this is available as fw_arg3.
668 */
669 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
670 octeon_bootinfo =
671 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
672 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
673
674 sysinfo = cvmx_sysinfo_get();
675 memset(sysinfo, 0, sizeof(*sysinfo));
676 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
677 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr);
678
679 if ((octeon_bootinfo->major_version > 1) ||
680 (octeon_bootinfo->major_version == 1 &&
681 octeon_bootinfo->minor_version >= 4))
682 cvmx_coremask_copy(&sysinfo->core_mask,
683 &octeon_bootinfo->ext_core_mask);
684 else
685 cvmx_coremask_set64(&sysinfo->core_mask,
686 octeon_bootinfo->core_mask);
687
688 /* Some broken u-boot pass garbage in upper bits, clear them out */
689 if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
690 for (i = 512; i < 1024; i++)
691 cvmx_coremask_clear_core(&sysinfo->core_mask, i);
692
693 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
694 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
695 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
696 sysinfo->board_type = octeon_bootinfo->board_type;
697 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
698 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
699 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
700 sizeof(sysinfo->mac_addr_base));
701 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
702 memcpy(sysinfo->board_serial_number,
703 octeon_bootinfo->board_serial_number,
704 sizeof(sysinfo->board_serial_number));
705 sysinfo->compact_flash_common_base_addr =
706 octeon_bootinfo->compact_flash_common_base_addr;
707 sysinfo->compact_flash_attribute_base_addr =
708 octeon_bootinfo->compact_flash_attribute_base_addr;
709 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
710 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
711 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
712
713 if (OCTEON_IS_OCTEON2()) {
714 /* I/O clock runs at a different rate than the CPU. */
715 union cvmx_mio_rst_boot rst_boot;
716 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
717 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
718 } else if (OCTEON_IS_OCTEON3()) {
719 /* I/O clock runs at a different rate than the CPU. */
720 union cvmx_rst_boot rst_boot;
721 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
722 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
723 } else {
724 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
725 }
726
727 t = read_c0_cvmctl();
728 if ((t & (1ull << 27)) == 0) {
729 /*
730 * Setup the multiplier save/restore code if
731 * CvmCtl[NOMUL] clear.
732 */
733 void *save;
734 void *save_end;
735 void *restore;
736 void *restore_end;
737 int save_len;
738 int restore_len;
739 int save_max = (char *)octeon_mult_save_end -
740 (char *)octeon_mult_save;
741 int restore_max = (char *)octeon_mult_restore_end -
742 (char *)octeon_mult_restore;
743 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
744 save = octeon_mult_save3;
745 save_end = octeon_mult_save3_end;
746 restore = octeon_mult_restore3;
747 restore_end = octeon_mult_restore3_end;
748 } else {
749 save = octeon_mult_save2;
750 save_end = octeon_mult_save2_end;
751 restore = octeon_mult_restore2;
752 restore_end = octeon_mult_restore2_end;
753 }
754 save_len = (char *)save_end - (char *)save;
755 restore_len = (char *)restore_end - (char *)restore;
756 if (!WARN_ON(save_len > save_max ||
757 restore_len > restore_max)) {
758 memcpy(octeon_mult_save, save, save_len);
759 memcpy(octeon_mult_restore, restore, restore_len);
760 }
761 }
762
763 /*
764 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
765 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
766 */
767 if (!octeon_is_simulation() &&
768 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
769 cvmx_write_csr(CVMX_LED_EN, 0);
770 cvmx_write_csr(CVMX_LED_PRT, 0);
771 cvmx_write_csr(CVMX_LED_DBG, 0);
772 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
773 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
774 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
775 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
776 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
777 cvmx_write_csr(CVMX_LED_EN, 1);
778 }
779
780 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
781 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
782 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
783 } else {
784 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
785 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
786 /* TLB refill */
787 cvmx_l2c_lock_mem_region(ebase, 0x100);
788 #endif
789 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
790 /* General exception */
791 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
792 #endif
793 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
794 /* Interrupt handler */
795 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
796 #endif
797 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
798 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
799 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
800 #endif
801 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
802 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
803 #endif
804 }
805 #endif
806
807 octeon_check_cpu_bist();
808
809 octeon_uart = octeon_get_boot_uart();
810
811 #ifdef CONFIG_SMP
812 octeon_write_lcd("LinuxSMP");
813 #else
814 octeon_write_lcd("Linux");
815 #endif
816
817 octeon_setup_delays();
818
819 /*
820 * BIST should always be enabled when doing a soft reset. L2
821 * Cache locking for instance is not cleared unless BIST is
822 * enabled. Unfortunately due to a chip errata G-200 for
823 * Cn38XX and CN31XX, BIST must be disabled on these parts.
824 */
825 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
826 OCTEON_IS_MODEL(OCTEON_CN31XX))
827 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
828 else
829 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
830
831 /* Default to 64MB in the simulator to speed things up */
832 if (octeon_is_simulation())
833 max_memory = 64ull << 20;
834
835 arg = strstr(arcs_cmdline, "mem=");
836 if (arg) {
837 max_memory = memparse(arg + 4, &p);
838 if (max_memory == 0)
839 max_memory = 32ull << 30;
840 if (*p == '@')
841 reserve_low_mem = memparse(p + 1, &p);
842 }
843
844 arcs_cmdline[0] = 0;
845 argc = octeon_boot_desc_ptr->argc;
846 for (i = 0; i < argc; i++) {
847 const char *arg =
848 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
849 if ((strncmp(arg, "MEM=", 4) == 0) ||
850 (strncmp(arg, "mem=", 4) == 0)) {
851 max_memory = memparse(arg + 4, &p);
852 if (max_memory == 0)
853 max_memory = 32ull << 30;
854 if (*p == '@')
855 reserve_low_mem = memparse(p + 1, &p);
856 #ifdef CONFIG_KEXEC
857 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
858 crashk_size = memparse(arg+12, &p);
859 if (*p == '@')
860 crashk_base = memparse(p+1, &p);
861 strcat(arcs_cmdline, " ");
862 strcat(arcs_cmdline, arg);
863 /*
864 * To do: switch parsing to new style, something like:
865 * parse_crashkernel(arg, sysinfo->system_dram_size,
866 * &crashk_size, &crashk_base);
867 */
868 #endif
869 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
870 sizeof(arcs_cmdline) - 1) {
871 strcat(arcs_cmdline, " ");
872 strcat(arcs_cmdline, arg);
873 }
874 }
875
876 if (strstr(arcs_cmdline, "console=") == NULL) {
877 if (octeon_uart == 1)
878 strcat(arcs_cmdline, " console=ttyS1,115200");
879 else
880 strcat(arcs_cmdline, " console=ttyS0,115200");
881 }
882
883 mips_hpt_frequency = octeon_get_clock_rate();
884
885 octeon_init_cvmcount();
886
887 _machine_restart = octeon_restart;
888 _machine_halt = octeon_halt;
889
890 #ifdef CONFIG_KEXEC
891 _machine_kexec_shutdown = octeon_shutdown;
892 _machine_crash_shutdown = octeon_crash_shutdown;
893 _machine_kexec_prepare = octeon_kexec_prepare;
894 #ifdef CONFIG_SMP
895 _crash_smp_send_stop = octeon_crash_smp_send_stop;
896 #endif
897 #endif
898
899 octeon_user_io_init();
900 octeon_setup_smp();
901 }
902
903 /* Exclude a single page from the regions obtained in plat_mem_setup. */
904 #ifndef CONFIG_CRASH_DUMP
memory_exclude_page(u64 addr,u64 * mem,u64 * size)905 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
906 {
907 if (addr > *mem && addr < *mem + *size) {
908 u64 inc = addr - *mem;
909 memblock_add(*mem, inc);
910 *mem += inc;
911 *size -= inc;
912 }
913
914 if (addr == *mem && *size > PAGE_SIZE) {
915 *mem += PAGE_SIZE;
916 *size -= PAGE_SIZE;
917 }
918 }
919 #endif /* CONFIG_CRASH_DUMP */
920
fw_init_cmdline(void)921 void __init fw_init_cmdline(void)
922 {
923 int i;
924
925 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
926 for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
927 const char *arg =
928 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
929 if (strlen(arcs_cmdline) + strlen(arg) + 1 <
930 sizeof(arcs_cmdline) - 1) {
931 strcat(arcs_cmdline, " ");
932 strcat(arcs_cmdline, arg);
933 }
934 }
935 }
936
plat_get_fdt(void)937 void __init *plat_get_fdt(void)
938 {
939 octeon_bootinfo =
940 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
941 return phys_to_virt(octeon_bootinfo->fdt_addr);
942 }
943
plat_mem_setup(void)944 void __init plat_mem_setup(void)
945 {
946 uint64_t mem_alloc_size;
947 uint64_t total;
948 uint64_t crashk_end;
949 #ifndef CONFIG_CRASH_DUMP
950 int64_t memory;
951 #endif
952
953 total = 0;
954 crashk_end = 0;
955
956 /*
957 * The Mips memory init uses the first memory location for
958 * some memory vectors. When SPARSEMEM is in use, it doesn't
959 * verify that the size is big enough for the final
960 * vectors. Making the smallest chuck 4MB seems to be enough
961 * to consistently work.
962 */
963 mem_alloc_size = 4 << 20;
964 if (mem_alloc_size > max_memory)
965 mem_alloc_size = max_memory;
966
967 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
968 #ifdef CONFIG_CRASH_DUMP
969 memblock_add(reserve_low_mem, max_memory);
970 total += max_memory;
971 #else
972 #ifdef CONFIG_KEXEC
973 if (crashk_size > 0) {
974 memblock_add(crashk_base, crashk_size);
975 crashk_end = crashk_base + crashk_size;
976 }
977 #endif
978 /*
979 * When allocating memory, we want incrementing addresses,
980 * which is handled by memblock
981 */
982 cvmx_bootmem_lock();
983 while (total < max_memory) {
984 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
985 __pa_symbol(&_end), -1,
986 0x100000,
987 CVMX_BOOTMEM_FLAG_NO_LOCKING);
988 if (memory >= 0) {
989 u64 size = mem_alloc_size;
990 #ifdef CONFIG_KEXEC
991 uint64_t end;
992 #endif
993
994 /*
995 * exclude a page at the beginning and end of
996 * the 256MB PCIe 'hole' so the kernel will not
997 * try to allocate multi-page buffers that
998 * span the discontinuity.
999 */
1000 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
1001 &memory, &size);
1002 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
1003 CVMX_PCIE_BAR1_PHYS_SIZE,
1004 &memory, &size);
1005 #ifdef CONFIG_KEXEC
1006 end = memory + mem_alloc_size;
1007
1008 /*
1009 * This function automatically merges address regions
1010 * next to each other if they are received in
1011 * incrementing order
1012 */
1013 if (memory < crashk_base && end > crashk_end) {
1014 /* region is fully in */
1015 memblock_add(memory, crashk_base - memory);
1016 total += crashk_base - memory;
1017 memblock_add(crashk_end, end - crashk_end);
1018 total += end - crashk_end;
1019 continue;
1020 }
1021
1022 if (memory >= crashk_base && end <= crashk_end)
1023 /*
1024 * Entire memory region is within the new
1025 * kernel's memory, ignore it.
1026 */
1027 continue;
1028
1029 if (memory > crashk_base && memory < crashk_end &&
1030 end > crashk_end) {
1031 /*
1032 * Overlap with the beginning of the region,
1033 * reserve the beginning.
1034 */
1035 mem_alloc_size -= crashk_end - memory;
1036 memory = crashk_end;
1037 } else if (memory < crashk_base && end > crashk_base &&
1038 end < crashk_end)
1039 /*
1040 * Overlap with the beginning of the region,
1041 * chop of end.
1042 */
1043 mem_alloc_size -= end - crashk_base;
1044 #endif
1045 memblock_add(memory, mem_alloc_size);
1046 total += mem_alloc_size;
1047 /* Recovering mem_alloc_size */
1048 mem_alloc_size = 4 << 20;
1049 } else {
1050 break;
1051 }
1052 }
1053 cvmx_bootmem_unlock();
1054 #endif /* CONFIG_CRASH_DUMP */
1055
1056 if (total == 0)
1057 panic("Unable to allocate memory from "
1058 "cvmx_bootmem_phy_alloc");
1059 }
1060
1061 /*
1062 * Emit one character to the boot UART. Exported for use by the
1063 * watchdog timer.
1064 */
prom_putchar(char c)1065 void prom_putchar(char c)
1066 {
1067 uint64_t lsrval;
1068
1069 /* Spin until there is room */
1070 do {
1071 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1072 } while ((lsrval & 0x20) == 0);
1073
1074 /* Write the byte */
1075 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1076 }
1077 EXPORT_SYMBOL(prom_putchar);
1078
prom_free_prom_memory(void)1079 void __init prom_free_prom_memory(void)
1080 {
1081 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
1082 /* Check for presence of Core-14449 fix. */
1083 u32 insn;
1084 u32 *foo;
1085
1086 foo = &insn;
1087
1088 asm volatile("# before" : : : "memory");
1089 prefetch(foo);
1090 asm volatile(
1091 ".set push\n\t"
1092 ".set noreorder\n\t"
1093 "bal 1f\n\t"
1094 "nop\n"
1095 "1:\tlw %0,-12($31)\n\t"
1096 ".set pop\n\t"
1097 : "=r" (insn) : : "$31", "memory");
1098
1099 if ((insn >> 26) != 0x33)
1100 panic("No PREF instruction at Core-14449 probe point.");
1101
1102 if (((insn >> 16) & 0x1f) != 28)
1103 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1104 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1105 insn);
1106 }
1107 }
1108
1109 void __init octeon_fill_mac_addresses(void);
1110
device_tree_init(void)1111 void __init device_tree_init(void)
1112 {
1113 const void *fdt;
1114 bool do_prune;
1115 bool fill_mac;
1116
1117 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
1118 if (!fdt_check_header(&__appended_dtb)) {
1119 fdt = &__appended_dtb;
1120 do_prune = false;
1121 fill_mac = true;
1122 pr_info("Using appended Device Tree.\n");
1123 } else
1124 #endif
1125 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1126 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1127 if (fdt_check_header(fdt))
1128 panic("Corrupt Device Tree passed to kernel.");
1129 do_prune = false;
1130 fill_mac = false;
1131 pr_info("Using passed Device Tree.\n");
1132 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1133 fdt = &__dtb_octeon_68xx_begin;
1134 do_prune = true;
1135 fill_mac = true;
1136 } else {
1137 fdt = &__dtb_octeon_3xxx_begin;
1138 do_prune = true;
1139 fill_mac = true;
1140 }
1141
1142 initial_boot_params = (void *)fdt;
1143
1144 if (do_prune) {
1145 octeon_prune_device_tree();
1146 pr_info("Using internal Device Tree.\n");
1147 }
1148 if (fill_mac)
1149 octeon_fill_mac_addresses();
1150 unflatten_and_copy_device_tree();
1151 init_octeon_system_type();
1152 }
1153
1154 static int __initdata disable_octeon_edac_p;
1155
disable_octeon_edac(char * str)1156 static int __init disable_octeon_edac(char *str)
1157 {
1158 disable_octeon_edac_p = 1;
1159 return 0;
1160 }
1161 early_param("disable_octeon_edac", disable_octeon_edac);
1162
1163 static char *edac_device_names[] = {
1164 "octeon_l2c_edac",
1165 "octeon_pc_edac",
1166 };
1167
edac_devinit(void)1168 static int __init edac_devinit(void)
1169 {
1170 struct platform_device *dev;
1171 int i, err = 0;
1172 int num_lmc;
1173 char *name;
1174
1175 if (disable_octeon_edac_p)
1176 return 0;
1177
1178 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1179 name = edac_device_names[i];
1180 dev = platform_device_register_simple(name, -1, NULL, 0);
1181 if (IS_ERR(dev)) {
1182 pr_err("Registration of %s failed!\n", name);
1183 err = PTR_ERR(dev);
1184 }
1185 }
1186
1187 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1188 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1189 for (i = 0; i < num_lmc; i++) {
1190 dev = platform_device_register_simple("octeon_lmc_edac",
1191 i, NULL, 0);
1192 if (IS_ERR(dev)) {
1193 pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
1194 err = PTR_ERR(dev);
1195 }
1196 }
1197
1198 return err;
1199 }
1200 device_initcall(edac_devinit);
1201
1202 static void __initdata *octeon_dummy_iospace;
1203
octeon_no_pci_init(void)1204 static int __init octeon_no_pci_init(void)
1205 {
1206 /*
1207 * Initially assume there is no PCI. The PCI/PCIe platform code will
1208 * later re-initialize these to correct values if they are present.
1209 */
1210 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1211 set_io_port_base((unsigned long)octeon_dummy_iospace);
1212 ioport_resource.start = MAX_RESOURCE;
1213 ioport_resource.end = 0;
1214 return 0;
1215 }
1216 core_initcall(octeon_no_pci_init);
1217
octeon_no_pci_release(void)1218 static int __init octeon_no_pci_release(void)
1219 {
1220 /*
1221 * Release the allocated memory if a real IO space is there.
1222 */
1223 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1224 vfree(octeon_dummy_iospace);
1225 return 0;
1226 }
1227 late_initcall(octeon_no_pci_release);
1228