1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
20 #include <linux/fs.h>
21 #include <linux/memblock.h>
22 #include <linux/pgtable.h>
23
24 #include <asm/fpu.h>
25 #include <asm/page.h>
26 #include <asm/cacheflush.h>
27 #include <asm/mmu_context.h>
28 #include <asm/pgalloc.h>
29
30 #include <linux/kvm_host.h>
31
32 #include "interrupt.h"
33
34 #define CREATE_TRACE_POINTS
35 #include "trace.h"
36
37 #ifndef VECTORSPACING
38 #define VECTORSPACING 0x100 /* for EI/VI mode */
39 #endif
40
41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
42 KVM_GENERIC_VM_STATS()
43 };
44
45 const struct kvm_stats_header kvm_vm_stats_header = {
46 .name_size = KVM_STATS_NAME_SIZE,
47 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
48 .id_offset = sizeof(struct kvm_stats_header),
49 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
50 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
51 sizeof(kvm_vm_stats_desc),
52 };
53
54 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
55 KVM_GENERIC_VCPU_STATS(),
56 STATS_DESC_COUNTER(VCPU, wait_exits),
57 STATS_DESC_COUNTER(VCPU, cache_exits),
58 STATS_DESC_COUNTER(VCPU, signal_exits),
59 STATS_DESC_COUNTER(VCPU, int_exits),
60 STATS_DESC_COUNTER(VCPU, cop_unusable_exits),
61 STATS_DESC_COUNTER(VCPU, tlbmod_exits),
62 STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits),
63 STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits),
64 STATS_DESC_COUNTER(VCPU, addrerr_st_exits),
65 STATS_DESC_COUNTER(VCPU, addrerr_ld_exits),
66 STATS_DESC_COUNTER(VCPU, syscall_exits),
67 STATS_DESC_COUNTER(VCPU, resvd_inst_exits),
68 STATS_DESC_COUNTER(VCPU, break_inst_exits),
69 STATS_DESC_COUNTER(VCPU, trap_inst_exits),
70 STATS_DESC_COUNTER(VCPU, msa_fpe_exits),
71 STATS_DESC_COUNTER(VCPU, fpe_exits),
72 STATS_DESC_COUNTER(VCPU, msa_disabled_exits),
73 STATS_DESC_COUNTER(VCPU, flush_dcache_exits),
74 STATS_DESC_COUNTER(VCPU, vz_gpsi_exits),
75 STATS_DESC_COUNTER(VCPU, vz_gsfc_exits),
76 STATS_DESC_COUNTER(VCPU, vz_hc_exits),
77 STATS_DESC_COUNTER(VCPU, vz_grr_exits),
78 STATS_DESC_COUNTER(VCPU, vz_gva_exits),
79 STATS_DESC_COUNTER(VCPU, vz_ghfc_exits),
80 STATS_DESC_COUNTER(VCPU, vz_gpa_exits),
81 STATS_DESC_COUNTER(VCPU, vz_resvd_exits),
82 #ifdef CONFIG_CPU_LOONGSON64
83 STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits),
84 #endif
85 };
86
87 const struct kvm_stats_header kvm_vcpu_stats_header = {
88 .name_size = KVM_STATS_NAME_SIZE,
89 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
90 .id_offset = sizeof(struct kvm_stats_header),
91 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
92 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
93 sizeof(kvm_vcpu_stats_desc),
94 };
95
96 bool kvm_trace_guest_mode_change;
97
kvm_guest_mode_change_trace_reg(void)98 int kvm_guest_mode_change_trace_reg(void)
99 {
100 kvm_trace_guest_mode_change = true;
101 return 0;
102 }
103
kvm_guest_mode_change_trace_unreg(void)104 void kvm_guest_mode_change_trace_unreg(void)
105 {
106 kvm_trace_guest_mode_change = false;
107 }
108
109 /*
110 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
111 * Config7, so we are "runnable" if interrupts are pending
112 */
kvm_arch_vcpu_runnable(struct kvm_vcpu * vcpu)113 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
114 {
115 return !!(vcpu->arch.pending_exceptions);
116 }
117
kvm_arch_vcpu_in_kernel(struct kvm_vcpu * vcpu)118 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
119 {
120 return false;
121 }
122
kvm_arch_vcpu_should_kick(struct kvm_vcpu * vcpu)123 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
124 {
125 return 1;
126 }
127
kvm_arch_hardware_enable(void)128 int kvm_arch_hardware_enable(void)
129 {
130 return kvm_mips_callbacks->hardware_enable();
131 }
132
kvm_arch_hardware_disable(void)133 void kvm_arch_hardware_disable(void)
134 {
135 kvm_mips_callbacks->hardware_disable();
136 }
137
kvm_arch_hardware_setup(void * opaque)138 int kvm_arch_hardware_setup(void *opaque)
139 {
140 return 0;
141 }
142
kvm_arch_check_processor_compat(void * opaque)143 int kvm_arch_check_processor_compat(void *opaque)
144 {
145 return 0;
146 }
147
148 extern void kvm_init_loongson_ipi(struct kvm *kvm);
149
kvm_arch_init_vm(struct kvm * kvm,unsigned long type)150 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
151 {
152 switch (type) {
153 case KVM_VM_MIPS_AUTO:
154 break;
155 case KVM_VM_MIPS_VZ:
156 break;
157 default:
158 /* Unsupported KVM type */
159 return -EINVAL;
160 }
161
162 /* Allocate page table to map GPA -> RPA */
163 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
164 if (!kvm->arch.gpa_mm.pgd)
165 return -ENOMEM;
166
167 #ifdef CONFIG_CPU_LOONGSON64
168 kvm_init_loongson_ipi(kvm);
169 #endif
170
171 return 0;
172 }
173
kvm_mips_free_gpa_pt(struct kvm * kvm)174 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
175 {
176 /* It should always be safe to remove after flushing the whole range */
177 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
178 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
179 }
180
kvm_arch_destroy_vm(struct kvm * kvm)181 void kvm_arch_destroy_vm(struct kvm *kvm)
182 {
183 kvm_destroy_vcpus(kvm);
184 kvm_mips_free_gpa_pt(kvm);
185 }
186
kvm_arch_dev_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
188 unsigned long arg)
189 {
190 return -ENOIOCTLCMD;
191 }
192
kvm_arch_flush_shadow_all(struct kvm * kvm)193 void kvm_arch_flush_shadow_all(struct kvm *kvm)
194 {
195 /* Flush whole GPA */
196 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
197 kvm_flush_remote_tlbs(kvm);
198 }
199
kvm_arch_flush_shadow_memslot(struct kvm * kvm,struct kvm_memory_slot * slot)200 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
201 struct kvm_memory_slot *slot)
202 {
203 /*
204 * The slot has been made invalid (ready for moving or deletion), so we
205 * need to ensure that it can no longer be accessed by any guest VCPUs.
206 */
207
208 spin_lock(&kvm->mmu_lock);
209 /* Flush slot from GPA */
210 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
211 slot->base_gfn + slot->npages - 1);
212 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
213 spin_unlock(&kvm->mmu_lock);
214 }
215
kvm_arch_prepare_memory_region(struct kvm * kvm,struct kvm_memory_slot * memslot,const struct kvm_userspace_memory_region * mem,enum kvm_mr_change change)216 int kvm_arch_prepare_memory_region(struct kvm *kvm,
217 struct kvm_memory_slot *memslot,
218 const struct kvm_userspace_memory_region *mem,
219 enum kvm_mr_change change)
220 {
221 return 0;
222 }
223
kvm_arch_commit_memory_region(struct kvm * kvm,const struct kvm_userspace_memory_region * mem,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)224 void kvm_arch_commit_memory_region(struct kvm *kvm,
225 const struct kvm_userspace_memory_region *mem,
226 struct kvm_memory_slot *old,
227 const struct kvm_memory_slot *new,
228 enum kvm_mr_change change)
229 {
230 int needs_flush;
231
232 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
233 __func__, kvm, mem->slot, mem->guest_phys_addr,
234 mem->memory_size, mem->userspace_addr);
235
236 /*
237 * If dirty page logging is enabled, write protect all pages in the slot
238 * ready for dirty logging.
239 *
240 * There is no need to do this in any of the following cases:
241 * CREATE: No dirty mappings will already exist.
242 * MOVE/DELETE: The old mappings will already have been cleaned up by
243 * kvm_arch_flush_shadow_memslot()
244 */
245 if (change == KVM_MR_FLAGS_ONLY &&
246 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
247 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
248 spin_lock(&kvm->mmu_lock);
249 /* Write protect GPA page table entries */
250 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
251 new->base_gfn + new->npages - 1);
252 if (needs_flush)
253 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
254 spin_unlock(&kvm->mmu_lock);
255 }
256 }
257
dump_handler(const char * symbol,void * start,void * end)258 static inline void dump_handler(const char *symbol, void *start, void *end)
259 {
260 u32 *p;
261
262 pr_debug("LEAF(%s)\n", symbol);
263
264 pr_debug("\t.set push\n");
265 pr_debug("\t.set noreorder\n");
266
267 for (p = start; p < (u32 *)end; ++p)
268 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
269
270 pr_debug("\t.set\tpop\n");
271
272 pr_debug("\tEND(%s)\n", symbol);
273 }
274
275 /* low level hrtimer wake routine */
kvm_mips_comparecount_wakeup(struct hrtimer * timer)276 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
277 {
278 struct kvm_vcpu *vcpu;
279
280 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
281
282 kvm_mips_callbacks->queue_timer_int(vcpu);
283
284 vcpu->arch.wait = 0;
285 rcuwait_wake_up(&vcpu->wait);
286
287 return kvm_mips_count_timeout(vcpu);
288 }
289
kvm_arch_vcpu_precreate(struct kvm * kvm,unsigned int id)290 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
291 {
292 return 0;
293 }
294
kvm_arch_vcpu_create(struct kvm_vcpu * vcpu)295 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
296 {
297 int err, size;
298 void *gebase, *p, *handler, *refill_start, *refill_end;
299 int i;
300
301 kvm_debug("kvm @ %p: create cpu %d at %p\n",
302 vcpu->kvm, vcpu->vcpu_id, vcpu);
303
304 err = kvm_mips_callbacks->vcpu_init(vcpu);
305 if (err)
306 return err;
307
308 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
309 HRTIMER_MODE_REL);
310 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
311
312 /*
313 * Allocate space for host mode exception handlers that handle
314 * guest mode exits
315 */
316 if (cpu_has_veic || cpu_has_vint)
317 size = 0x200 + VECTORSPACING * 64;
318 else
319 size = 0x4000;
320
321 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
322
323 if (!gebase) {
324 err = -ENOMEM;
325 goto out_uninit_vcpu;
326 }
327 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
328 ALIGN(size, PAGE_SIZE), gebase);
329
330 /*
331 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
332 * limits us to the low 512MB of physical address space. If the memory
333 * we allocate is out of range, just give up now.
334 */
335 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
336 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
337 gebase);
338 err = -ENOMEM;
339 goto out_free_gebase;
340 }
341
342 /* Save new ebase */
343 vcpu->arch.guest_ebase = gebase;
344
345 /* Build guest exception vectors dynamically in unmapped memory */
346 handler = gebase + 0x2000;
347
348 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
349 refill_start = gebase;
350 if (IS_ENABLED(CONFIG_64BIT))
351 refill_start += 0x080;
352 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
353
354 /* General Exception Entry point */
355 kvm_mips_build_exception(gebase + 0x180, handler);
356
357 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
358 for (i = 0; i < 8; i++) {
359 kvm_debug("L1 Vectored handler @ %p\n",
360 gebase + 0x200 + (i * VECTORSPACING));
361 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
362 handler);
363 }
364
365 /* General exit handler */
366 p = handler;
367 p = kvm_mips_build_exit(p);
368
369 /* Guest entry routine */
370 vcpu->arch.vcpu_run = p;
371 p = kvm_mips_build_vcpu_run(p);
372
373 /* Dump the generated code */
374 pr_debug("#include <asm/asm.h>\n");
375 pr_debug("#include <asm/regdef.h>\n");
376 pr_debug("\n");
377 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
378 dump_handler("kvm_tlb_refill", refill_start, refill_end);
379 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
380 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
381
382 /* Invalidate the icache for these ranges */
383 flush_icache_range((unsigned long)gebase,
384 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
385
386 /* Init */
387 vcpu->arch.last_sched_cpu = -1;
388 vcpu->arch.last_exec_cpu = -1;
389
390 /* Initial guest state */
391 err = kvm_mips_callbacks->vcpu_setup(vcpu);
392 if (err)
393 goto out_free_gebase;
394
395 return 0;
396
397 out_free_gebase:
398 kfree(gebase);
399 out_uninit_vcpu:
400 kvm_mips_callbacks->vcpu_uninit(vcpu);
401 return err;
402 }
403
kvm_arch_vcpu_destroy(struct kvm_vcpu * vcpu)404 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
405 {
406 hrtimer_cancel(&vcpu->arch.comparecount_timer);
407
408 kvm_mips_dump_stats(vcpu);
409
410 kvm_mmu_free_memory_caches(vcpu);
411 kfree(vcpu->arch.guest_ebase);
412
413 kvm_mips_callbacks->vcpu_uninit(vcpu);
414 }
415
kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu * vcpu,struct kvm_guest_debug * dbg)416 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
417 struct kvm_guest_debug *dbg)
418 {
419 return -ENOIOCTLCMD;
420 }
421
kvm_arch_vcpu_ioctl_run(struct kvm_vcpu * vcpu)422 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
423 {
424 int r = -EINTR;
425
426 vcpu_load(vcpu);
427
428 kvm_sigset_activate(vcpu);
429
430 if (vcpu->mmio_needed) {
431 if (!vcpu->mmio_is_write)
432 kvm_mips_complete_mmio_load(vcpu);
433 vcpu->mmio_needed = 0;
434 }
435
436 if (vcpu->run->immediate_exit)
437 goto out;
438
439 lose_fpu(1);
440
441 local_irq_disable();
442 guest_enter_irqoff();
443 trace_kvm_enter(vcpu);
444
445 /*
446 * Make sure the read of VCPU requests in vcpu_run() callback is not
447 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
448 * flush request while the requester sees the VCPU as outside of guest
449 * mode and not needing an IPI.
450 */
451 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
452
453 r = kvm_mips_callbacks->vcpu_run(vcpu);
454
455 trace_kvm_out(vcpu);
456 guest_exit_irqoff();
457 local_irq_enable();
458
459 out:
460 kvm_sigset_deactivate(vcpu);
461
462 vcpu_put(vcpu);
463 return r;
464 }
465
kvm_vcpu_ioctl_interrupt(struct kvm_vcpu * vcpu,struct kvm_mips_interrupt * irq)466 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
467 struct kvm_mips_interrupt *irq)
468 {
469 int intr = (int)irq->irq;
470 struct kvm_vcpu *dvcpu = NULL;
471
472 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
473 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
474 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
475 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
476 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
477 (int)intr);
478
479 if (irq->cpu == -1)
480 dvcpu = vcpu;
481 else
482 dvcpu = kvm_get_vcpu(vcpu->kvm, irq->cpu);
483
484 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
485 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
486
487 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
488 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
489 } else {
490 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
491 irq->cpu, irq->irq);
492 return -EINVAL;
493 }
494
495 dvcpu->arch.wait = 0;
496
497 rcuwait_wake_up(&dvcpu->wait);
498
499 return 0;
500 }
501
kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)502 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
503 struct kvm_mp_state *mp_state)
504 {
505 return -ENOIOCTLCMD;
506 }
507
kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)508 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
509 struct kvm_mp_state *mp_state)
510 {
511 return -ENOIOCTLCMD;
512 }
513
514 static u64 kvm_mips_get_one_regs[] = {
515 KVM_REG_MIPS_R0,
516 KVM_REG_MIPS_R1,
517 KVM_REG_MIPS_R2,
518 KVM_REG_MIPS_R3,
519 KVM_REG_MIPS_R4,
520 KVM_REG_MIPS_R5,
521 KVM_REG_MIPS_R6,
522 KVM_REG_MIPS_R7,
523 KVM_REG_MIPS_R8,
524 KVM_REG_MIPS_R9,
525 KVM_REG_MIPS_R10,
526 KVM_REG_MIPS_R11,
527 KVM_REG_MIPS_R12,
528 KVM_REG_MIPS_R13,
529 KVM_REG_MIPS_R14,
530 KVM_REG_MIPS_R15,
531 KVM_REG_MIPS_R16,
532 KVM_REG_MIPS_R17,
533 KVM_REG_MIPS_R18,
534 KVM_REG_MIPS_R19,
535 KVM_REG_MIPS_R20,
536 KVM_REG_MIPS_R21,
537 KVM_REG_MIPS_R22,
538 KVM_REG_MIPS_R23,
539 KVM_REG_MIPS_R24,
540 KVM_REG_MIPS_R25,
541 KVM_REG_MIPS_R26,
542 KVM_REG_MIPS_R27,
543 KVM_REG_MIPS_R28,
544 KVM_REG_MIPS_R29,
545 KVM_REG_MIPS_R30,
546 KVM_REG_MIPS_R31,
547
548 #ifndef CONFIG_CPU_MIPSR6
549 KVM_REG_MIPS_HI,
550 KVM_REG_MIPS_LO,
551 #endif
552 KVM_REG_MIPS_PC,
553 };
554
555 static u64 kvm_mips_get_one_regs_fpu[] = {
556 KVM_REG_MIPS_FCR_IR,
557 KVM_REG_MIPS_FCR_CSR,
558 };
559
560 static u64 kvm_mips_get_one_regs_msa[] = {
561 KVM_REG_MIPS_MSA_IR,
562 KVM_REG_MIPS_MSA_CSR,
563 };
564
kvm_mips_num_regs(struct kvm_vcpu * vcpu)565 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
566 {
567 unsigned long ret;
568
569 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
570 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
571 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
572 /* odd doubles */
573 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
574 ret += 16;
575 }
576 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
577 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
578 ret += kvm_mips_callbacks->num_regs(vcpu);
579
580 return ret;
581 }
582
kvm_mips_copy_reg_indices(struct kvm_vcpu * vcpu,u64 __user * indices)583 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
584 {
585 u64 index;
586 unsigned int i;
587
588 if (copy_to_user(indices, kvm_mips_get_one_regs,
589 sizeof(kvm_mips_get_one_regs)))
590 return -EFAULT;
591 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
592
593 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
594 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
595 sizeof(kvm_mips_get_one_regs_fpu)))
596 return -EFAULT;
597 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
598
599 for (i = 0; i < 32; ++i) {
600 index = KVM_REG_MIPS_FPR_32(i);
601 if (copy_to_user(indices, &index, sizeof(index)))
602 return -EFAULT;
603 ++indices;
604
605 /* skip odd doubles if no F64 */
606 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
607 continue;
608
609 index = KVM_REG_MIPS_FPR_64(i);
610 if (copy_to_user(indices, &index, sizeof(index)))
611 return -EFAULT;
612 ++indices;
613 }
614 }
615
616 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
617 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
618 sizeof(kvm_mips_get_one_regs_msa)))
619 return -EFAULT;
620 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
621
622 for (i = 0; i < 32; ++i) {
623 index = KVM_REG_MIPS_VEC_128(i);
624 if (copy_to_user(indices, &index, sizeof(index)))
625 return -EFAULT;
626 ++indices;
627 }
628 }
629
630 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
631 }
632
kvm_mips_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)633 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
634 const struct kvm_one_reg *reg)
635 {
636 struct mips_coproc *cop0 = &vcpu->arch.cop0;
637 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
638 int ret;
639 s64 v;
640 s64 vs[2];
641 unsigned int idx;
642
643 switch (reg->id) {
644 /* General purpose registers */
645 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
646 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
647 break;
648 #ifndef CONFIG_CPU_MIPSR6
649 case KVM_REG_MIPS_HI:
650 v = (long)vcpu->arch.hi;
651 break;
652 case KVM_REG_MIPS_LO:
653 v = (long)vcpu->arch.lo;
654 break;
655 #endif
656 case KVM_REG_MIPS_PC:
657 v = (long)vcpu->arch.pc;
658 break;
659
660 /* Floating point registers */
661 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
662 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
663 return -EINVAL;
664 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
665 /* Odd singles in top of even double when FR=0 */
666 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
667 v = get_fpr32(&fpu->fpr[idx], 0);
668 else
669 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
670 break;
671 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
672 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
673 return -EINVAL;
674 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
675 /* Can't access odd doubles in FR=0 mode */
676 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
677 return -EINVAL;
678 v = get_fpr64(&fpu->fpr[idx], 0);
679 break;
680 case KVM_REG_MIPS_FCR_IR:
681 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
682 return -EINVAL;
683 v = boot_cpu_data.fpu_id;
684 break;
685 case KVM_REG_MIPS_FCR_CSR:
686 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
687 return -EINVAL;
688 v = fpu->fcr31;
689 break;
690
691 /* MIPS SIMD Architecture (MSA) registers */
692 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
693 if (!kvm_mips_guest_has_msa(&vcpu->arch))
694 return -EINVAL;
695 /* Can't access MSA registers in FR=0 mode */
696 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
697 return -EINVAL;
698 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
699 #ifdef CONFIG_CPU_LITTLE_ENDIAN
700 /* least significant byte first */
701 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
702 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
703 #else
704 /* most significant byte first */
705 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
706 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
707 #endif
708 break;
709 case KVM_REG_MIPS_MSA_IR:
710 if (!kvm_mips_guest_has_msa(&vcpu->arch))
711 return -EINVAL;
712 v = boot_cpu_data.msa_id;
713 break;
714 case KVM_REG_MIPS_MSA_CSR:
715 if (!kvm_mips_guest_has_msa(&vcpu->arch))
716 return -EINVAL;
717 v = fpu->msacsr;
718 break;
719
720 /* registers to be handled specially */
721 default:
722 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
723 if (ret)
724 return ret;
725 break;
726 }
727 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
728 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
729
730 return put_user(v, uaddr64);
731 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
732 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
733 u32 v32 = (u32)v;
734
735 return put_user(v32, uaddr32);
736 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
737 void __user *uaddr = (void __user *)(long)reg->addr;
738
739 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
740 } else {
741 return -EINVAL;
742 }
743 }
744
kvm_mips_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)745 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
746 const struct kvm_one_reg *reg)
747 {
748 struct mips_coproc *cop0 = &vcpu->arch.cop0;
749 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
750 s64 v;
751 s64 vs[2];
752 unsigned int idx;
753
754 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
755 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
756
757 if (get_user(v, uaddr64) != 0)
758 return -EFAULT;
759 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
760 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
761 s32 v32;
762
763 if (get_user(v32, uaddr32) != 0)
764 return -EFAULT;
765 v = (s64)v32;
766 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
767 void __user *uaddr = (void __user *)(long)reg->addr;
768
769 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
770 } else {
771 return -EINVAL;
772 }
773
774 switch (reg->id) {
775 /* General purpose registers */
776 case KVM_REG_MIPS_R0:
777 /* Silently ignore requests to set $0 */
778 break;
779 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
780 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
781 break;
782 #ifndef CONFIG_CPU_MIPSR6
783 case KVM_REG_MIPS_HI:
784 vcpu->arch.hi = v;
785 break;
786 case KVM_REG_MIPS_LO:
787 vcpu->arch.lo = v;
788 break;
789 #endif
790 case KVM_REG_MIPS_PC:
791 vcpu->arch.pc = v;
792 break;
793
794 /* Floating point registers */
795 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
796 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
797 return -EINVAL;
798 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
799 /* Odd singles in top of even double when FR=0 */
800 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
801 set_fpr32(&fpu->fpr[idx], 0, v);
802 else
803 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
804 break;
805 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
806 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
807 return -EINVAL;
808 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
809 /* Can't access odd doubles in FR=0 mode */
810 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
811 return -EINVAL;
812 set_fpr64(&fpu->fpr[idx], 0, v);
813 break;
814 case KVM_REG_MIPS_FCR_IR:
815 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
816 return -EINVAL;
817 /* Read-only */
818 break;
819 case KVM_REG_MIPS_FCR_CSR:
820 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
821 return -EINVAL;
822 fpu->fcr31 = v;
823 break;
824
825 /* MIPS SIMD Architecture (MSA) registers */
826 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
827 if (!kvm_mips_guest_has_msa(&vcpu->arch))
828 return -EINVAL;
829 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
830 #ifdef CONFIG_CPU_LITTLE_ENDIAN
831 /* least significant byte first */
832 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
833 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
834 #else
835 /* most significant byte first */
836 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
837 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
838 #endif
839 break;
840 case KVM_REG_MIPS_MSA_IR:
841 if (!kvm_mips_guest_has_msa(&vcpu->arch))
842 return -EINVAL;
843 /* Read-only */
844 break;
845 case KVM_REG_MIPS_MSA_CSR:
846 if (!kvm_mips_guest_has_msa(&vcpu->arch))
847 return -EINVAL;
848 fpu->msacsr = v;
849 break;
850
851 /* registers to be handled specially */
852 default:
853 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
854 }
855 return 0;
856 }
857
kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu * vcpu,struct kvm_enable_cap * cap)858 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
859 struct kvm_enable_cap *cap)
860 {
861 int r = 0;
862
863 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
864 return -EINVAL;
865 if (cap->flags)
866 return -EINVAL;
867 if (cap->args[0])
868 return -EINVAL;
869
870 switch (cap->cap) {
871 case KVM_CAP_MIPS_FPU:
872 vcpu->arch.fpu_enabled = true;
873 break;
874 case KVM_CAP_MIPS_MSA:
875 vcpu->arch.msa_enabled = true;
876 break;
877 default:
878 r = -EINVAL;
879 break;
880 }
881
882 return r;
883 }
884
kvm_arch_vcpu_async_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)885 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
886 unsigned long arg)
887 {
888 struct kvm_vcpu *vcpu = filp->private_data;
889 void __user *argp = (void __user *)arg;
890
891 if (ioctl == KVM_INTERRUPT) {
892 struct kvm_mips_interrupt irq;
893
894 if (copy_from_user(&irq, argp, sizeof(irq)))
895 return -EFAULT;
896 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
897 irq.irq);
898
899 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
900 }
901
902 return -ENOIOCTLCMD;
903 }
904
kvm_arch_vcpu_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)905 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
906 unsigned long arg)
907 {
908 struct kvm_vcpu *vcpu = filp->private_data;
909 void __user *argp = (void __user *)arg;
910 long r;
911
912 vcpu_load(vcpu);
913
914 switch (ioctl) {
915 case KVM_SET_ONE_REG:
916 case KVM_GET_ONE_REG: {
917 struct kvm_one_reg reg;
918
919 r = -EFAULT;
920 if (copy_from_user(®, argp, sizeof(reg)))
921 break;
922 if (ioctl == KVM_SET_ONE_REG)
923 r = kvm_mips_set_reg(vcpu, ®);
924 else
925 r = kvm_mips_get_reg(vcpu, ®);
926 break;
927 }
928 case KVM_GET_REG_LIST: {
929 struct kvm_reg_list __user *user_list = argp;
930 struct kvm_reg_list reg_list;
931 unsigned n;
932
933 r = -EFAULT;
934 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
935 break;
936 n = reg_list.n;
937 reg_list.n = kvm_mips_num_regs(vcpu);
938 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
939 break;
940 r = -E2BIG;
941 if (n < reg_list.n)
942 break;
943 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
944 break;
945 }
946 case KVM_ENABLE_CAP: {
947 struct kvm_enable_cap cap;
948
949 r = -EFAULT;
950 if (copy_from_user(&cap, argp, sizeof(cap)))
951 break;
952 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
953 break;
954 }
955 default:
956 r = -ENOIOCTLCMD;
957 }
958
959 vcpu_put(vcpu);
960 return r;
961 }
962
kvm_arch_sync_dirty_log(struct kvm * kvm,struct kvm_memory_slot * memslot)963 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
964 {
965
966 }
967
kvm_arch_flush_remote_tlb(struct kvm * kvm)968 int kvm_arch_flush_remote_tlb(struct kvm *kvm)
969 {
970 kvm_mips_callbacks->prepare_flush_shadow(kvm);
971 return 1;
972 }
973
kvm_arch_flush_remote_tlbs_memslot(struct kvm * kvm,const struct kvm_memory_slot * memslot)974 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
975 const struct kvm_memory_slot *memslot)
976 {
977 kvm_flush_remote_tlbs(kvm);
978 }
979
kvm_arch_vm_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)980 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
981 {
982 long r;
983
984 switch (ioctl) {
985 default:
986 r = -ENOIOCTLCMD;
987 }
988
989 return r;
990 }
991
kvm_arch_init(void * opaque)992 int kvm_arch_init(void *opaque)
993 {
994 if (kvm_mips_callbacks) {
995 kvm_err("kvm: module already exists\n");
996 return -EEXIST;
997 }
998
999 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1000 }
1001
kvm_arch_exit(void)1002 void kvm_arch_exit(void)
1003 {
1004 kvm_mips_callbacks = NULL;
1005 }
1006
kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)1007 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1008 struct kvm_sregs *sregs)
1009 {
1010 return -ENOIOCTLCMD;
1011 }
1012
kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)1013 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1014 struct kvm_sregs *sregs)
1015 {
1016 return -ENOIOCTLCMD;
1017 }
1018
kvm_arch_vcpu_postcreate(struct kvm_vcpu * vcpu)1019 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1020 {
1021 }
1022
kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)1023 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1024 {
1025 return -ENOIOCTLCMD;
1026 }
1027
kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)1028 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1029 {
1030 return -ENOIOCTLCMD;
1031 }
1032
kvm_arch_vcpu_fault(struct kvm_vcpu * vcpu,struct vm_fault * vmf)1033 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1034 {
1035 return VM_FAULT_SIGBUS;
1036 }
1037
kvm_vm_ioctl_check_extension(struct kvm * kvm,long ext)1038 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1039 {
1040 int r;
1041
1042 switch (ext) {
1043 case KVM_CAP_ONE_REG:
1044 case KVM_CAP_ENABLE_CAP:
1045 case KVM_CAP_READONLY_MEM:
1046 case KVM_CAP_SYNC_MMU:
1047 case KVM_CAP_IMMEDIATE_EXIT:
1048 r = 1;
1049 break;
1050 case KVM_CAP_NR_VCPUS:
1051 r = num_online_cpus();
1052 break;
1053 case KVM_CAP_MAX_VCPUS:
1054 r = KVM_MAX_VCPUS;
1055 break;
1056 case KVM_CAP_MAX_VCPU_ID:
1057 r = KVM_MAX_VCPU_ID;
1058 break;
1059 case KVM_CAP_MIPS_FPU:
1060 /* We don't handle systems with inconsistent cpu_has_fpu */
1061 r = !!raw_cpu_has_fpu;
1062 break;
1063 case KVM_CAP_MIPS_MSA:
1064 /*
1065 * We don't support MSA vector partitioning yet:
1066 * 1) It would require explicit support which can't be tested
1067 * yet due to lack of support in current hardware.
1068 * 2) It extends the state that would need to be saved/restored
1069 * by e.g. QEMU for migration.
1070 *
1071 * When vector partitioning hardware becomes available, support
1072 * could be added by requiring a flag when enabling
1073 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1074 * to save/restore the appropriate extra state.
1075 */
1076 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1077 break;
1078 default:
1079 r = kvm_mips_callbacks->check_extension(kvm, ext);
1080 break;
1081 }
1082 return r;
1083 }
1084
kvm_cpu_has_pending_timer(struct kvm_vcpu * vcpu)1085 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1086 {
1087 return kvm_mips_pending_timer(vcpu) ||
1088 kvm_read_c0_guest_cause(&vcpu->arch.cop0) & C_TI;
1089 }
1090
kvm_arch_vcpu_dump_regs(struct kvm_vcpu * vcpu)1091 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1092 {
1093 int i;
1094 struct mips_coproc *cop0;
1095
1096 if (!vcpu)
1097 return -1;
1098
1099 kvm_debug("VCPU Register Dump:\n");
1100 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1101 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1102
1103 for (i = 0; i < 32; i += 4) {
1104 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1105 vcpu->arch.gprs[i],
1106 vcpu->arch.gprs[i + 1],
1107 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1108 }
1109 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1110 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1111
1112 cop0 = &vcpu->arch.cop0;
1113 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1114 kvm_read_c0_guest_status(cop0),
1115 kvm_read_c0_guest_cause(cop0));
1116
1117 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1118
1119 return 0;
1120 }
1121
kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)1122 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1123 {
1124 int i;
1125
1126 vcpu_load(vcpu);
1127
1128 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1129 vcpu->arch.gprs[i] = regs->gpr[i];
1130 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1131 vcpu->arch.hi = regs->hi;
1132 vcpu->arch.lo = regs->lo;
1133 vcpu->arch.pc = regs->pc;
1134
1135 vcpu_put(vcpu);
1136 return 0;
1137 }
1138
kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)1139 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1140 {
1141 int i;
1142
1143 vcpu_load(vcpu);
1144
1145 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1146 regs->gpr[i] = vcpu->arch.gprs[i];
1147
1148 regs->hi = vcpu->arch.hi;
1149 regs->lo = vcpu->arch.lo;
1150 regs->pc = vcpu->arch.pc;
1151
1152 vcpu_put(vcpu);
1153 return 0;
1154 }
1155
kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu * vcpu,struct kvm_translation * tr)1156 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1157 struct kvm_translation *tr)
1158 {
1159 return 0;
1160 }
1161
kvm_mips_set_c0_status(void)1162 static void kvm_mips_set_c0_status(void)
1163 {
1164 u32 status = read_c0_status();
1165
1166 if (cpu_has_dsp)
1167 status |= (ST0_MX);
1168
1169 write_c0_status(status);
1170 ehb();
1171 }
1172
1173 /*
1174 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1175 */
kvm_mips_handle_exit(struct kvm_vcpu * vcpu)1176 int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1177 {
1178 struct kvm_run *run = vcpu->run;
1179 u32 cause = vcpu->arch.host_cp0_cause;
1180 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1181 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1182 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1183 enum emulation_result er = EMULATE_DONE;
1184 u32 inst;
1185 int ret = RESUME_GUEST;
1186
1187 vcpu->mode = OUTSIDE_GUEST_MODE;
1188
1189 /* Set a default exit reason */
1190 run->exit_reason = KVM_EXIT_UNKNOWN;
1191 run->ready_for_interrupt_injection = 1;
1192
1193 /*
1194 * Set the appropriate status bits based on host CPU features,
1195 * before we hit the scheduler
1196 */
1197 kvm_mips_set_c0_status();
1198
1199 local_irq_enable();
1200
1201 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1202 cause, opc, run, vcpu);
1203 trace_kvm_exit(vcpu, exccode);
1204
1205 switch (exccode) {
1206 case EXCCODE_INT:
1207 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1208
1209 ++vcpu->stat.int_exits;
1210
1211 if (need_resched())
1212 cond_resched();
1213
1214 ret = RESUME_GUEST;
1215 break;
1216
1217 case EXCCODE_CPU:
1218 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1219
1220 ++vcpu->stat.cop_unusable_exits;
1221 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1222 /* XXXKYMA: Might need to return to user space */
1223 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1224 ret = RESUME_HOST;
1225 break;
1226
1227 case EXCCODE_MOD:
1228 ++vcpu->stat.tlbmod_exits;
1229 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1230 break;
1231
1232 case EXCCODE_TLBS:
1233 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1234 cause, kvm_read_c0_guest_status(&vcpu->arch.cop0), opc,
1235 badvaddr);
1236
1237 ++vcpu->stat.tlbmiss_st_exits;
1238 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1239 break;
1240
1241 case EXCCODE_TLBL:
1242 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1243 cause, opc, badvaddr);
1244
1245 ++vcpu->stat.tlbmiss_ld_exits;
1246 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1247 break;
1248
1249 case EXCCODE_ADES:
1250 ++vcpu->stat.addrerr_st_exits;
1251 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1252 break;
1253
1254 case EXCCODE_ADEL:
1255 ++vcpu->stat.addrerr_ld_exits;
1256 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1257 break;
1258
1259 case EXCCODE_SYS:
1260 ++vcpu->stat.syscall_exits;
1261 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1262 break;
1263
1264 case EXCCODE_RI:
1265 ++vcpu->stat.resvd_inst_exits;
1266 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1267 break;
1268
1269 case EXCCODE_BP:
1270 ++vcpu->stat.break_inst_exits;
1271 ret = kvm_mips_callbacks->handle_break(vcpu);
1272 break;
1273
1274 case EXCCODE_TR:
1275 ++vcpu->stat.trap_inst_exits;
1276 ret = kvm_mips_callbacks->handle_trap(vcpu);
1277 break;
1278
1279 case EXCCODE_MSAFPE:
1280 ++vcpu->stat.msa_fpe_exits;
1281 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1282 break;
1283
1284 case EXCCODE_FPE:
1285 ++vcpu->stat.fpe_exits;
1286 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1287 break;
1288
1289 case EXCCODE_MSADIS:
1290 ++vcpu->stat.msa_disabled_exits;
1291 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1292 break;
1293
1294 case EXCCODE_GE:
1295 /* defer exit accounting to handler */
1296 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1297 break;
1298
1299 default:
1300 if (cause & CAUSEF_BD)
1301 opc += 1;
1302 inst = 0;
1303 kvm_get_badinstr(opc, vcpu, &inst);
1304 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1305 exccode, opc, inst, badvaddr,
1306 kvm_read_c0_guest_status(&vcpu->arch.cop0));
1307 kvm_arch_vcpu_dump_regs(vcpu);
1308 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1309 ret = RESUME_HOST;
1310 break;
1311
1312 }
1313
1314 local_irq_disable();
1315
1316 if (ret == RESUME_GUEST)
1317 kvm_vz_acquire_htimer(vcpu);
1318
1319 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1320 kvm_mips_deliver_interrupts(vcpu, cause);
1321
1322 if (!(ret & RESUME_HOST)) {
1323 /* Only check for signals if not already exiting to userspace */
1324 if (signal_pending(current)) {
1325 run->exit_reason = KVM_EXIT_INTR;
1326 ret = (-EINTR << 2) | RESUME_HOST;
1327 ++vcpu->stat.signal_exits;
1328 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1329 }
1330 }
1331
1332 if (ret == RESUME_GUEST) {
1333 trace_kvm_reenter(vcpu);
1334
1335 /*
1336 * Make sure the read of VCPU requests in vcpu_reenter()
1337 * callback is not reordered ahead of the write to vcpu->mode,
1338 * or we could miss a TLB flush request while the requester sees
1339 * the VCPU as outside of guest mode and not needing an IPI.
1340 */
1341 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1342
1343 kvm_mips_callbacks->vcpu_reenter(vcpu);
1344
1345 /*
1346 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1347 * is live), restore FCR31 / MSACSR.
1348 *
1349 * This should be before returning to the guest exception
1350 * vector, as it may well cause an [MSA] FP exception if there
1351 * are pending exception bits unmasked. (see
1352 * kvm_mips_csr_die_notifier() for how that is handled).
1353 */
1354 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1355 read_c0_status() & ST0_CU1)
1356 __kvm_restore_fcsr(&vcpu->arch);
1357
1358 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1359 read_c0_config5() & MIPS_CONF5_MSAEN)
1360 __kvm_restore_msacsr(&vcpu->arch);
1361 }
1362 return ret;
1363 }
1364
1365 /* Enable FPU for guest and restore context */
kvm_own_fpu(struct kvm_vcpu * vcpu)1366 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1367 {
1368 struct mips_coproc *cop0 = &vcpu->arch.cop0;
1369 unsigned int sr, cfg5;
1370
1371 preempt_disable();
1372
1373 sr = kvm_read_c0_guest_status(cop0);
1374
1375 /*
1376 * If MSA state is already live, it is undefined how it interacts with
1377 * FR=0 FPU state, and we don't want to hit reserved instruction
1378 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1379 * play it safe and save it first.
1380 */
1381 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1382 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1383 kvm_lose_fpu(vcpu);
1384
1385 /*
1386 * Enable FPU for guest
1387 * We set FR and FRE according to guest context
1388 */
1389 change_c0_status(ST0_CU1 | ST0_FR, sr);
1390 if (cpu_has_fre) {
1391 cfg5 = kvm_read_c0_guest_config5(cop0);
1392 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1393 }
1394 enable_fpu_hazard();
1395
1396 /* If guest FPU state not active, restore it now */
1397 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1398 __kvm_restore_fpu(&vcpu->arch);
1399 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1400 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1401 } else {
1402 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1403 }
1404
1405 preempt_enable();
1406 }
1407
1408 #ifdef CONFIG_CPU_HAS_MSA
1409 /* Enable MSA for guest and restore context */
kvm_own_msa(struct kvm_vcpu * vcpu)1410 void kvm_own_msa(struct kvm_vcpu *vcpu)
1411 {
1412 struct mips_coproc *cop0 = &vcpu->arch.cop0;
1413 unsigned int sr, cfg5;
1414
1415 preempt_disable();
1416
1417 /*
1418 * Enable FPU if enabled in guest, since we're restoring FPU context
1419 * anyway. We set FR and FRE according to guest context.
1420 */
1421 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1422 sr = kvm_read_c0_guest_status(cop0);
1423
1424 /*
1425 * If FR=0 FPU state is already live, it is undefined how it
1426 * interacts with MSA state, so play it safe and save it first.
1427 */
1428 if (!(sr & ST0_FR) &&
1429 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1430 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1431 kvm_lose_fpu(vcpu);
1432
1433 change_c0_status(ST0_CU1 | ST0_FR, sr);
1434 if (sr & ST0_CU1 && cpu_has_fre) {
1435 cfg5 = kvm_read_c0_guest_config5(cop0);
1436 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1437 }
1438 }
1439
1440 /* Enable MSA for guest */
1441 set_c0_config5(MIPS_CONF5_MSAEN);
1442 enable_fpu_hazard();
1443
1444 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1445 case KVM_MIPS_AUX_FPU:
1446 /*
1447 * Guest FPU state already loaded, only restore upper MSA state
1448 */
1449 __kvm_restore_msa_upper(&vcpu->arch);
1450 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1451 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1452 break;
1453 case 0:
1454 /* Neither FPU or MSA already active, restore full MSA state */
1455 __kvm_restore_msa(&vcpu->arch);
1456 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1457 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1458 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1459 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1460 KVM_TRACE_AUX_FPU_MSA);
1461 break;
1462 default:
1463 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1464 break;
1465 }
1466
1467 preempt_enable();
1468 }
1469 #endif
1470
1471 /* Drop FPU & MSA without saving it */
kvm_drop_fpu(struct kvm_vcpu * vcpu)1472 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1473 {
1474 preempt_disable();
1475 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1476 disable_msa();
1477 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1478 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1479 }
1480 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1481 clear_c0_status(ST0_CU1 | ST0_FR);
1482 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1483 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1484 }
1485 preempt_enable();
1486 }
1487
1488 /* Save and disable FPU & MSA */
kvm_lose_fpu(struct kvm_vcpu * vcpu)1489 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1490 {
1491 /*
1492 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1493 * is disabled in guest context (software), but the register state in
1494 * the hardware may still be in use.
1495 * This is why we explicitly re-enable the hardware before saving.
1496 */
1497
1498 preempt_disable();
1499 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1500 __kvm_save_msa(&vcpu->arch);
1501 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1502
1503 /* Disable MSA & FPU */
1504 disable_msa();
1505 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1506 clear_c0_status(ST0_CU1 | ST0_FR);
1507 disable_fpu_hazard();
1508 }
1509 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1510 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1511 __kvm_save_fpu(&vcpu->arch);
1512 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1513 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1514
1515 /* Disable FPU */
1516 clear_c0_status(ST0_CU1 | ST0_FR);
1517 disable_fpu_hazard();
1518 }
1519 preempt_enable();
1520 }
1521
1522 /*
1523 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1524 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1525 * exception if cause bits are set in the value being written.
1526 */
kvm_mips_csr_die_notify(struct notifier_block * self,unsigned long cmd,void * ptr)1527 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1528 unsigned long cmd, void *ptr)
1529 {
1530 struct die_args *args = (struct die_args *)ptr;
1531 struct pt_regs *regs = args->regs;
1532 unsigned long pc;
1533
1534 /* Only interested in FPE and MSAFPE */
1535 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1536 return NOTIFY_DONE;
1537
1538 /* Return immediately if guest context isn't active */
1539 if (!(current->flags & PF_VCPU))
1540 return NOTIFY_DONE;
1541
1542 /* Should never get here from user mode */
1543 BUG_ON(user_mode(regs));
1544
1545 pc = instruction_pointer(regs);
1546 switch (cmd) {
1547 case DIE_FP:
1548 /* match 2nd instruction in __kvm_restore_fcsr */
1549 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1550 return NOTIFY_DONE;
1551 break;
1552 case DIE_MSAFP:
1553 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1554 if (!cpu_has_msa ||
1555 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1556 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1557 return NOTIFY_DONE;
1558 break;
1559 }
1560
1561 /* Move PC forward a little and continue executing */
1562 instruction_pointer(regs) += 4;
1563
1564 return NOTIFY_STOP;
1565 }
1566
1567 static struct notifier_block kvm_mips_csr_die_notifier = {
1568 .notifier_call = kvm_mips_csr_die_notify,
1569 };
1570
1571 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1572 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1573 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1574 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1575 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1576 };
1577
1578 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1579 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1580 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1581 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1582 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1583 };
1584
1585 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1586
kvm_irq_to_priority(u32 irq)1587 u32 kvm_irq_to_priority(u32 irq)
1588 {
1589 int i;
1590
1591 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1592 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1593 return i;
1594 }
1595
1596 return MIPS_EXC_MAX;
1597 }
1598
kvm_mips_init(void)1599 static int __init kvm_mips_init(void)
1600 {
1601 int ret;
1602
1603 if (cpu_has_mmid) {
1604 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1605 return -EOPNOTSUPP;
1606 }
1607
1608 ret = kvm_mips_entry_setup();
1609 if (ret)
1610 return ret;
1611
1612 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1613
1614 if (ret)
1615 return ret;
1616
1617 if (boot_cpu_type() == CPU_LOONGSON64)
1618 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1619
1620 register_die_notifier(&kvm_mips_csr_die_notifier);
1621
1622 return 0;
1623 }
1624
kvm_mips_exit(void)1625 static void __exit kvm_mips_exit(void)
1626 {
1627 kvm_exit();
1628
1629 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1630 }
1631
1632 module_init(kvm_mips_init);
1633 module_exit(kvm_mips_exit);
1634
1635 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
1636