1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 4 * Initial PowerPC version. 5 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Rewritten for PReP 7 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 8 * Low-level exception handers, MMU support, and rewrite. 9 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 10 * PowerPC 8xx modifications. 11 * Copyright (c) 1998-1999 TiVo, Inc. 12 * PowerPC 403GCX modifications. 13 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 14 * PowerPC 403GCX/405GP modifications. 15 * Copyright 2000 MontaVista Software Inc. 16 * PPC405 modifications 17 * PowerPC 403GCX/405GP modifications. 18 * Author: MontaVista Software, Inc. 19 * frank_rowand@mvista.com or source@mvista.com 20 * debbie_chu@mvista.com 21 * 22 * Module name: head_4xx.S 23 * 24 * Description: 25 * Kernel execution entry point code. 26 */ 27 28#include <linux/init.h> 29#include <linux/pgtable.h> 30#include <linux/sizes.h> 31#include <asm/processor.h> 32#include <asm/page.h> 33#include <asm/mmu.h> 34#include <asm/cputable.h> 35#include <asm/thread_info.h> 36#include <asm/ppc_asm.h> 37#include <asm/asm-offsets.h> 38#include <asm/ptrace.h> 39#include <asm/export.h> 40 41#include "head_32.h" 42 43/* As with the other PowerPC ports, it is expected that when code 44 * execution begins here, the following registers contain valid, yet 45 * optional, information: 46 * 47 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 48 * r4 - Starting address of the init RAM disk 49 * r5 - Ending address of the init RAM disk 50 * r6 - Start of kernel command line string (e.g. "mem=96m") 51 * r7 - End of kernel command line string 52 * 53 * This is all going to change RSN when we add bi_recs....... -- Dan 54 */ 55 __HEAD 56_ENTRY(_stext); 57_ENTRY(_start); 58 59 mr r31,r3 /* save device tree ptr */ 60 61 /* We have to turn on the MMU right away so we get cache modes 62 * set correctly. 63 */ 64 bl initial_mmu 65 66/* We now have the lower 16 Meg mapped into TLB entries, and the caches 67 * ready to work. 68 */ 69turn_on_mmu: 70 lis r0,MSR_KERNEL@h 71 ori r0,r0,MSR_KERNEL@l 72 mtspr SPRN_SRR1,r0 73 lis r0,start_here@h 74 ori r0,r0,start_here@l 75 mtspr SPRN_SRR0,r0 76 rfi /* enables MMU */ 77 b . /* prevent prefetch past rfi */ 78 79/* 80 * This area is used for temporarily saving registers during the 81 * critical exception prolog. 82 */ 83 . = 0xc0 84crit_save: 85_ENTRY(crit_r10) 86 .space 4 87_ENTRY(crit_r11) 88 .space 4 89_ENTRY(crit_srr0) 90 .space 4 91_ENTRY(crit_srr1) 92 .space 4 93_ENTRY(crit_r1) 94 .space 4 95_ENTRY(crit_dear) 96 .space 4 97_ENTRY(crit_esr) 98 .space 4 99 100/* 101 * Exception prolog for critical exceptions. This is a little different 102 * from the normal exception prolog above since a critical exception 103 * can potentially occur at any point during normal exception processing. 104 * Thus we cannot use the same SPRG registers as the normal prolog above. 105 * Instead we use a couple of words of memory at low physical addresses. 106 * This is OK since we don't support SMP on these processors. 107 */ 108.macro CRITICAL_EXCEPTION_PROLOG trapno name 109 stw r10,crit_r10@l(0) /* save two registers to work with */ 110 stw r11,crit_r11@l(0) 111 mfspr r10,SPRN_SRR0 112 mfspr r11,SPRN_SRR1 113 stw r10,crit_srr0@l(0) 114 stw r11,crit_srr1@l(0) 115 mfspr r10,SPRN_DEAR 116 mfspr r11,SPRN_ESR 117 stw r10,crit_dear@l(0) 118 stw r11,crit_esr@l(0) 119 mfcr r10 /* save CR in r10 for now */ 120 mfspr r11,SPRN_SRR3 /* check whether user or kernel */ 121 andi. r11,r11,MSR_PR 122 lis r11,(critirq_ctx-PAGE_OFFSET)@ha 123 lwz r11,(critirq_ctx-PAGE_OFFSET)@l(r11) 124 beq 1f 125 /* COMING FROM USER MODE */ 126 mfspr r11,SPRN_SPRG_THREAD /* if from user, start at top of */ 127 lwz r11,TASK_STACK-THREAD(r11) /* this thread's kernel stack */ 1281: stw r1,crit_r1@l(0) 129 addi r1,r11,THREAD_SIZE-INT_FRAME_SIZE /* Alloc an excpt frm */ 130 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)) /* re-enable MMU */ 131 mtspr SPRN_SRR1, r11 132 lis r11, 1f@h 133 ori r11, r11, 1f@l 134 mtspr SPRN_SRR0, r11 135 rfi 136 137 .text 1381: 139\name\()_virt: 140 lwz r11,crit_r1@l(0) 141 stw r11,GPR1(r1) 142 stw r11,0(r1) 143 mr r11,r1 144 stw r10,_CCR(r11) /* save various registers */ 145 stw r12,GPR12(r11) 146 stw r9,GPR9(r11) 147 mflr r10 148 stw r10,_LINK(r11) 149 lis r9,PAGE_OFFSET@ha 150 lwz r10,crit_r10@l(r9) 151 lwz r12,crit_r11@l(r9) 152 stw r10,GPR10(r11) 153 stw r12,GPR11(r11) 154 lwz r12,crit_dear@l(r9) 155 lwz r9,crit_esr@l(r9) 156 stw r12,_DEAR(r11) /* since they may have had stuff */ 157 stw r9,_ESR(r11) /* exception was taken */ 158 mfspr r12,SPRN_SRR2 159 mfspr r9,SPRN_SRR3 160 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 161 COMMON_EXCEPTION_PROLOG_END \trapno + 2 162_ASM_NOKPROBE_SYMBOL(\name\()_virt) 163.endm 164 165 /* 166 * State at this point: 167 * r9 saved in stack frame, now saved SRR3 & ~MSR_WE 168 * r10 saved in crit_r10 and in stack frame, trashed 169 * r11 saved in crit_r11 and in stack frame, 170 * now phys stack/exception frame pointer 171 * r12 saved in stack frame, now saved SRR2 172 * CR saved in stack frame, CR0.EQ = !SRR3.PR 173 * LR, DEAR, ESR in stack frame 174 * r1 saved in stack frame, now virt stack/excframe pointer 175 * r0, r3-r8 saved in stack frame 176 */ 177 178/* 179 * Exception vectors. 180 */ 181#define CRITICAL_EXCEPTION(n, label, hdlr) \ 182 START_EXCEPTION(n, label); \ 183 CRITICAL_EXCEPTION_PROLOG n label; \ 184 prepare_transfer_to_handler; \ 185 bl hdlr; \ 186 b ret_from_crit_exc 187 188/* 189 * 0x0100 - Critical Interrupt Exception 190 */ 191 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) 192 193/* 194 * 0x0200 - Machine Check Exception 195 */ 196 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 197 198/* 199 * 0x0300 - Data Storage Exception 200 * This happens for just a few reasons. U0 set (but we don't do that), 201 * or zone protection fault (user violation, write to protected page). 202 * The other Data TLB exceptions bail out to this point 203 * if they can't resolve the lightweight TLB fault. 204 */ 205 START_EXCEPTION(0x0300, DataStorage) 206 EXCEPTION_PROLOG 0x300 DataStorage handle_dar_dsisr=1 207 prepare_transfer_to_handler 208 bl do_page_fault 209 b interrupt_return 210 211/* 212 * 0x0400 - Instruction Storage Exception 213 * This is caused by a fetch from non-execute or guarded pages. 214 */ 215 START_EXCEPTION(0x0400, InstructionAccess) 216 EXCEPTION_PROLOG 0x400 InstructionAccess 217 li r5,0 218 stw r5, _ESR(r11) /* Zero ESR */ 219 stw r12, _DEAR(r11) /* SRR0 as DEAR */ 220 prepare_transfer_to_handler 221 bl do_page_fault 222 b interrupt_return 223 224/* 0x0500 - External Interrupt Exception */ 225 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ) 226 227/* 0x0600 - Alignment Exception */ 228 START_EXCEPTION(0x0600, Alignment) 229 EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1 230 prepare_transfer_to_handler 231 bl alignment_exception 232 REST_NVGPRS(r1) 233 b interrupt_return 234 235/* 0x0700 - Program Exception */ 236 START_EXCEPTION(0x0700, ProgramCheck) 237 EXCEPTION_PROLOG 0x700 ProgramCheck handle_dar_dsisr=1 238 prepare_transfer_to_handler 239 bl program_check_exception 240 REST_NVGPRS(r1) 241 b interrupt_return 242 243 EXCEPTION(0x0800, Trap_08, unknown_exception) 244 EXCEPTION(0x0900, Trap_09, unknown_exception) 245 EXCEPTION(0x0A00, Trap_0A, unknown_exception) 246 EXCEPTION(0x0B00, Trap_0B, unknown_exception) 247 248/* 0x0C00 - System Call Exception */ 249 START_EXCEPTION(0x0C00, SystemCall) 250 SYSCALL_ENTRY 0xc00 251/* Trap_0D is commented out to get more space for system call exception */ 252 253/* EXCEPTION(0x0D00, Trap_0D, unknown_exception) */ 254 EXCEPTION(0x0E00, Trap_0E, unknown_exception) 255 EXCEPTION(0x0F00, Trap_0F, unknown_exception) 256 257/* 0x1000 - Programmable Interval Timer (PIT) Exception */ 258 START_EXCEPTION(0x1000, DecrementerTrap) 259 b Decrementer 260 261/* 0x1010 - Fixed Interval Timer (FIT) Exception */ 262 START_EXCEPTION(0x1010, FITExceptionTrap) 263 b FITException 264 265/* 0x1020 - Watchdog Timer (WDT) Exception */ 266 START_EXCEPTION(0x1020, WDTExceptionTrap) 267 b WDTException 268 269/* 0x1100 - Data TLB Miss Exception 270 * As the name implies, translation is not in the MMU, so search the 271 * page tables and fix it. The only purpose of this function is to 272 * load TLB entries from the page table if they exist. 273 */ 274 START_EXCEPTION(0x1100, DTLBMiss) 275 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */ 276 mtspr SPRN_SPRG_SCRATCH6, r11 277 mtspr SPRN_SPRG_SCRATCH3, r12 278 mtspr SPRN_SPRG_SCRATCH4, r9 279 mfcr r12 280 mfspr r9, SPRN_PID 281 rlwimi r12, r9, 0, 0xff 282 mfspr r10, SPRN_DEAR /* Get faulting address */ 283 284 /* If we are faulting a kernel address, we have to use the 285 * kernel page tables. 286 */ 287 lis r11, PAGE_OFFSET@h 288 cmplw r10, r11 289 blt+ 3f 290 lis r11, swapper_pg_dir@h 291 ori r11, r11, swapper_pg_dir@l 292 li r9, 0 293 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 294 b 4f 295 296 /* Get the PGD for the current thread. 297 */ 2983: 299 mfspr r11,SPRN_SPRG_THREAD 300 lwz r11,PGDIR(r11) 3014: 302 tophys(r11, r11) 303 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 304 lwz r11, 0(r11) /* Get L1 entry */ 305 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 306 beq 2f /* Bail if no table */ 307 308 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 309 lwz r11, 0(r11) /* Get Linux PTE */ 310 li r9, _PAGE_PRESENT | _PAGE_ACCESSED 311 andc. r9, r9, r11 /* Check permission */ 312 bne 5f 313 314 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 315 and r9, r9, r11 /* hwwrite = dirty & rw */ 316 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 317 318 /* Create TLB tag. This is the faulting address plus a static 319 * set of bits. These are size, valid, E, U0. 320 */ 321 li r9, 0x00c0 322 rlwimi r10, r9, 0, 20, 31 323 324 b finish_tlb_load 325 3262: /* Check for possible large-page pmd entry */ 327 rlwinm. r9, r11, 2, 22, 24 328 beq 5f 329 330 /* Create TLB tag. This is the faulting address, plus a static 331 * set of bits (valid, E, U0) plus the size from the PMD. 332 */ 333 ori r9, r9, 0x40 334 rlwimi r10, r9, 0, 20, 31 335 336 b finish_tlb_load 337 3385: 339 /* The bailout. Restore registers to pre-exception conditions 340 * and call the heavyweights to help us out. 341 */ 342 mtspr SPRN_PID, r12 343 mtcrf 0x80, r12 344 mfspr r9, SPRN_SPRG_SCRATCH4 345 mfspr r12, SPRN_SPRG_SCRATCH3 346 mfspr r11, SPRN_SPRG_SCRATCH6 347 mfspr r10, SPRN_SPRG_SCRATCH5 348 b DataStorage 349 350/* 0x1200 - Instruction TLB Miss Exception 351 * Nearly the same as above, except we get our information from different 352 * registers and bailout to a different point. 353 */ 354 START_EXCEPTION(0x1200, ITLBMiss) 355 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */ 356 mtspr SPRN_SPRG_SCRATCH6, r11 357 mtspr SPRN_SPRG_SCRATCH3, r12 358 mtspr SPRN_SPRG_SCRATCH4, r9 359 mfcr r12 360 mfspr r9, SPRN_PID 361 rlwimi r12, r9, 0, 0xff 362 mfspr r10, SPRN_SRR0 /* Get faulting address */ 363 364 /* If we are faulting a kernel address, we have to use the 365 * kernel page tables. 366 */ 367 lis r11, PAGE_OFFSET@h 368 cmplw r10, r11 369 blt+ 3f 370 lis r11, swapper_pg_dir@h 371 ori r11, r11, swapper_pg_dir@l 372 li r9, 0 373 mtspr SPRN_PID, r9 /* TLB will have 0 TID */ 374 b 4f 375 376 /* Get the PGD for the current thread. 377 */ 3783: 379 mfspr r11,SPRN_SPRG_THREAD 380 lwz r11,PGDIR(r11) 3814: 382 tophys(r11, r11) 383 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ 384 lwz r11, 0(r11) /* Get L1 entry */ 385 andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ 386 beq 2f /* Bail if no table */ 387 388 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 389 lwz r11, 0(r11) /* Get Linux PTE */ 390 li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 391 andc. r9, r9, r11 /* Check permission */ 392 bne 5f 393 394 rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ 395 and r9, r9, r11 /* hwwrite = dirty & rw */ 396 rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ 397 398 /* Create TLB tag. This is the faulting address plus a static 399 * set of bits. These are size, valid, E, U0. 400 */ 401 li r9, 0x00c0 402 rlwimi r10, r9, 0, 20, 31 403 404 b finish_tlb_load 405 4062: /* Check for possible large-page pmd entry */ 407 rlwinm. r9, r11, 2, 22, 24 408 beq 5f 409 410 /* Create TLB tag. This is the faulting address, plus a static 411 * set of bits (valid, E, U0) plus the size from the PMD. 412 */ 413 ori r9, r9, 0x40 414 rlwimi r10, r9, 0, 20, 31 415 416 b finish_tlb_load 417 4185: 419 /* The bailout. Restore registers to pre-exception conditions 420 * and call the heavyweights to help us out. 421 */ 422 mtspr SPRN_PID, r12 423 mtcrf 0x80, r12 424 mfspr r9, SPRN_SPRG_SCRATCH4 425 mfspr r12, SPRN_SPRG_SCRATCH3 426 mfspr r11, SPRN_SPRG_SCRATCH6 427 mfspr r10, SPRN_SPRG_SCRATCH5 428 b InstructionAccess 429 430 EXCEPTION(0x1300, Trap_13, unknown_exception) 431 EXCEPTION(0x1400, Trap_14, unknown_exception) 432 EXCEPTION(0x1500, Trap_15, unknown_exception) 433 EXCEPTION(0x1600, Trap_16, unknown_exception) 434 EXCEPTION(0x1700, Trap_17, unknown_exception) 435 EXCEPTION(0x1800, Trap_18, unknown_exception) 436 EXCEPTION(0x1900, Trap_19, unknown_exception) 437 EXCEPTION(0x1A00, Trap_1A, unknown_exception) 438 EXCEPTION(0x1B00, Trap_1B, unknown_exception) 439 EXCEPTION(0x1C00, Trap_1C, unknown_exception) 440 EXCEPTION(0x1D00, Trap_1D, unknown_exception) 441 EXCEPTION(0x1E00, Trap_1E, unknown_exception) 442 EXCEPTION(0x1F00, Trap_1F, unknown_exception) 443 444/* Check for a single step debug exception while in an exception 445 * handler before state has been saved. This is to catch the case 446 * where an instruction that we are trying to single step causes 447 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 448 * the exception handler generates a single step debug exception. 449 * 450 * If we get a debug trap on the first instruction of an exception handler, 451 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 452 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 453 * The exception handler was handling a non-critical interrupt, so it will 454 * save (and later restore) the MSR via SPRN_SRR1, which will still have 455 * the MSR_DE bit set. 456 */ 457 /* 0x2000 - Debug Exception */ 458 START_EXCEPTION(0x2000, DebugTrap) 459 CRITICAL_EXCEPTION_PROLOG 0x2000 DebugTrap 460 461 /* 462 * If this is a single step or branch-taken exception in an 463 * exception entry sequence, it was probably meant to apply to 464 * the code where the exception occurred (since exception entry 465 * doesn't turn off DE automatically). We simulate the effect 466 * of turning off DE on entry to an exception handler by turning 467 * off DE in the SRR3 value and clearing the debug status. 468 */ 469 mfspr r10,SPRN_DBSR /* check single-step/branch taken */ 470 andis. r10,r10,DBSR_IC@h 471 beq+ 2f 472 473 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ 474 beq 1f /* branch and fix it up */ 475 476 mfspr r10,SPRN_SRR2 /* Faulting instruction address */ 477 cmplwi r10,0x2100 478 bgt+ 2f /* address above exception vectors */ 479 480 /* here it looks like we got an inappropriate debug exception. */ 4811: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ 482 lis r10,DBSR_IC@h /* clear the IC event */ 483 mtspr SPRN_DBSR,r10 484 /* restore state and get out */ 485 lwz r10,_CCR(r11) 486 lwz r0,GPR0(r11) 487 lwz r1,GPR1(r11) 488 mtcrf 0x80,r10 489 mtspr SPRN_SRR2,r12 490 mtspr SPRN_SRR3,r9 491 lwz r9,GPR9(r11) 492 lwz r12,GPR12(r11) 493 lwz r10,crit_r10@l(0) 494 lwz r11,crit_r11@l(0) 495 rfci 496 b . 497 498 /* continue normal handling for a critical exception... */ 4992: mfspr r4,SPRN_DBSR 500 stw r4,_ESR(r11) /* DebugException takes DBSR in _ESR */ 501 prepare_transfer_to_handler 502 bl DebugException 503 b ret_from_crit_exc 504 505 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ 506 __HEAD 507Decrementer: 508 EXCEPTION_PROLOG 0x1000 Decrementer 509 lis r0,TSR_PIS@h 510 mtspr SPRN_TSR,r0 /* Clear the PIT exception */ 511 prepare_transfer_to_handler 512 bl timer_interrupt 513 b interrupt_return 514 515 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ 516 __HEAD 517FITException: 518 EXCEPTION_PROLOG 0x1010 FITException 519 prepare_transfer_to_handler 520 bl unknown_exception 521 b interrupt_return 522 523 /* Watchdog Timer (WDT) Exception. (from 0x1020) */ 524 __HEAD 525WDTException: 526 CRITICAL_EXCEPTION_PROLOG 0x1020 WDTException 527 prepare_transfer_to_handler 528 bl WatchdogException 529 b ret_from_crit_exc 530 531/* Other PowerPC processors, namely those derived from the 6xx-series 532 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. 533 * However, for the 4xx-series processors these are neither defined nor 534 * reserved. 535 */ 536 537 __HEAD 538 /* Damn, I came up one instruction too many to fit into the 539 * exception space :-). Both the instruction and data TLB 540 * miss get to this point to load the TLB. 541 * r10 - TLB_TAG value 542 * r11 - Linux PTE 543 * r9 - available to use 544 * PID - loaded with proper value when we get here 545 * Upon exit, we reload everything and RFI. 546 * Actually, it will fit now, but oh well.....a common place 547 * to load the TLB. 548 */ 549tlb_4xx_index: 550 .long 0 551finish_tlb_load: 552 /* 553 * Clear out the software-only bits in the PTE to generate the 554 * TLB_DATA value. These are the bottom 2 bits of the RPM, the 555 * top 3 bits of the zone field, and M. 556 */ 557 li r9, 0x0ce2 558 andc r11, r11, r9 559 560 /* load the next available TLB index. */ 561 lwz r9, tlb_4xx_index@l(0) 562 addi r9, r9, 1 563 andi. r9, r9, PPC40X_TLB_SIZE - 1 564 stw r9, tlb_4xx_index@l(0) 565 566 tlbwe r11, r9, TLB_DATA /* Load TLB LO */ 567 tlbwe r10, r9, TLB_TAG /* Load TLB HI */ 568 569 /* Done...restore registers and get out of here. 570 */ 571 mtspr SPRN_PID, r12 572 mtcrf 0x80, r12 573 mfspr r9, SPRN_SPRG_SCRATCH4 574 mfspr r12, SPRN_SPRG_SCRATCH3 575 mfspr r11, SPRN_SPRG_SCRATCH6 576 mfspr r10, SPRN_SPRG_SCRATCH5 577 rfi /* Should sync shadow TLBs */ 578 b . /* prevent prefetch past rfi */ 579 580/* This is where the main kernel code starts. 581 */ 582start_here: 583 584 /* ptr to current */ 585 lis r2,init_task@h 586 ori r2,r2,init_task@l 587 588 /* ptr to phys current thread */ 589 tophys(r4,r2) 590 addi r4,r4,THREAD /* init task's THREAD */ 591 mtspr SPRN_SPRG_THREAD,r4 592 593 /* stack */ 594 lis r1,init_thread_union@ha 595 addi r1,r1,init_thread_union@l 596 li r0,0 597 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 598 599 bl early_init /* We have to do this with MMU on */ 600 601/* 602 * Decide what sort of machine this is and initialize the MMU. 603 */ 604#ifdef CONFIG_KASAN 605 bl kasan_early_init 606#endif 607 li r3,0 608 mr r4,r31 609 bl machine_init 610 bl MMU_init 611 612/* Go back to running unmapped so we can load up new values 613 * and change to using our exception vectors. 614 * On the 4xx, all we have to do is invalidate the TLB to clear 615 * the old 16M byte TLB mappings. 616 */ 617 lis r4,2f@h 618 ori r4,r4,2f@l 619 tophys(r4,r4) 620 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h 621 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l 622 mtspr SPRN_SRR0,r4 623 mtspr SPRN_SRR1,r3 624 rfi 625 b . /* prevent prefetch past rfi */ 626 627/* Load up the kernel context */ 6282: 629 sync /* Flush to memory before changing TLB */ 630 tlbia 631 isync /* Flush shadow TLBs */ 632 633 /* set up the PTE pointers for the Abatron bdiGDB. 634 */ 635 lis r6, swapper_pg_dir@h 636 ori r6, r6, swapper_pg_dir@l 637 lis r5, abatron_pteptrs@h 638 ori r5, r5, abatron_pteptrs@l 639 stw r5, 0xf0(0) /* Must match your Abatron config file */ 640 tophys(r5,r5) 641 stw r6, 0(r5) 642 643/* Now turn on the MMU for real! */ 644 lis r4,MSR_KERNEL@h 645 ori r4,r4,MSR_KERNEL@l 646 lis r3,start_kernel@h 647 ori r3,r3,start_kernel@l 648 mtspr SPRN_SRR0,r3 649 mtspr SPRN_SRR1,r4 650 rfi /* enable MMU and jump to start_kernel */ 651 b . /* prevent prefetch past rfi */ 652 653/* Set up the initial MMU state so we can do the first level of 654 * kernel initialization. This maps the first 32 MBytes of memory 1:1 655 * virtual to physical and more importantly sets the cache mode. 656 */ 657initial_mmu: 658 tlbia /* Invalidate all TLB entries */ 659 isync 660 661 /* We should still be executing code at physical address 0x0000xxxx 662 * at this point. However, start_here is at virtual address 663 * 0xC000xxxx. So, set up a TLB mapping to cover this once 664 * translation is enabled. 665 */ 666 667 lis r3,KERNELBASE@h /* Load the kernel virtual address */ 668 ori r3,r3,KERNELBASE@l 669 tophys(r4,r3) /* Load the kernel physical address */ 670 671 iccci r0,r3 /* Invalidate the i-cache before use */ 672 673 /* Load the kernel PID. 674 */ 675 li r0,0 676 mtspr SPRN_PID,r0 677 sync 678 679 /* Configure and load one entry into TLB slots 63 */ 680 clrrwi r4,r4,10 /* Mask off the real page number */ 681 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 682 683 clrrwi r3,r3,10 /* Mask off the effective page number */ 684 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 685 686 li r0,63 /* TLB slot 63 */ 687 688 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 689 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 690 691 li r0,62 /* TLB slot 62 */ 692 addis r4,r4,SZ_16M@h 693 addis r3,r3,SZ_16M@h 694 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ 695 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ 696 697 isync 698 699 /* Establish the exception vector base 700 */ 701 lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ 702 tophys(r0,r4) /* Use the physical address */ 703 mtspr SPRN_EVPR,r0 704 705 blr 706 707_GLOBAL(abort) 708 mfspr r13,SPRN_DBCR0 709 oris r13,r13,DBCR0_RST_SYSTEM@h 710 mtspr SPRN_DBCR0,r13 711