1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Common Performance counter support functions for PowerISA v2.07 processors.
4 *
5 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * Copyright 2013 Michael Ellerman, IBM Corporation.
7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
8 */
9 #include "isa207-common.h"
10
11 PMU_FORMAT_ATTR(event, "config:0-49");
12 PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
13 PMU_FORMAT_ATTR(mark, "config:8");
14 PMU_FORMAT_ATTR(combine, "config:11");
15 PMU_FORMAT_ATTR(unit, "config:12-15");
16 PMU_FORMAT_ATTR(pmc, "config:16-19");
17 PMU_FORMAT_ATTR(cache_sel, "config:20-23");
18 PMU_FORMAT_ATTR(sample_mode, "config:24-28");
19 PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
20 PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
21 PMU_FORMAT_ATTR(thresh_start, "config:36-39");
22 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
23
24 static struct attribute *isa207_pmu_format_attr[] = {
25 &format_attr_event.attr,
26 &format_attr_pmcxsel.attr,
27 &format_attr_mark.attr,
28 &format_attr_combine.attr,
29 &format_attr_unit.attr,
30 &format_attr_pmc.attr,
31 &format_attr_cache_sel.attr,
32 &format_attr_sample_mode.attr,
33 &format_attr_thresh_sel.attr,
34 &format_attr_thresh_stop.attr,
35 &format_attr_thresh_start.attr,
36 &format_attr_thresh_cmp.attr,
37 NULL,
38 };
39
40 struct attribute_group isa207_pmu_format_group = {
41 .name = "format",
42 .attrs = isa207_pmu_format_attr,
43 };
44
event_is_fab_match(u64 event)45 static inline bool event_is_fab_match(u64 event)
46 {
47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
48 event &= 0xff0fe;
49
50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
51 return (event == 0x30056 || event == 0x4f052);
52 }
53
is_event_valid(u64 event)54 static bool is_event_valid(u64 event)
55 {
56 u64 valid_mask = EVENT_VALID_MASK;
57
58 if (cpu_has_feature(CPU_FTR_ARCH_31))
59 valid_mask = p10_EVENT_VALID_MASK;
60 else if (cpu_has_feature(CPU_FTR_ARCH_300))
61 valid_mask = p9_EVENT_VALID_MASK;
62
63 return !(event & ~valid_mask);
64 }
65
is_event_marked(u64 event)66 static inline bool is_event_marked(u64 event)
67 {
68 if (event & EVENT_IS_MARKED)
69 return true;
70
71 return false;
72 }
73
sdar_mod_val(u64 event)74 static unsigned long sdar_mod_val(u64 event)
75 {
76 if (cpu_has_feature(CPU_FTR_ARCH_31))
77 return p10_SDAR_MODE(event);
78
79 return p9_SDAR_MODE(event);
80 }
81
mmcra_sdar_mode(u64 event,unsigned long * mmcra)82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
83 {
84 /*
85 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
86 * continous sampling mode.
87 *
88 * Incase of Power8:
89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling
90 * mode and will be un-changed when setting MMCRA[63] (Marked events).
91 *
92 * Incase of Power9/power10:
93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
94 * or if group already have any marked events.
95 * For rest
96 * MMCRA[SDAR_MODE] will be set from event code.
97 * If sdar_mode from event is zero, default to 0b01. Hardware
98 * requires that we set a non-zero value.
99 */
100 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
103 else if (sdar_mod_val(event))
104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
105 else
106 *mmcra |= MMCRA_SDAR_MODE_DCACHE;
107 } else
108 *mmcra |= MMCRA_SDAR_MODE_TLB;
109 }
110
p10_thresh_cmp_val(u64 value)111 static int p10_thresh_cmp_val(u64 value)
112 {
113 int exp = 0;
114 u64 result = value;
115
116 if (!value)
117 return value;
118
119 /*
120 * Incase of P10, thresh_cmp value is not part of raw event code
121 * and provided via attr.config1 parameter. To program threshold in MMCRA,
122 * take a 18 bit number N and shift right 2 places and increment
123 * the exponent E by 1 until the upper 10 bits of N are zero.
124 * Write E to the threshold exponent and write the lower 8 bits of N
125 * to the threshold mantissa.
126 * The max threshold that can be written is 261120.
127 */
128 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
129 if (value > 261120)
130 value = 261120;
131 while ((64 - __builtin_clzl(value)) > 8) {
132 exp++;
133 value >>= 2;
134 }
135
136 /*
137 * Note that it is invalid to write a mantissa with the
138 * upper 2 bits of mantissa being zero, unless the
139 * exponent is also zero.
140 */
141 if (!(value & 0xC0) && exp)
142 result = -1;
143 else
144 result = (exp << 8) | value;
145 }
146 return result;
147 }
148
thresh_cmp_val(u64 value)149 static u64 thresh_cmp_val(u64 value)
150 {
151 if (cpu_has_feature(CPU_FTR_ARCH_31))
152 value = p10_thresh_cmp_val(value);
153
154 /*
155 * Since location of threshold compare bits in MMCRA
156 * is different for p8, using different shift value.
157 */
158 if (cpu_has_feature(CPU_FTR_ARCH_300))
159 return value << p9_MMCRA_THR_CMP_SHIFT;
160 else
161 return value << MMCRA_THR_CMP_SHIFT;
162 }
163
combine_from_event(u64 event)164 static unsigned long combine_from_event(u64 event)
165 {
166 if (cpu_has_feature(CPU_FTR_ARCH_300))
167 return p9_EVENT_COMBINE(event);
168
169 return EVENT_COMBINE(event);
170 }
171
combine_shift(unsigned long pmc)172 static unsigned long combine_shift(unsigned long pmc)
173 {
174 if (cpu_has_feature(CPU_FTR_ARCH_300))
175 return p9_MMCR1_COMBINE_SHIFT(pmc);
176
177 return MMCR1_COMBINE_SHIFT(pmc);
178 }
179
event_is_threshold(u64 event)180 static inline bool event_is_threshold(u64 event)
181 {
182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
183 }
184
is_thresh_cmp_valid(u64 event)185 static bool is_thresh_cmp_valid(u64 event)
186 {
187 unsigned int cmp, exp;
188
189 if (cpu_has_feature(CPU_FTR_ARCH_31))
190 return p10_thresh_cmp_val(event) >= 0;
191
192 /*
193 * Check the mantissa upper two bits are not zero, unless the
194 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
195 */
196
197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
198 exp = cmp >> 7;
199
200 if (exp && (cmp & 0x60) == 0)
201 return false;
202
203 return true;
204 }
205
dc_ic_rld_quad_l1_sel(u64 event)206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
207 {
208 unsigned int cache;
209
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
211 return cache;
212 }
213
isa207_find_source(u64 idx,u32 sub_idx)214 static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
215 {
216 u64 ret = PERF_MEM_NA;
217
218 switch(idx) {
219 case 0:
220 /* Nothing to do */
221 break;
222 case 1:
223 ret = PH(LVL, L1);
224 break;
225 case 2:
226 ret = PH(LVL, L2);
227 break;
228 case 3:
229 ret = PH(LVL, L3);
230 break;
231 case 4:
232 if (sub_idx <= 1)
233 ret = PH(LVL, LOC_RAM);
234 else if (sub_idx > 1 && sub_idx <= 2)
235 ret = PH(LVL, REM_RAM1);
236 else
237 ret = PH(LVL, REM_RAM2);
238 ret |= P(SNOOP, HIT);
239 break;
240 case 5:
241 ret = PH(LVL, REM_CCE1);
242 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
243 ret |= P(SNOOP, HIT);
244 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
245 ret |= P(SNOOP, HITM);
246 break;
247 case 6:
248 ret = PH(LVL, REM_CCE2);
249 if ((sub_idx == 0) || (sub_idx == 2))
250 ret |= P(SNOOP, HIT);
251 else if ((sub_idx == 1) || (sub_idx == 3))
252 ret |= P(SNOOP, HITM);
253 break;
254 case 7:
255 ret = PM(LVL, L1);
256 break;
257 }
258
259 return ret;
260 }
261
isa207_get_mem_data_src(union perf_mem_data_src * dsrc,u32 flags,struct pt_regs * regs)262 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
263 struct pt_regs *regs)
264 {
265 u64 idx;
266 u32 sub_idx;
267 u64 sier;
268 u64 val;
269
270 /* Skip if no SIER support */
271 if (!(flags & PPMU_HAS_SIER)) {
272 dsrc->val = 0;
273 return;
274 }
275
276 sier = mfspr(SPRN_SIER);
277 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
278 if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31)))
279 return;
280
281 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
282 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
283
284 dsrc->val = isa207_find_source(idx, sub_idx);
285 if (val == 7) {
286 u64 mmcra;
287 u32 op_type;
288
289 /*
290 * Type 0b111 denotes either larx or stcx instruction. Use the
291 * MMCRA sampling bits [57:59] along with the type value
292 * to determine the exact instruction type. If the sampling
293 * criteria is neither load or store, set the type as default
294 * to NA.
295 */
296 mmcra = mfspr(SPRN_MMCRA);
297
298 op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
299 switch (op_type) {
300 case 5:
301 dsrc->val |= P(OP, LOAD);
302 break;
303 case 7:
304 dsrc->val |= P(OP, STORE);
305 break;
306 default:
307 dsrc->val |= P(OP, NA);
308 break;
309 }
310 } else {
311 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
312 }
313 }
314
isa207_get_mem_weight(u64 * weight,u64 type)315 void isa207_get_mem_weight(u64 *weight, u64 type)
316 {
317 union perf_sample_weight *weight_fields;
318 u64 weight_lat;
319 u64 mmcra = mfspr(SPRN_MMCRA);
320 u64 exp = MMCRA_THR_CTR_EXP(mmcra);
321 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
322 u64 sier = mfspr(SPRN_SIER);
323 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
324
325 if (cpu_has_feature(CPU_FTR_ARCH_31))
326 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
327
328 if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
329 weight_lat = 0;
330 else
331 weight_lat = mantissa << (2 * exp);
332
333 /*
334 * Use 64 bit weight field (full) if sample type is
335 * WEIGHT.
336 *
337 * if sample type is WEIGHT_STRUCT:
338 * - store memory latency in the lower 32 bits.
339 * - For ISA v3.1, use remaining two 16 bit fields of
340 * perf_sample_weight to store cycle counter values
341 * from sier2.
342 */
343 weight_fields = (union perf_sample_weight *)weight;
344 if (type & PERF_SAMPLE_WEIGHT)
345 weight_fields->full = weight_lat;
346 else {
347 weight_fields->var1_dw = (u32)weight_lat;
348 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
349 weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));
350 weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));
351 }
352 }
353 }
354
isa207_get_constraint(u64 event,unsigned long * maskp,unsigned long * valp,u64 event_config1)355 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
356 {
357 unsigned int unit, pmc, cache, ebb;
358 unsigned long mask, value;
359
360 mask = value = 0;
361
362 if (!is_event_valid(event))
363 return -1;
364
365 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
366 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
367 if (cpu_has_feature(CPU_FTR_ARCH_31))
368 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
369 p10_EVENT_CACHE_SEL_MASK;
370 else
371 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
372 EVENT_CACHE_SEL_MASK;
373 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
374
375 if (pmc) {
376 u64 base_event;
377
378 if (pmc > 6)
379 return -1;
380
381 /* Ignore Linux defined bits when checking event below */
382 base_event = event & ~EVENT_LINUX_MASK;
383
384 if (pmc >= 5 && base_event != 0x500fa &&
385 base_event != 0x600f4)
386 return -1;
387
388 mask |= CNST_PMC_MASK(pmc);
389 value |= CNST_PMC_VAL(pmc);
390
391 /*
392 * PMC5 and PMC6 are used to count cycles and instructions and
393 * they do not support most of the constraint bits. Add a check
394 * to exclude PMC5/6 from most of the constraints except for
395 * EBB/BHRB.
396 */
397 if (pmc >= 5)
398 goto ebb_bhrb;
399 }
400
401 if (pmc <= 4) {
402 /*
403 * Add to number of counters in use. Note this includes events with
404 * a PMC of 0 - they still need a PMC, it's just assigned later.
405 * Don't count events on PMC 5 & 6, there is only one valid event
406 * on each of those counters, and they are handled above.
407 */
408 mask |= CNST_NC_MASK;
409 value |= CNST_NC_VAL;
410 }
411
412 if (unit >= 6 && unit <= 9) {
413 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
414 if (unit == 6) {
415 mask |= CNST_L2L3_GROUP_MASK;
416 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
417 }
418 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
419 mask |= CNST_CACHE_GROUP_MASK;
420 value |= CNST_CACHE_GROUP_VAL(event & 0xff);
421
422 mask |= CNST_CACHE_PMC4_MASK;
423 if (pmc == 4)
424 value |= CNST_CACHE_PMC4_VAL;
425 } else if (cache & 0x7) {
426 /*
427 * L2/L3 events contain a cache selector field, which is
428 * supposed to be programmed into MMCRC. However MMCRC is only
429 * HV writable, and there is no API for guest kernels to modify
430 * it. The solution is for the hypervisor to initialise the
431 * field to zeroes, and for us to only ever allow events that
432 * have a cache selector of zero. The bank selector (bit 3) is
433 * irrelevant, as long as the rest of the value is 0.
434 */
435 return -1;
436 }
437
438 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
439 mask |= CNST_L1_QUAL_MASK;
440 value |= CNST_L1_QUAL_VAL(cache);
441 }
442
443 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
444 mask |= CNST_RADIX_SCOPE_GROUP_MASK;
445 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
446 }
447
448 if (is_event_marked(event)) {
449 mask |= CNST_SAMPLE_MASK;
450 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
451 }
452
453 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
454 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
455 mask |= CNST_THRESH_CTL_SEL_MASK;
456 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
457 mask |= p10_CNST_THRESH_CMP_MASK;
458 value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1));
459 } else if (event_is_threshold(event))
460 return -1;
461 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
462 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
463 mask |= CNST_THRESH_MASK;
464 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
465 } else if (event_is_threshold(event))
466 return -1;
467 } else {
468 /*
469 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
470 * the threshold control bits are used for the match value.
471 */
472 if (event_is_fab_match(event)) {
473 mask |= CNST_FAB_MATCH_MASK;
474 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
475 } else {
476 if (!is_thresh_cmp_valid(event))
477 return -1;
478
479 mask |= CNST_THRESH_MASK;
480 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
481 }
482 }
483
484 ebb_bhrb:
485 if (!pmc && ebb)
486 /* EBB events must specify the PMC */
487 return -1;
488
489 if (event & EVENT_WANTS_BHRB) {
490 if (!ebb)
491 /* Only EBB events can request BHRB */
492 return -1;
493
494 mask |= CNST_IFM_MASK;
495 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
496 }
497
498 /*
499 * All events must agree on EBB, either all request it or none.
500 * EBB events are pinned & exclusive, so this should never actually
501 * hit, but we leave it as a fallback in case.
502 */
503 mask |= CNST_EBB_MASK;
504 value |= CNST_EBB_VAL(ebb);
505
506 *maskp = mask;
507 *valp = value;
508
509 return 0;
510 }
511
isa207_compute_mmcr(u64 event[],int n_ev,unsigned int hwc[],struct mmcr_regs * mmcr,struct perf_event * pevents[],u32 flags)512 int isa207_compute_mmcr(u64 event[], int n_ev,
513 unsigned int hwc[], struct mmcr_regs *mmcr,
514 struct perf_event *pevents[], u32 flags)
515 {
516 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
517 unsigned long mmcr3;
518 unsigned int pmc, pmc_inuse;
519 int i;
520
521 pmc_inuse = 0;
522
523 /* First pass to count resource use */
524 for (i = 0; i < n_ev; ++i) {
525 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
526 if (pmc)
527 pmc_inuse |= 1 << pmc;
528 }
529
530 mmcra = mmcr1 = mmcr2 = mmcr3 = 0;
531
532 /*
533 * Disable bhrb unless explicitly requested
534 * by setting MMCRA (BHRBRD) bit.
535 */
536 if (cpu_has_feature(CPU_FTR_ARCH_31))
537 mmcra |= MMCRA_BHRB_DISABLE;
538
539 /* Second pass: assign PMCs, set all MMCR1 fields */
540 for (i = 0; i < n_ev; ++i) {
541 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
542 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
543 combine = combine_from_event(event[i]);
544 psel = event[i] & EVENT_PSEL_MASK;
545
546 if (!pmc) {
547 for (pmc = 1; pmc <= 4; ++pmc) {
548 if (!(pmc_inuse & (1 << pmc)))
549 break;
550 }
551
552 pmc_inuse |= 1 << pmc;
553 }
554
555 if (pmc <= 4) {
556 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
557 mmcr1 |= combine << combine_shift(pmc);
558 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
559 }
560
561 /* In continuous sampling mode, update SDAR on TLB miss */
562 mmcra_sdar_mode(event[i], &mmcra);
563
564 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
565 cache = dc_ic_rld_quad_l1_sel(event[i]);
566 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
567 } else {
568 if (event[i] & EVENT_IS_L1) {
569 cache = dc_ic_rld_quad_l1_sel(event[i]);
570 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
571 }
572 }
573
574 /* Set RADIX_SCOPE_QUAL bit */
575 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
576 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
577 p10_EVENT_RADIX_SCOPE_QUAL_MASK;
578 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
579 }
580
581 if (is_event_marked(event[i])) {
582 mmcra |= MMCRA_SAMPLE_ENABLE;
583
584 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
585 if (val) {
586 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
587 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
588 }
589 }
590
591 /*
592 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
593 * the threshold bits are used for the match value.
594 */
595 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
596 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
597 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
598 } else {
599 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
600 mmcra |= val << MMCRA_THR_CTL_SHIFT;
601 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
602 mmcra |= val << MMCRA_THR_SEL_SHIFT;
603 if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
604 val = (event[i] >> EVENT_THR_CMP_SHIFT) &
605 EVENT_THR_CMP_MASK;
606 mmcra |= thresh_cmp_val(val);
607 } else if (flags & PPMU_HAS_ATTR_CONFIG1) {
608 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
609 p10_EVENT_THR_CMP_MASK;
610 mmcra |= thresh_cmp_val(val);
611 }
612 }
613
614 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
615 val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
616 p10_EVENT_L2L3_SEL_MASK;
617 mmcr2 |= val << p10_L2L3_SEL_SHIFT;
618 }
619
620 if (event[i] & EVENT_WANTS_BHRB) {
621 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
622 mmcra |= val << MMCRA_IFM_SHIFT;
623 }
624
625 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */
626 if (cpu_has_feature(CPU_FTR_ARCH_31) &&
627 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
628 mmcra &= ~MMCRA_BHRB_DISABLE;
629
630 if (pevents[i]->attr.exclude_user)
631 mmcr2 |= MMCR2_FCP(pmc);
632
633 if (pevents[i]->attr.exclude_hv)
634 mmcr2 |= MMCR2_FCH(pmc);
635
636 if (pevents[i]->attr.exclude_kernel) {
637 if (cpu_has_feature(CPU_FTR_HVMODE))
638 mmcr2 |= MMCR2_FCH(pmc);
639 else
640 mmcr2 |= MMCR2_FCS(pmc);
641 }
642
643 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
644 if (pmc <= 4) {
645 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
646 p10_EVENT_MMCR3_MASK;
647 mmcr3 |= val << MMCR3_SHIFT(pmc);
648 }
649 }
650
651 hwc[i] = pmc - 1;
652 }
653
654 /* Return MMCRx values */
655 mmcr->mmcr0 = 0;
656
657 /* pmc_inuse is 1-based */
658 if (pmc_inuse & 2)
659 mmcr->mmcr0 = MMCR0_PMC1CE;
660
661 if (pmc_inuse & 0x7c)
662 mmcr->mmcr0 |= MMCR0_PMCjCE;
663
664 /* If we're not using PMC 5 or 6, freeze them */
665 if (!(pmc_inuse & 0x60))
666 mmcr->mmcr0 |= MMCR0_FC56;
667
668 /*
669 * Set mmcr0 (PMCCEXT) for p10 which
670 * will restrict access to group B registers
671 * when MMCR0 PMCC=0b00.
672 */
673 if (cpu_has_feature(CPU_FTR_ARCH_31))
674 mmcr->mmcr0 |= MMCR0_PMCCEXT;
675
676 mmcr->mmcr1 = mmcr1;
677 mmcr->mmcra = mmcra;
678 mmcr->mmcr2 = mmcr2;
679 mmcr->mmcr3 = mmcr3;
680
681 return 0;
682 }
683
isa207_disable_pmc(unsigned int pmc,struct mmcr_regs * mmcr)684 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
685 {
686 if (pmc <= 3)
687 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
688 }
689
find_alternative(u64 event,const unsigned int ev_alt[][MAX_ALT],int size)690 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
691 {
692 int i, j;
693
694 for (i = 0; i < size; ++i) {
695 if (event < ev_alt[i][0])
696 break;
697
698 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
699 if (event == ev_alt[i][j])
700 return i;
701 }
702
703 return -1;
704 }
705
isa207_get_alternatives(u64 event,u64 alt[],int size,unsigned int flags,const unsigned int ev_alt[][MAX_ALT])706 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
707 const unsigned int ev_alt[][MAX_ALT])
708 {
709 int i, j, num_alt = 0;
710 u64 alt_event;
711
712 alt[num_alt++] = event;
713 i = find_alternative(event, ev_alt, size);
714 if (i >= 0) {
715 /* Filter out the original event, it's already in alt[0] */
716 for (j = 0; j < MAX_ALT; ++j) {
717 alt_event = ev_alt[i][j];
718 if (alt_event && alt_event != event)
719 alt[num_alt++] = alt_event;
720 }
721 }
722
723 if (flags & PPMU_ONLY_COUNT_RUN) {
724 /*
725 * We're only counting in RUN state, so PM_CYC is equivalent to
726 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
727 */
728 j = num_alt;
729 for (i = 0; i < num_alt; ++i) {
730 switch (alt[i]) {
731 case 0x1e: /* PMC_CYC */
732 alt[j++] = 0x600f4; /* PM_RUN_CYC */
733 break;
734 case 0x600f4:
735 alt[j++] = 0x1e;
736 break;
737 case 0x2: /* PM_INST_CMPL */
738 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
739 break;
740 case 0x500fa:
741 alt[j++] = 0x2;
742 break;
743 }
744 }
745 num_alt = j;
746 }
747
748 return num_alt;
749 }
750
isa3XX_check_attr_config(struct perf_event * ev)751 int isa3XX_check_attr_config(struct perf_event *ev)
752 {
753 u64 val, sample_mode;
754 u64 event = ev->attr.config;
755
756 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
757 sample_mode = val & 0x3;
758
759 /*
760 * MMCRA[61:62] is Random Sampling Mode (SM).
761 * value of 0b11 is reserved.
762 */
763 if (sample_mode == 0x3)
764 return -EINVAL;
765
766 /*
767 * Check for all reserved value
768 * Source: Performance Monitoring Unit User Guide
769 */
770 switch (val) {
771 case 0x5:
772 case 0x9:
773 case 0xD:
774 case 0x19:
775 case 0x1D:
776 case 0x1A:
777 case 0x1E:
778 return -EINVAL;
779 }
780
781 /*
782 * MMCRA[48:51]/[52:55]) Threshold Start/Stop
783 * Events Selection.
784 * 0b11110000/0b00001111 is reserved.
785 */
786 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
787 if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
788 return -EINVAL;
789
790 return 0;
791 }
792