1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 SiFive 4 */ 5 6 #ifndef _ASM_RISCV_INSN_H 7 #define _ASM_RISCV_INSN_H 8 9 #include <linux/bits.h> 10 11 /* The bit field of immediate value in I-type instruction */ 12 #define I_IMM_SIGN_OPOFF 31 13 #define I_IMM_11_0_OPOFF 20 14 #define I_IMM_SIGN_OFF 12 15 #define I_IMM_11_0_OFF 0 16 #define I_IMM_11_0_MASK GENMASK(11, 0) 17 18 /* The bit field of immediate value in J-type instruction */ 19 #define J_IMM_SIGN_OPOFF 31 20 #define J_IMM_10_1_OPOFF 21 21 #define J_IMM_11_OPOFF 20 22 #define J_IMM_19_12_OPOFF 12 23 #define J_IMM_SIGN_OFF 20 24 #define J_IMM_10_1_OFF 1 25 #define J_IMM_11_OFF 11 26 #define J_IMM_19_12_OFF 12 27 #define J_IMM_10_1_MASK GENMASK(9, 0) 28 #define J_IMM_11_MASK GENMASK(0, 0) 29 #define J_IMM_19_12_MASK GENMASK(7, 0) 30 31 /* The bit field of immediate value in B-type instruction */ 32 #define B_IMM_SIGN_OPOFF 31 33 #define B_IMM_10_5_OPOFF 25 34 #define B_IMM_4_1_OPOFF 8 35 #define B_IMM_11_OPOFF 7 36 #define B_IMM_SIGN_OFF 12 37 #define B_IMM_10_5_OFF 5 38 #define B_IMM_4_1_OFF 1 39 #define B_IMM_11_OFF 11 40 #define B_IMM_10_5_MASK GENMASK(5, 0) 41 #define B_IMM_4_1_MASK GENMASK(3, 0) 42 #define B_IMM_11_MASK GENMASK(0, 0) 43 44 /* The register offset in RVG instruction */ 45 #define RVG_RS1_OPOFF 15 46 #define RVG_RS2_OPOFF 20 47 #define RVG_RD_OPOFF 7 48 49 /* The bit field of immediate value in RVC J instruction */ 50 #define RVC_J_IMM_SIGN_OPOFF 12 51 #define RVC_J_IMM_4_OPOFF 11 52 #define RVC_J_IMM_9_8_OPOFF 9 53 #define RVC_J_IMM_10_OPOFF 8 54 #define RVC_J_IMM_6_OPOFF 7 55 #define RVC_J_IMM_7_OPOFF 6 56 #define RVC_J_IMM_3_1_OPOFF 3 57 #define RVC_J_IMM_5_OPOFF 2 58 #define RVC_J_IMM_SIGN_OFF 11 59 #define RVC_J_IMM_4_OFF 4 60 #define RVC_J_IMM_9_8_OFF 8 61 #define RVC_J_IMM_10_OFF 10 62 #define RVC_J_IMM_6_OFF 6 63 #define RVC_J_IMM_7_OFF 7 64 #define RVC_J_IMM_3_1_OFF 1 65 #define RVC_J_IMM_5_OFF 5 66 #define RVC_J_IMM_4_MASK GENMASK(0, 0) 67 #define RVC_J_IMM_9_8_MASK GENMASK(1, 0) 68 #define RVC_J_IMM_10_MASK GENMASK(0, 0) 69 #define RVC_J_IMM_6_MASK GENMASK(0, 0) 70 #define RVC_J_IMM_7_MASK GENMASK(0, 0) 71 #define RVC_J_IMM_3_1_MASK GENMASK(2, 0) 72 #define RVC_J_IMM_5_MASK GENMASK(0, 0) 73 74 /* The bit field of immediate value in RVC B instruction */ 75 #define RVC_B_IMM_SIGN_OPOFF 12 76 #define RVC_B_IMM_4_3_OPOFF 10 77 #define RVC_B_IMM_7_6_OPOFF 5 78 #define RVC_B_IMM_2_1_OPOFF 3 79 #define RVC_B_IMM_5_OPOFF 2 80 #define RVC_B_IMM_SIGN_OFF 8 81 #define RVC_B_IMM_4_3_OFF 3 82 #define RVC_B_IMM_7_6_OFF 6 83 #define RVC_B_IMM_2_1_OFF 1 84 #define RVC_B_IMM_5_OFF 5 85 #define RVC_B_IMM_4_3_MASK GENMASK(1, 0) 86 #define RVC_B_IMM_7_6_MASK GENMASK(1, 0) 87 #define RVC_B_IMM_2_1_MASK GENMASK(1, 0) 88 #define RVC_B_IMM_5_MASK GENMASK(0, 0) 89 90 /* The register offset in RVC op=C0 instruction */ 91 #define RVC_C0_RS1_OPOFF 7 92 #define RVC_C0_RS2_OPOFF 2 93 #define RVC_C0_RD_OPOFF 2 94 95 /* The register offset in RVC op=C1 instruction */ 96 #define RVC_C1_RS1_OPOFF 7 97 #define RVC_C1_RS2_OPOFF 2 98 #define RVC_C1_RD_OPOFF 7 99 100 /* The register offset in RVC op=C2 instruction */ 101 #define RVC_C2_RS1_OPOFF 7 102 #define RVC_C2_RS2_OPOFF 2 103 #define RVC_C2_RD_OPOFF 7 104 105 /* parts of opcode for RVG*/ 106 #define OPCODE_BRANCH 0x63 107 #define OPCODE_JALR 0x67 108 #define OPCODE_JAL 0x6f 109 #define OPCODE_SYSTEM 0x73 110 111 /* parts of opcode for RVC*/ 112 #define OPCODE_C_0 0x0 113 #define OPCODE_C_1 0x1 114 #define OPCODE_C_2 0x2 115 116 /* parts of funct3 code for I, M, A extension*/ 117 #define FUNCT3_JALR 0x0 118 #define FUNCT3_BEQ 0x0 119 #define FUNCT3_BNE 0x1000 120 #define FUNCT3_BLT 0x4000 121 #define FUNCT3_BGE 0x5000 122 #define FUNCT3_BLTU 0x6000 123 #define FUNCT3_BGEU 0x7000 124 125 /* parts of funct3 code for C extension*/ 126 #define FUNCT3_C_BEQZ 0xc000 127 #define FUNCT3_C_BNEZ 0xe000 128 #define FUNCT3_C_J 0xa000 129 #define FUNCT3_C_JAL 0x2000 130 #define FUNCT4_C_JR 0x8000 131 #define FUNCT4_C_JALR 0x9000 132 133 #define FUNCT12_SRET 0x10200000 134 135 #define MATCH_JALR (FUNCT3_JALR | OPCODE_JALR) 136 #define MATCH_JAL (OPCODE_JAL) 137 #define MATCH_BEQ (FUNCT3_BEQ | OPCODE_BRANCH) 138 #define MATCH_BNE (FUNCT3_BNE | OPCODE_BRANCH) 139 #define MATCH_BLT (FUNCT3_BLT | OPCODE_BRANCH) 140 #define MATCH_BGE (FUNCT3_BGE | OPCODE_BRANCH) 141 #define MATCH_BLTU (FUNCT3_BLTU | OPCODE_BRANCH) 142 #define MATCH_BGEU (FUNCT3_BGEU | OPCODE_BRANCH) 143 #define MATCH_SRET (FUNCT12_SRET | OPCODE_SYSTEM) 144 #define MATCH_C_BEQZ (FUNCT3_C_BEQZ | OPCODE_C_1) 145 #define MATCH_C_BNEZ (FUNCT3_C_BNEZ | OPCODE_C_1) 146 #define MATCH_C_J (FUNCT3_C_J | OPCODE_C_1) 147 #define MATCH_C_JAL (FUNCT3_C_JAL | OPCODE_C_1) 148 #define MATCH_C_JR (FUNCT4_C_JR | OPCODE_C_2) 149 #define MATCH_C_JALR (FUNCT4_C_JALR | OPCODE_C_2) 150 151 #define MASK_JALR 0x707f 152 #define MASK_JAL 0x7f 153 #define MASK_C_JALR 0xf07f 154 #define MASK_C_JR 0xf07f 155 #define MASK_C_JAL 0xe003 156 #define MASK_C_J 0xe003 157 #define MASK_BEQ 0x707f 158 #define MASK_BNE 0x707f 159 #define MASK_BLT 0x707f 160 #define MASK_BGE 0x707f 161 #define MASK_BLTU 0x707f 162 #define MASK_BGEU 0x707f 163 #define MASK_C_BEQZ 0xe003 164 #define MASK_C_BNEZ 0xe003 165 #define MASK_SRET 0xffffffff 166 167 #define __INSN_LENGTH_MASK _UL(0x3) 168 #define __INSN_LENGTH_GE_32 _UL(0x3) 169 #define __INSN_OPCODE_MASK _UL(0x7F) 170 #define __INSN_BRANCH_OPCODE _UL(OPCODE_BRANCH) 171 172 /* Define a series of is_XXX_insn functions to check if the value INSN 173 * is an instance of instruction XXX. 174 */ 175 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ 176 static inline bool is_ ## INSN_NAME ## _insn(long insn) \ 177 { \ 178 return (insn & (INSN_MASK)) == (INSN_MATCH); \ 179 } 180 181 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 182 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) 183 #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) 184 #define RVC_X(X, s, mask) RV_X(X, s, mask) 185 186 #define EXTRACT_JTYPE_IMM(x) \ 187 ({typeof(x) x_ = (x); \ 188 (RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \ 189 (RV_X(x_, J_IMM_11_OPOFF, J_IMM_11_MASK) << J_IMM_11_OFF) | \ 190 (RV_X(x_, J_IMM_19_12_OPOFF, J_IMM_19_12_MASK) << J_IMM_19_12_OFF) | \ 191 (RV_IMM_SIGN(x_) << J_IMM_SIGN_OFF); }) 192 193 #define EXTRACT_ITYPE_IMM(x) \ 194 ({typeof(x) x_ = (x); \ 195 (RV_X(x_, I_IMM_11_0_OPOFF, I_IMM_11_0_MASK)) | \ 196 (RV_IMM_SIGN(x_) << I_IMM_SIGN_OFF); }) 197 198 #define EXTRACT_BTYPE_IMM(x) \ 199 ({typeof(x) x_ = (x); \ 200 (RV_X(x_, B_IMM_4_1_OPOFF, B_IMM_4_1_MASK) << B_IMM_4_1_OFF) | \ 201 (RV_X(x_, B_IMM_10_5_OPOFF, B_IMM_10_5_MASK) << B_IMM_10_5_OFF) | \ 202 (RV_X(x_, B_IMM_11_OPOFF, B_IMM_11_MASK) << B_IMM_11_OFF) | \ 203 (RV_IMM_SIGN(x_) << B_IMM_SIGN_OFF); }) 204 205 #define EXTRACT_RVC_J_IMM(x) \ 206 ({typeof(x) x_ = (x); \ 207 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \ 208 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \ 209 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \ 210 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \ 211 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \ 212 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \ 213 (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \ 214 (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); }) 215 216 #define EXTRACT_RVC_B_IMM(x) \ 217 ({typeof(x) x_ = (x); \ 218 (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \ 219 (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \ 220 (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \ 221 (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ 222 (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) 223 224 #endif /* _ASM_RISCV_INSN_H */ 225