1 #include <linux/efi.h>
2 #include <asm/e820/types.h>
3 #include <asm/processor.h>
4 #include <asm/efi.h>
5 #include "pgtable.h"
6 #include "../string.h"
7
8 #define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
9 #define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
10
11 #ifdef CONFIG_X86_5LEVEL
12 /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */
13 unsigned int __section(".data") __pgtable_l5_enabled;
14 unsigned int __section(".data") pgdir_shift = 39;
15 unsigned int __section(".data") ptrs_per_p4d = 1;
16 #endif
17
18 struct paging_config {
19 unsigned long trampoline_start;
20 unsigned long l5_required;
21 };
22
23 /* Buffer to preserve trampoline memory */
24 static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
25
26 /*
27 * Trampoline address will be printed by extract_kernel() for debugging
28 * purposes.
29 *
30 * Avoid putting the pointer into .bss as it will be cleared between
31 * paging_prepare() and extract_kernel().
32 */
33 unsigned long *trampoline_32bit __section(".data");
34
35 extern struct boot_params *boot_params;
36 int cmdline_find_option_bool(const char *option);
37
find_trampoline_placement(void)38 static unsigned long find_trampoline_placement(void)
39 {
40 unsigned long bios_start = 0, ebda_start = 0;
41 struct boot_e820_entry *entry;
42 char *signature;
43 int i;
44
45 /*
46 * Find a suitable spot for the trampoline.
47 * This code is based on reserve_bios_regions().
48 */
49
50 /*
51 * EFI systems may not provide legacy ROM. The memory may not be mapped
52 * at all.
53 *
54 * Only look for values in the legacy ROM for non-EFI system.
55 */
56 signature = (char *)&boot_params->efi_info.efi_loader_signature;
57 if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) &&
58 strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) {
59 ebda_start = *(unsigned short *)0x40e << 4;
60 bios_start = *(unsigned short *)0x413 << 10;
61 }
62
63 if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX)
64 bios_start = BIOS_START_MAX;
65
66 if (ebda_start > BIOS_START_MIN && ebda_start < bios_start)
67 bios_start = ebda_start;
68
69 bios_start = round_down(bios_start, PAGE_SIZE);
70
71 /* Find the first usable memory region under bios_start. */
72 for (i = boot_params->e820_entries - 1; i >= 0; i--) {
73 unsigned long new = bios_start;
74
75 entry = &boot_params->e820_table[i];
76
77 /* Skip all entries above bios_start. */
78 if (bios_start <= entry->addr)
79 continue;
80
81 /* Skip non-RAM entries. */
82 if (entry->type != E820_TYPE_RAM)
83 continue;
84
85 /* Adjust bios_start to the end of the entry if needed. */
86 if (bios_start > entry->addr + entry->size)
87 new = entry->addr + entry->size;
88
89 /* Keep bios_start page-aligned. */
90 new = round_down(new, PAGE_SIZE);
91
92 /* Skip the entry if it's too small. */
93 if (new - TRAMPOLINE_32BIT_SIZE < entry->addr)
94 continue;
95
96 /* Protect against underflow. */
97 if (new - TRAMPOLINE_32BIT_SIZE > bios_start)
98 break;
99
100 bios_start = new;
101 break;
102 }
103
104 /* Place the trampoline just below the end of low memory */
105 return bios_start - TRAMPOLINE_32BIT_SIZE;
106 }
107
paging_prepare(void * rmode)108 struct paging_config paging_prepare(void *rmode)
109 {
110 struct paging_config paging_config = {};
111
112 /* Initialize boot_params. Required for cmdline_find_option_bool(). */
113 boot_params = rmode;
114
115 /*
116 * Check if LA57 is desired and supported.
117 *
118 * There are several parts to the check:
119 * - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
120 * - if user asked to disable 5-level paging: no5lvl in cmdline
121 * - if the machine supports 5-level paging:
122 * + CPUID leaf 7 is supported
123 * + the leaf has the feature bit set
124 *
125 * That's substitute for boot_cpu_has() in early boot code.
126 */
127 if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
128 !cmdline_find_option_bool("no5lvl") &&
129 native_cpuid_eax(0) >= 7 &&
130 (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
131 paging_config.l5_required = 1;
132 }
133
134 paging_config.trampoline_start = find_trampoline_placement();
135
136 trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
137
138 /* Preserve trampoline memory */
139 memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
140
141 /* Clear trampoline memory first */
142 memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
143
144 /* Copy trampoline code in place */
145 memcpy(trampoline_32bit + TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
146 &trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
147
148 /*
149 * The code below prepares page table in trampoline memory.
150 *
151 * The new page table will be used by trampoline code for switching
152 * from 4- to 5-level paging or vice versa.
153 *
154 * If switching is not required, the page table is unused: trampoline
155 * code wouldn't touch CR3.
156 */
157
158 /*
159 * We are not going to use the page table in trampoline memory if we
160 * are already in the desired paging mode.
161 */
162 if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
163 goto out;
164
165 if (paging_config.l5_required) {
166 /*
167 * For 4- to 5-level paging transition, set up current CR3 as
168 * the first and the only entry in a new top-level page table.
169 */
170 trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC;
171 } else {
172 unsigned long src;
173
174 /*
175 * For 5- to 4-level paging transition, copy page table pointed
176 * by first entry in the current top-level page table as our
177 * new top-level page table.
178 *
179 * We cannot just point to the page table from trampoline as it
180 * may be above 4G.
181 */
182 src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;
183 memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long),
184 (void *)src, PAGE_SIZE);
185 }
186
187 out:
188 return paging_config;
189 }
190
cleanup_trampoline(void * pgtable)191 void cleanup_trampoline(void *pgtable)
192 {
193 void *trampoline_pgtable;
194
195 trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long);
196
197 /*
198 * Move the top level page table out of trampoline memory,
199 * if it's there.
200 */
201 if ((void *)__native_read_cr3() == trampoline_pgtable) {
202 memcpy(pgtable, trampoline_pgtable, PAGE_SIZE);
203 native_write_cr3((unsigned long)pgtable);
204 }
205
206 /* Restore trampoline memory */
207 memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE);
208
209 /* Initialize variables for 5-level paging */
210 #ifdef CONFIG_X86_5LEVEL
211 if (__read_cr4() & X86_CR4_LA57) {
212 __pgtable_l5_enabled = 1;
213 pgdir_shift = 48;
214 ptrs_per_p4d = 512;
215 }
216 #endif
217 }
218