1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * KVM PMU support for Intel CPUs
4 *
5 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
6 *
7 * Authors:
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
10 */
11 #include <linux/types.h>
12 #include <linux/kvm_host.h>
13 #include <linux/perf_event.h>
14 #include <asm/perf_event.h>
15 #include "x86.h"
16 #include "cpuid.h"
17 #include "lapic.h"
18 #include "nested.h"
19 #include "pmu.h"
20
21 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0)
22
23 static struct kvm_event_hw_type_mapping intel_arch_events[] = {
24 /* Index must match CPUID 0x0A.EBX bit vector */
25 [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
26 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
27 [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
28 [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
29 [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
30 [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
31 [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
32 [7] = { 0x00, 0x03, PERF_COUNT_HW_REF_CPU_CYCLES },
33 };
34
35 /* mapping between fixed pmc index and intel_arch_events array */
36 static int fixed_pmc_events[] = {1, 0, 7};
37
reprogram_fixed_counters(struct kvm_pmu * pmu,u64 data)38 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
39 {
40 int i;
41
42 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
43 u8 new_ctrl = fixed_ctrl_field(data, i);
44 u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
45 struct kvm_pmc *pmc;
46
47 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
48
49 if (old_ctrl == new_ctrl)
50 continue;
51
52 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use);
53 reprogram_fixed_counter(pmc, new_ctrl, i);
54 }
55
56 pmu->fixed_ctr_ctrl = data;
57 }
58
59 /* function is called when global control register has been updated. */
global_ctrl_changed(struct kvm_pmu * pmu,u64 data)60 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
61 {
62 int bit;
63 u64 diff = pmu->global_ctrl ^ data;
64
65 pmu->global_ctrl = data;
66
67 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
68 reprogram_counter(pmu, bit);
69 }
70
intel_pmc_perf_hw_id(struct kvm_pmc * pmc)71 static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc)
72 {
73 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
74 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
75 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
76 int i;
77
78 for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++)
79 if (intel_arch_events[i].eventsel == event_select
80 && intel_arch_events[i].unit_mask == unit_mask
81 && (pmu->available_event_types & (1 << i)))
82 break;
83
84 if (i == ARRAY_SIZE(intel_arch_events))
85 return PERF_COUNT_HW_MAX;
86
87 return intel_arch_events[i].event_type;
88 }
89
intel_find_fixed_event(int idx)90 static unsigned intel_find_fixed_event(int idx)
91 {
92 u32 event;
93 size_t size = ARRAY_SIZE(fixed_pmc_events);
94
95 if (idx >= size)
96 return PERF_COUNT_HW_MAX;
97
98 event = fixed_pmc_events[array_index_nospec(idx, size)];
99 return intel_arch_events[event].event_type;
100 }
101
102 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
intel_pmc_is_enabled(struct kvm_pmc * pmc)103 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
104 {
105 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
106
107 if (!intel_pmu_has_perf_global_ctrl(pmu))
108 return true;
109
110 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
111 }
112
intel_pmc_idx_to_pmc(struct kvm_pmu * pmu,int pmc_idx)113 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
114 {
115 if (pmc_idx < INTEL_PMC_IDX_FIXED)
116 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
117 MSR_P6_EVNTSEL0);
118 else {
119 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
120
121 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
122 }
123 }
124
125 /* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
intel_is_valid_rdpmc_ecx(struct kvm_vcpu * vcpu,unsigned int idx)126 static int intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
127 {
128 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
129 bool fixed = idx & (1u << 30);
130
131 idx &= ~(3u << 30);
132
133 return (!fixed && idx >= pmu->nr_arch_gp_counters) ||
134 (fixed && idx >= pmu->nr_arch_fixed_counters);
135 }
136
intel_rdpmc_ecx_to_pmc(struct kvm_vcpu * vcpu,unsigned int idx,u64 * mask)137 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
138 unsigned int idx, u64 *mask)
139 {
140 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
141 bool fixed = idx & (1u << 30);
142 struct kvm_pmc *counters;
143 unsigned int num_counters;
144
145 idx &= ~(3u << 30);
146 if (fixed) {
147 counters = pmu->fixed_counters;
148 num_counters = pmu->nr_arch_fixed_counters;
149 } else {
150 counters = pmu->gp_counters;
151 num_counters = pmu->nr_arch_gp_counters;
152 }
153 if (idx >= num_counters)
154 return NULL;
155 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
156 return &counters[array_index_nospec(idx, num_counters)];
157 }
158
vcpu_get_perf_capabilities(struct kvm_vcpu * vcpu)159 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu)
160 {
161 if (!guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
162 return 0;
163
164 return vcpu->arch.perf_capabilities;
165 }
166
fw_writes_is_enabled(struct kvm_vcpu * vcpu)167 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu)
168 {
169 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0;
170 }
171
get_fw_gp_pmc(struct kvm_pmu * pmu,u32 msr)172 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
173 {
174 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu)))
175 return NULL;
176
177 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);
178 }
179
intel_pmu_lbr_is_compatible(struct kvm_vcpu * vcpu)180 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu)
181 {
182 /*
183 * As a first step, a guest could only enable LBR feature if its
184 * cpu model is the same as the host because the LBR registers
185 * would be pass-through to the guest and they're model specific.
186 */
187 return boot_cpu_data.x86_model == guest_cpuid_model(vcpu);
188 }
189
intel_pmu_lbr_is_enabled(struct kvm_vcpu * vcpu)190 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu)
191 {
192 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu);
193
194 return lbr->nr && (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_LBR_FMT);
195 }
196
intel_pmu_is_valid_lbr_msr(struct kvm_vcpu * vcpu,u32 index)197 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
198 {
199 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu);
200 bool ret = false;
201
202 if (!intel_pmu_lbr_is_enabled(vcpu))
203 return ret;
204
205 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) ||
206 (index >= records->from && index < records->from + records->nr) ||
207 (index >= records->to && index < records->to + records->nr);
208
209 if (!ret && records->info)
210 ret = (index >= records->info && index < records->info + records->nr);
211
212 return ret;
213 }
214
intel_is_valid_msr(struct kvm_vcpu * vcpu,u32 msr)215 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
216 {
217 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
218 int ret;
219
220 switch (msr) {
221 case MSR_CORE_PERF_FIXED_CTR_CTRL:
222 case MSR_CORE_PERF_GLOBAL_STATUS:
223 case MSR_CORE_PERF_GLOBAL_CTRL:
224 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
225 return intel_pmu_has_perf_global_ctrl(pmu);
226 break;
227 default:
228 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
229 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
230 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) ||
231 intel_pmu_is_valid_lbr_msr(vcpu, msr);
232 break;
233 }
234
235 return ret;
236 }
237
intel_msr_idx_to_pmc(struct kvm_vcpu * vcpu,u32 msr)238 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
239 {
240 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
241 struct kvm_pmc *pmc;
242
243 pmc = get_fixed_pmc(pmu, msr);
244 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);
245 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);
246
247 return pmc;
248 }
249
intel_pmu_release_guest_lbr_event(struct kvm_vcpu * vcpu)250 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu)
251 {
252 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
253
254 if (lbr_desc->event) {
255 perf_event_release_kernel(lbr_desc->event);
256 lbr_desc->event = NULL;
257 vcpu_to_pmu(vcpu)->event_count--;
258 }
259 }
260
intel_pmu_create_guest_lbr_event(struct kvm_vcpu * vcpu)261 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu)
262 {
263 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
264 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
265 struct perf_event *event;
266
267 /*
268 * The perf_event_attr is constructed in the minimum efficient way:
269 * - set 'pinned = true' to make it task pinned so that if another
270 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1;
271 * - set '.exclude_host = true' to record guest branches behavior;
272 *
273 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf
274 * schedule the event without a real HW counter but a fake one;
275 * check is_guest_lbr_event() and __intel_get_event_constraints();
276 *
277 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and
278 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
279 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack
280 * event, which helps KVM to save/restore guest LBR records
281 * during host context switches and reduces quite a lot overhead,
282 * check branch_user_callstack() and intel_pmu_lbr_sched_task();
283 */
284 struct perf_event_attr attr = {
285 .type = PERF_TYPE_RAW,
286 .size = sizeof(attr),
287 .config = INTEL_FIXED_VLBR_EVENT,
288 .sample_type = PERF_SAMPLE_BRANCH_STACK,
289 .pinned = true,
290 .exclude_host = true,
291 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
292 PERF_SAMPLE_BRANCH_USER,
293 };
294
295 if (unlikely(lbr_desc->event)) {
296 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
297 return 0;
298 }
299
300 event = perf_event_create_kernel_counter(&attr, -1,
301 current, NULL, NULL);
302 if (IS_ERR(event)) {
303 pr_debug_ratelimited("%s: failed %ld\n",
304 __func__, PTR_ERR(event));
305 return PTR_ERR(event);
306 }
307 lbr_desc->event = event;
308 pmu->event_count++;
309 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
310 return 0;
311 }
312
313 /*
314 * It's safe to access LBR msrs from guest when they have not
315 * been passthrough since the host would help restore or reset
316 * the LBR msrs records when the guest LBR event is scheduled in.
317 */
intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu * vcpu,struct msr_data * msr_info,bool read)318 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
319 struct msr_data *msr_info, bool read)
320 {
321 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
322 u32 index = msr_info->index;
323
324 if (!intel_pmu_is_valid_lbr_msr(vcpu, index))
325 return false;
326
327 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
328 goto dummy;
329
330 /*
331 * Disable irq to ensure the LBR feature doesn't get reclaimed by the
332 * host at the time the value is read from the msr, and this avoids the
333 * host LBR value to be leaked to the guest. If LBR has been reclaimed,
334 * return 0 on guest reads.
335 */
336 local_irq_disable();
337 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) {
338 if (read)
339 rdmsrl(index, msr_info->data);
340 else
341 wrmsrl(index, msr_info->data);
342 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
343 local_irq_enable();
344 return true;
345 }
346 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
347 local_irq_enable();
348
349 dummy:
350 if (read)
351 msr_info->data = 0;
352 return true;
353 }
354
intel_pmu_get_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)355 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
356 {
357 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
358 struct kvm_pmc *pmc;
359 u32 msr = msr_info->index;
360
361 switch (msr) {
362 case MSR_CORE_PERF_FIXED_CTR_CTRL:
363 msr_info->data = pmu->fixed_ctr_ctrl;
364 return 0;
365 case MSR_CORE_PERF_GLOBAL_STATUS:
366 msr_info->data = pmu->global_status;
367 return 0;
368 case MSR_CORE_PERF_GLOBAL_CTRL:
369 msr_info->data = pmu->global_ctrl;
370 return 0;
371 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
372 msr_info->data = pmu->global_ovf_ctrl;
373 return 0;
374 default:
375 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
376 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
377 u64 val = pmc_read_counter(pmc);
378 msr_info->data =
379 val & pmu->counter_bitmask[KVM_PMC_GP];
380 return 0;
381 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
382 u64 val = pmc_read_counter(pmc);
383 msr_info->data =
384 val & pmu->counter_bitmask[KVM_PMC_FIXED];
385 return 0;
386 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
387 msr_info->data = pmc->eventsel;
388 return 0;
389 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true))
390 return 0;
391 }
392
393 return 1;
394 }
395
intel_pmu_set_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)396 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
397 {
398 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
399 struct kvm_pmc *pmc;
400 u32 msr = msr_info->index;
401 u64 data = msr_info->data;
402 u64 reserved_bits;
403
404 switch (msr) {
405 case MSR_CORE_PERF_FIXED_CTR_CTRL:
406 if (pmu->fixed_ctr_ctrl == data)
407 return 0;
408 if (!(data & pmu->fixed_ctr_ctrl_mask)) {
409 reprogram_fixed_counters(pmu, data);
410 return 0;
411 }
412 break;
413 case MSR_CORE_PERF_GLOBAL_STATUS:
414 if (msr_info->host_initiated) {
415 pmu->global_status = data;
416 return 0;
417 }
418 break; /* RO MSR */
419 case MSR_CORE_PERF_GLOBAL_CTRL:
420 if (pmu->global_ctrl == data)
421 return 0;
422 if (kvm_valid_perf_global_ctrl(pmu, data)) {
423 global_ctrl_changed(pmu, data);
424 return 0;
425 }
426 break;
427 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
428 if (!(data & pmu->global_ovf_ctrl_mask)) {
429 if (!msr_info->host_initiated)
430 pmu->global_status &= ~data;
431 pmu->global_ovf_ctrl = data;
432 return 0;
433 }
434 break;
435 default:
436 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
437 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
438 if ((msr & MSR_PMC_FULL_WIDTH_BIT) &&
439 (data & ~pmu->counter_bitmask[KVM_PMC_GP]))
440 return 1;
441 if (!msr_info->host_initiated &&
442 !(msr & MSR_PMC_FULL_WIDTH_BIT))
443 data = (s64)(s32)data;
444 pmc->counter += data - pmc_read_counter(pmc);
445 pmc_update_sample_period(pmc);
446 return 0;
447 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
448 pmc->counter += data - pmc_read_counter(pmc);
449 pmc_update_sample_period(pmc);
450 return 0;
451 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
452 if (data == pmc->eventsel)
453 return 0;
454 reserved_bits = pmu->reserved_bits;
455 if ((pmc->idx == 2) &&
456 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED))
457 reserved_bits ^= HSW_IN_TX_CHECKPOINTED;
458 if (!(data & reserved_bits)) {
459 reprogram_gp_counter(pmc, data);
460 return 0;
461 }
462 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false))
463 return 0;
464 }
465
466 return 1;
467 }
468
intel_pmu_refresh(struct kvm_vcpu * vcpu)469 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
470 {
471 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
472 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
473
474 struct x86_pmu_capability x86_pmu;
475 struct kvm_cpuid_entry2 *entry;
476 union cpuid10_eax eax;
477 union cpuid10_edx edx;
478 int i;
479
480 pmu->nr_arch_gp_counters = 0;
481 pmu->nr_arch_fixed_counters = 0;
482 pmu->counter_bitmask[KVM_PMC_GP] = 0;
483 pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
484 pmu->version = 0;
485 pmu->reserved_bits = 0xffffffff00200000ull;
486 pmu->raw_event_mask = X86_RAW_EVENT_MASK;
487 pmu->global_ctrl_mask = ~0ull;
488 pmu->global_ovf_ctrl_mask = ~0ull;
489 pmu->fixed_ctr_ctrl_mask = ~0ull;
490
491 entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
492 if (!entry)
493 return;
494 eax.full = entry->eax;
495 edx.full = entry->edx;
496
497 pmu->version = eax.split.version_id;
498 if (!pmu->version)
499 return;
500
501 perf_get_x86_pmu_capability(&x86_pmu);
502
503 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
504 x86_pmu.num_counters_gp);
505 eax.split.bit_width = min_t(int, eax.split.bit_width, x86_pmu.bit_width_gp);
506 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
507 eax.split.mask_length = min_t(int, eax.split.mask_length, x86_pmu.events_mask_len);
508 pmu->available_event_types = ~entry->ebx &
509 ((1ull << eax.split.mask_length) - 1);
510
511 if (pmu->version == 1) {
512 pmu->nr_arch_fixed_counters = 0;
513 } else {
514 pmu->nr_arch_fixed_counters =
515 min_t(int, edx.split.num_counters_fixed,
516 x86_pmu.num_counters_fixed);
517 edx.split.bit_width_fixed = min_t(int,
518 edx.split.bit_width_fixed, x86_pmu.bit_width_fixed);
519 pmu->counter_bitmask[KVM_PMC_FIXED] =
520 ((u64)1 << edx.split.bit_width_fixed) - 1;
521 }
522
523 for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
524 pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4));
525 pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
526 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
527 pmu->global_ctrl_mask = ~pmu->global_ctrl;
528 pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
529 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
530 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
531 if (vmx_pt_mode_is_host_guest())
532 pmu->global_ovf_ctrl_mask &=
533 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
534
535 entry = kvm_find_cpuid_entry(vcpu, 7, 0);
536 if (entry &&
537 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
538 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) {
539 pmu->reserved_bits ^= HSW_IN_TX;
540 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
541 }
542
543 bitmap_set(pmu->all_valid_pmc_idx,
544 0, pmu->nr_arch_gp_counters);
545 bitmap_set(pmu->all_valid_pmc_idx,
546 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
547
548 nested_vmx_pmu_entry_exit_ctls_update(vcpu);
549
550 if (intel_pmu_lbr_is_compatible(vcpu))
551 x86_perf_get_lbr(&lbr_desc->records);
552 else
553 lbr_desc->records.nr = 0;
554
555 if (lbr_desc->records.nr)
556 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
557 }
558
intel_pmu_init(struct kvm_vcpu * vcpu)559 static void intel_pmu_init(struct kvm_vcpu *vcpu)
560 {
561 int i;
562 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
563 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
564
565 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
566 pmu->gp_counters[i].type = KVM_PMC_GP;
567 pmu->gp_counters[i].vcpu = vcpu;
568 pmu->gp_counters[i].idx = i;
569 pmu->gp_counters[i].current_config = 0;
570 }
571
572 for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
573 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
574 pmu->fixed_counters[i].vcpu = vcpu;
575 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
576 pmu->fixed_counters[i].current_config = 0;
577 }
578
579 vcpu->arch.perf_capabilities = vmx_get_perf_capabilities();
580 lbr_desc->records.nr = 0;
581 lbr_desc->event = NULL;
582 lbr_desc->msr_passthrough = false;
583 }
584
intel_pmu_reset(struct kvm_vcpu * vcpu)585 static void intel_pmu_reset(struct kvm_vcpu *vcpu)
586 {
587 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
588 struct kvm_pmc *pmc = NULL;
589 int i;
590
591 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
592 pmc = &pmu->gp_counters[i];
593
594 pmc_stop_counter(pmc);
595 pmc->counter = pmc->eventsel = 0;
596 }
597
598 for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
599 pmc = &pmu->fixed_counters[i];
600
601 pmc_stop_counter(pmc);
602 pmc->counter = 0;
603 }
604
605 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
606 pmu->global_ovf_ctrl = 0;
607
608 intel_pmu_release_guest_lbr_event(vcpu);
609 }
610
611 /*
612 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4.
613 *
614 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and
615 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL.
616 *
617 * Guest needs to re-enable LBR to resume branches recording.
618 */
intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu * vcpu)619 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu)
620 {
621 u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL);
622
623 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) {
624 data &= ~DEBUGCTLMSR_LBR;
625 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
626 }
627 }
628
intel_pmu_deliver_pmi(struct kvm_vcpu * vcpu)629 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
630 {
631 u8 version = vcpu_to_pmu(vcpu)->version;
632
633 if (!intel_pmu_lbr_is_enabled(vcpu))
634 return;
635
636 if (version > 1 && version < 4)
637 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu);
638 }
639
vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu * vcpu,bool set)640 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set)
641 {
642 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu);
643 int i;
644
645 for (i = 0; i < lbr->nr; i++) {
646 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);
647 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);
648 if (lbr->info)
649 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);
650 }
651
652 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);
653 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);
654 }
655
vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)656 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
657 {
658 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
659
660 if (!lbr_desc->msr_passthrough)
661 return;
662
663 vmx_update_intercept_for_lbr_msrs(vcpu, true);
664 lbr_desc->msr_passthrough = false;
665 }
666
vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)667 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
668 {
669 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
670
671 if (lbr_desc->msr_passthrough)
672 return;
673
674 vmx_update_intercept_for_lbr_msrs(vcpu, false);
675 lbr_desc->msr_passthrough = true;
676 }
677
678 /*
679 * Higher priority host perf events (e.g. cpu pinned) could reclaim the
680 * pmu resources (e.g. LBR) that were assigned to the guest. This is
681 * usually done via ipi calls (more details in perf_install_in_context).
682 *
683 * Before entering the non-root mode (with irq disabled here), double
684 * confirm that the pmu features enabled to the guest are not reclaimed
685 * by higher priority host events. Otherwise, disallow vcpu's access to
686 * the reclaimed features.
687 */
vmx_passthrough_lbr_msrs(struct kvm_vcpu * vcpu)688 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
689 {
690 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
691 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
692
693 if (!lbr_desc->event) {
694 vmx_disable_lbr_msrs_passthrough(vcpu);
695 if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)
696 goto warn;
697 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use))
698 goto warn;
699 return;
700 }
701
702 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
703 vmx_disable_lbr_msrs_passthrough(vcpu);
704 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
705 goto warn;
706 } else
707 vmx_enable_lbr_msrs_passthrough(vcpu);
708
709 return;
710
711 warn:
712 pr_warn_ratelimited("kvm: vcpu-%d: fail to passthrough LBR.\n",
713 vcpu->vcpu_id);
714 }
715
intel_pmu_cleanup(struct kvm_vcpu * vcpu)716 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
717 {
718 if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR))
719 intel_pmu_release_guest_lbr_event(vcpu);
720 }
721
722 struct kvm_pmu_ops intel_pmu_ops = {
723 .pmc_perf_hw_id = intel_pmc_perf_hw_id,
724 .find_fixed_event = intel_find_fixed_event,
725 .pmc_is_enabled = intel_pmc_is_enabled,
726 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
727 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
728 .msr_idx_to_pmc = intel_msr_idx_to_pmc,
729 .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx,
730 .is_valid_msr = intel_is_valid_msr,
731 .get_msr = intel_pmu_get_msr,
732 .set_msr = intel_pmu_set_msr,
733 .refresh = intel_pmu_refresh,
734 .init = intel_pmu_init,
735 .reset = intel_pmu_reset,
736 .deliver_pmi = intel_pmu_deliver_pmi,
737 .cleanup = intel_pmu_cleanup,
738 };
739