1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/idr.h>
12 #include <linux/interrupt.h>
13 #include <linux/list.h>
14 #include <linux/mhi.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/wait.h>
20 #include "internal.h"
21
22 static DEFINE_IDA(mhi_controller_ida);
23
24 const char * const mhi_ee_str[MHI_EE_MAX] = {
25 [MHI_EE_PBL] = "PRIMARY BOOTLOADER",
26 [MHI_EE_SBL] = "SECONDARY BOOTLOADER",
27 [MHI_EE_AMSS] = "MISSION MODE",
28 [MHI_EE_RDDM] = "RAMDUMP DOWNLOAD MODE",
29 [MHI_EE_WFW] = "WLAN FIRMWARE",
30 [MHI_EE_PTHRU] = "PASS THROUGH",
31 [MHI_EE_EDL] = "EMERGENCY DOWNLOAD",
32 [MHI_EE_FP] = "FLASH PROGRAMMER",
33 [MHI_EE_DISABLE_TRANSITION] = "DISABLE",
34 [MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED",
35 };
36
37 const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
38 [DEV_ST_TRANSITION_PBL] = "PBL",
39 [DEV_ST_TRANSITION_READY] = "READY",
40 [DEV_ST_TRANSITION_SBL] = "SBL",
41 [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION MODE",
42 [DEV_ST_TRANSITION_FP] = "FLASH PROGRAMMER",
43 [DEV_ST_TRANSITION_SYS_ERR] = "SYS ERROR",
44 [DEV_ST_TRANSITION_DISABLE] = "DISABLE",
45 };
46
47 const char * const mhi_state_str[MHI_STATE_MAX] = {
48 [MHI_STATE_RESET] = "RESET",
49 [MHI_STATE_READY] = "READY",
50 [MHI_STATE_M0] = "M0",
51 [MHI_STATE_M1] = "M1",
52 [MHI_STATE_M2] = "M2",
53 [MHI_STATE_M3] = "M3",
54 [MHI_STATE_M3_FAST] = "M3 FAST",
55 [MHI_STATE_BHI] = "BHI",
56 [MHI_STATE_SYS_ERR] = "SYS ERROR",
57 };
58
59 const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = {
60 [MHI_CH_STATE_TYPE_RESET] = "RESET",
61 [MHI_CH_STATE_TYPE_STOP] = "STOP",
62 [MHI_CH_STATE_TYPE_START] = "START",
63 };
64
65 static const char * const mhi_pm_state_str[] = {
66 [MHI_PM_STATE_DISABLE] = "DISABLE",
67 [MHI_PM_STATE_POR] = "POWER ON RESET",
68 [MHI_PM_STATE_M0] = "M0",
69 [MHI_PM_STATE_M2] = "M2",
70 [MHI_PM_STATE_M3_ENTER] = "M?->M3",
71 [MHI_PM_STATE_M3] = "M3",
72 [MHI_PM_STATE_M3_EXIT] = "M3->M0",
73 [MHI_PM_STATE_FW_DL_ERR] = "Firmware Download Error",
74 [MHI_PM_STATE_SYS_ERR_DETECT] = "SYS ERROR Detect",
75 [MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS ERROR Process",
76 [MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process",
77 [MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "Linkdown or Error Fatal Detect",
78 };
79
to_mhi_pm_state_str(u32 state)80 const char *to_mhi_pm_state_str(u32 state)
81 {
82 int index;
83
84 if (state)
85 index = __fls(state);
86
87 if (!state || index >= ARRAY_SIZE(mhi_pm_state_str))
88 return "Invalid State";
89
90 return mhi_pm_state_str[index];
91 }
92
serial_number_show(struct device * dev,struct device_attribute * attr,char * buf)93 static ssize_t serial_number_show(struct device *dev,
94 struct device_attribute *attr,
95 char *buf)
96 {
97 struct mhi_device *mhi_dev = to_mhi_device(dev);
98 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
99
100 return snprintf(buf, PAGE_SIZE, "Serial Number: %u\n",
101 mhi_cntrl->serial_number);
102 }
103 static DEVICE_ATTR_RO(serial_number);
104
oem_pk_hash_show(struct device * dev,struct device_attribute * attr,char * buf)105 static ssize_t oem_pk_hash_show(struct device *dev,
106 struct device_attribute *attr,
107 char *buf)
108 {
109 struct mhi_device *mhi_dev = to_mhi_device(dev);
110 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
111 int i, cnt = 0;
112
113 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++)
114 cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
115 "OEMPKHASH[%d]: 0x%x\n", i,
116 mhi_cntrl->oem_pk_hash[i]);
117
118 return cnt;
119 }
120 static DEVICE_ATTR_RO(oem_pk_hash);
121
122 static struct attribute *mhi_dev_attrs[] = {
123 &dev_attr_serial_number.attr,
124 &dev_attr_oem_pk_hash.attr,
125 NULL,
126 };
127 ATTRIBUTE_GROUPS(mhi_dev);
128
129 /* MHI protocol requires the transfer ring to be aligned with ring length */
mhi_alloc_aligned_ring(struct mhi_controller * mhi_cntrl,struct mhi_ring * ring,u64 len)130 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,
131 struct mhi_ring *ring,
132 u64 len)
133 {
134 ring->alloc_size = len + (len - 1);
135 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
136 &ring->dma_handle, GFP_KERNEL);
137 if (!ring->pre_aligned)
138 return -ENOMEM;
139
140 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1);
141 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle);
142
143 return 0;
144 }
145
mhi_deinit_free_irq(struct mhi_controller * mhi_cntrl)146 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)
147 {
148 int i;
149 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
150
151 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
152 if (mhi_event->offload_ev)
153 continue;
154
155 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
156 }
157
158 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
159 }
160
mhi_init_irq_setup(struct mhi_controller * mhi_cntrl)161 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
162 {
163 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
164 struct device *dev = &mhi_cntrl->mhi_dev->dev;
165 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND;
166 int i, ret;
167
168 /* if controller driver has set irq_flags, use it */
169 if (mhi_cntrl->irq_flags)
170 irq_flags = mhi_cntrl->irq_flags;
171
172 /* Setup BHI_INTVEC IRQ */
173 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,
174 mhi_intvec_threaded_handler,
175 irq_flags,
176 "bhi", mhi_cntrl);
177 if (ret)
178 return ret;
179
180 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
181 if (mhi_event->offload_ev)
182 continue;
183
184 if (mhi_event->irq >= mhi_cntrl->nr_irqs) {
185 dev_err(dev, "irq %d not available for event ring\n",
186 mhi_event->irq);
187 ret = -EINVAL;
188 goto error_request;
189 }
190
191 ret = request_irq(mhi_cntrl->irq[mhi_event->irq],
192 mhi_irq_handler,
193 irq_flags,
194 "mhi", mhi_event);
195 if (ret) {
196 dev_err(dev, "Error requesting irq:%d for ev:%d\n",
197 mhi_cntrl->irq[mhi_event->irq], i);
198 goto error_request;
199 }
200 }
201
202 return 0;
203
204 error_request:
205 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
206 if (mhi_event->offload_ev)
207 continue;
208
209 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
210 }
211 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
212
213 return ret;
214 }
215
mhi_deinit_dev_ctxt(struct mhi_controller * mhi_cntrl)216 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)
217 {
218 int i;
219 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;
220 struct mhi_cmd *mhi_cmd;
221 struct mhi_event *mhi_event;
222 struct mhi_ring *ring;
223
224 mhi_cmd = mhi_cntrl->mhi_cmd;
225 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) {
226 ring = &mhi_cmd->ring;
227 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
228 ring->pre_aligned, ring->dma_handle);
229 ring->base = NULL;
230 ring->iommu_base = 0;
231 }
232
233 dma_free_coherent(mhi_cntrl->cntrl_dev,
234 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
235 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
236
237 mhi_event = mhi_cntrl->mhi_event;
238 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
239 if (mhi_event->offload_ev)
240 continue;
241
242 ring = &mhi_event->ring;
243 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
244 ring->pre_aligned, ring->dma_handle);
245 ring->base = NULL;
246 ring->iommu_base = 0;
247 }
248
249 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
250 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
251 mhi_ctxt->er_ctxt_addr);
252
253 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
254 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
255 mhi_ctxt->chan_ctxt_addr);
256
257 kfree(mhi_ctxt);
258 mhi_cntrl->mhi_ctxt = NULL;
259 }
260
mhi_init_dev_ctxt(struct mhi_controller * mhi_cntrl)261 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
262 {
263 struct mhi_ctxt *mhi_ctxt;
264 struct mhi_chan_ctxt *chan_ctxt;
265 struct mhi_event_ctxt *er_ctxt;
266 struct mhi_cmd_ctxt *cmd_ctxt;
267 struct mhi_chan *mhi_chan;
268 struct mhi_event *mhi_event;
269 struct mhi_cmd *mhi_cmd;
270 u32 tmp;
271 int ret = -ENOMEM, i;
272
273 atomic_set(&mhi_cntrl->dev_wake, 0);
274 atomic_set(&mhi_cntrl->pending_pkts, 0);
275
276 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL);
277 if (!mhi_ctxt)
278 return -ENOMEM;
279
280 /* Setup channel ctxt */
281 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
282 sizeof(*mhi_ctxt->chan_ctxt) *
283 mhi_cntrl->max_chan,
284 &mhi_ctxt->chan_ctxt_addr,
285 GFP_KERNEL);
286 if (!mhi_ctxt->chan_ctxt)
287 goto error_alloc_chan_ctxt;
288
289 mhi_chan = mhi_cntrl->mhi_chan;
290 chan_ctxt = mhi_ctxt->chan_ctxt;
291 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {
292 /* Skip if it is an offload channel */
293 if (mhi_chan->offload_ch)
294 continue;
295
296 tmp = le32_to_cpu(chan_ctxt->chcfg);
297 tmp &= ~CHAN_CTX_CHSTATE_MASK;
298 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
299 tmp &= ~CHAN_CTX_BRSTMODE_MASK;
300 tmp |= (mhi_chan->db_cfg.brstmode << CHAN_CTX_BRSTMODE_SHIFT);
301 tmp &= ~CHAN_CTX_POLLCFG_MASK;
302 tmp |= (mhi_chan->db_cfg.pollcfg << CHAN_CTX_POLLCFG_SHIFT);
303 chan_ctxt->chcfg = cpu_to_le32(tmp);
304
305 chan_ctxt->chtype = cpu_to_le32(mhi_chan->type);
306 chan_ctxt->erindex = cpu_to_le32(mhi_chan->er_index);
307
308 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
309 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;
310 }
311
312 /* Setup event context */
313 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
314 sizeof(*mhi_ctxt->er_ctxt) *
315 mhi_cntrl->total_ev_rings,
316 &mhi_ctxt->er_ctxt_addr,
317 GFP_KERNEL);
318 if (!mhi_ctxt->er_ctxt)
319 goto error_alloc_er_ctxt;
320
321 er_ctxt = mhi_ctxt->er_ctxt;
322 mhi_event = mhi_cntrl->mhi_event;
323 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
324 mhi_event++) {
325 struct mhi_ring *ring = &mhi_event->ring;
326
327 /* Skip if it is an offload event */
328 if (mhi_event->offload_ev)
329 continue;
330
331 tmp = le32_to_cpu(er_ctxt->intmod);
332 tmp &= ~EV_CTX_INTMODC_MASK;
333 tmp &= ~EV_CTX_INTMODT_MASK;
334 tmp |= (mhi_event->intmod << EV_CTX_INTMODT_SHIFT);
335 er_ctxt->intmod = cpu_to_le32(tmp);
336
337 er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID);
338 er_ctxt->msivec = cpu_to_le32(mhi_event->irq);
339 mhi_event->db_cfg.db_mode = true;
340
341 ring->el_size = sizeof(struct mhi_ring_element);
342 ring->len = ring->el_size * ring->elements;
343 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
344 if (ret)
345 goto error_alloc_er;
346
347 /*
348 * If the read pointer equals to the write pointer, then the
349 * ring is empty
350 */
351 ring->rp = ring->wp = ring->base;
352 er_ctxt->rbase = cpu_to_le64(ring->iommu_base);
353 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;
354 er_ctxt->rlen = cpu_to_le64(ring->len);
355 ring->ctxt_wp = &er_ctxt->wp;
356 }
357
358 /* Setup cmd context */
359 ret = -ENOMEM;
360 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
361 sizeof(*mhi_ctxt->cmd_ctxt) *
362 NR_OF_CMD_RINGS,
363 &mhi_ctxt->cmd_ctxt_addr,
364 GFP_KERNEL);
365 if (!mhi_ctxt->cmd_ctxt)
366 goto error_alloc_er;
367
368 mhi_cmd = mhi_cntrl->mhi_cmd;
369 cmd_ctxt = mhi_ctxt->cmd_ctxt;
370 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
371 struct mhi_ring *ring = &mhi_cmd->ring;
372
373 ring->el_size = sizeof(struct mhi_ring_element);
374 ring->elements = CMD_EL_PER_RING;
375 ring->len = ring->el_size * ring->elements;
376 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
377 if (ret)
378 goto error_alloc_cmd;
379
380 ring->rp = ring->wp = ring->base;
381 cmd_ctxt->rbase = cpu_to_le64(ring->iommu_base);
382 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;
383 cmd_ctxt->rlen = cpu_to_le64(ring->len);
384 ring->ctxt_wp = &cmd_ctxt->wp;
385 }
386
387 mhi_cntrl->mhi_ctxt = mhi_ctxt;
388
389 return 0;
390
391 error_alloc_cmd:
392 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) {
393 struct mhi_ring *ring = &mhi_cmd->ring;
394
395 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
396 ring->pre_aligned, ring->dma_handle);
397 }
398 dma_free_coherent(mhi_cntrl->cntrl_dev,
399 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
400 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
401 i = mhi_cntrl->total_ev_rings;
402 mhi_event = mhi_cntrl->mhi_event + i;
403
404 error_alloc_er:
405 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
406 struct mhi_ring *ring = &mhi_event->ring;
407
408 if (mhi_event->offload_ev)
409 continue;
410
411 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
412 ring->pre_aligned, ring->dma_handle);
413 }
414 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
415 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
416 mhi_ctxt->er_ctxt_addr);
417
418 error_alloc_er_ctxt:
419 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
420 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
421 mhi_ctxt->chan_ctxt_addr);
422
423 error_alloc_chan_ctxt:
424 kfree(mhi_ctxt);
425
426 return ret;
427 }
428
mhi_init_mmio(struct mhi_controller * mhi_cntrl)429 int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
430 {
431 u32 val;
432 int i, ret;
433 struct mhi_chan *mhi_chan;
434 struct mhi_event *mhi_event;
435 void __iomem *base = mhi_cntrl->regs;
436 struct device *dev = &mhi_cntrl->mhi_dev->dev;
437 struct {
438 u32 offset;
439 u32 mask;
440 u32 shift;
441 u32 val;
442 } reg_info[] = {
443 {
444 CCABAP_HIGHER, U32_MAX, 0,
445 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
446 },
447 {
448 CCABAP_LOWER, U32_MAX, 0,
449 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
450 },
451 {
452 ECABAP_HIGHER, U32_MAX, 0,
453 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
454 },
455 {
456 ECABAP_LOWER, U32_MAX, 0,
457 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
458 },
459 {
460 CRCBAP_HIGHER, U32_MAX, 0,
461 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
462 },
463 {
464 CRCBAP_LOWER, U32_MAX, 0,
465 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
466 },
467 {
468 MHICFG, MHICFG_NER_MASK, MHICFG_NER_SHIFT,
469 mhi_cntrl->total_ev_rings,
470 },
471 {
472 MHICFG, MHICFG_NHWER_MASK, MHICFG_NHWER_SHIFT,
473 mhi_cntrl->hw_ev_rings,
474 },
475 {
476 MHICTRLBASE_HIGHER, U32_MAX, 0,
477 upper_32_bits(mhi_cntrl->iova_start),
478 },
479 {
480 MHICTRLBASE_LOWER, U32_MAX, 0,
481 lower_32_bits(mhi_cntrl->iova_start),
482 },
483 {
484 MHIDATABASE_HIGHER, U32_MAX, 0,
485 upper_32_bits(mhi_cntrl->iova_start),
486 },
487 {
488 MHIDATABASE_LOWER, U32_MAX, 0,
489 lower_32_bits(mhi_cntrl->iova_start),
490 },
491 {
492 MHICTRLLIMIT_HIGHER, U32_MAX, 0,
493 upper_32_bits(mhi_cntrl->iova_stop),
494 },
495 {
496 MHICTRLLIMIT_LOWER, U32_MAX, 0,
497 lower_32_bits(mhi_cntrl->iova_stop),
498 },
499 {
500 MHIDATALIMIT_HIGHER, U32_MAX, 0,
501 upper_32_bits(mhi_cntrl->iova_stop),
502 },
503 {
504 MHIDATALIMIT_LOWER, U32_MAX, 0,
505 lower_32_bits(mhi_cntrl->iova_stop),
506 },
507 { 0, 0, 0 }
508 };
509
510 dev_dbg(dev, "Initializing MHI registers\n");
511
512 /* Read channel db offset */
513 ret = mhi_read_reg_field(mhi_cntrl, base, CHDBOFF, CHDBOFF_CHDBOFF_MASK,
514 CHDBOFF_CHDBOFF_SHIFT, &val);
515 if (ret) {
516 dev_err(dev, "Unable to read CHDBOFF register\n");
517 return -EIO;
518 }
519
520 if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) {
521 dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n",
522 val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB));
523 return -ERANGE;
524 }
525
526 /* Setup wake db */
527 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
528 mhi_cntrl->wake_set = false;
529
530 /* Setup channel db address for each channel in tre_ring */
531 mhi_chan = mhi_cntrl->mhi_chan;
532 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
533 mhi_chan->tre_ring.db_addr = base + val;
534
535 /* Read event ring db offset */
536 ret = mhi_read_reg_field(mhi_cntrl, base, ERDBOFF, ERDBOFF_ERDBOFF_MASK,
537 ERDBOFF_ERDBOFF_SHIFT, &val);
538 if (ret) {
539 dev_err(dev, "Unable to read ERDBOFF register\n");
540 return -EIO;
541 }
542
543 if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) {
544 dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n",
545 val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings));
546 return -ERANGE;
547 }
548
549 /* Setup event db address for each ev_ring */
550 mhi_event = mhi_cntrl->mhi_event;
551 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
552 if (mhi_event->offload_ev)
553 continue;
554
555 mhi_event->ring.db_addr = base + val;
556 }
557
558 /* Setup DB register for primary CMD rings */
559 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
560
561 /* Write to MMIO registers */
562 for (i = 0; reg_info[i].offset; i++)
563 mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
564 reg_info[i].mask, reg_info[i].shift,
565 reg_info[i].val);
566
567 return 0;
568 }
569
mhi_deinit_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)570 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
571 struct mhi_chan *mhi_chan)
572 {
573 struct mhi_ring *buf_ring;
574 struct mhi_ring *tre_ring;
575 struct mhi_chan_ctxt *chan_ctxt;
576 u32 tmp;
577
578 buf_ring = &mhi_chan->buf_ring;
579 tre_ring = &mhi_chan->tre_ring;
580 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
581
582 if (!chan_ctxt->rbase) /* Already uninitialized */
583 return;
584
585 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
586 tre_ring->pre_aligned, tre_ring->dma_handle);
587 vfree(buf_ring->base);
588
589 buf_ring->base = tre_ring->base = NULL;
590 tre_ring->ctxt_wp = NULL;
591 chan_ctxt->rbase = 0;
592 chan_ctxt->rlen = 0;
593 chan_ctxt->rp = 0;
594 chan_ctxt->wp = 0;
595
596 tmp = le32_to_cpu(chan_ctxt->chcfg);
597 tmp &= ~CHAN_CTX_CHSTATE_MASK;
598 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
599 chan_ctxt->chcfg = cpu_to_le32(tmp);
600
601 /* Update to all cores */
602 smp_wmb();
603 }
604
mhi_init_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)605 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
606 struct mhi_chan *mhi_chan)
607 {
608 struct mhi_ring *buf_ring;
609 struct mhi_ring *tre_ring;
610 struct mhi_chan_ctxt *chan_ctxt;
611 u32 tmp;
612 int ret;
613
614 buf_ring = &mhi_chan->buf_ring;
615 tre_ring = &mhi_chan->tre_ring;
616 tre_ring->el_size = sizeof(struct mhi_ring_element);
617 tre_ring->len = tre_ring->el_size * tre_ring->elements;
618 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
619 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);
620 if (ret)
621 return -ENOMEM;
622
623 buf_ring->el_size = sizeof(struct mhi_buf_info);
624 buf_ring->len = buf_ring->el_size * buf_ring->elements;
625 buf_ring->base = vzalloc(buf_ring->len);
626
627 if (!buf_ring->base) {
628 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
629 tre_ring->pre_aligned, tre_ring->dma_handle);
630 return -ENOMEM;
631 }
632
633 tmp = le32_to_cpu(chan_ctxt->chcfg);
634 tmp &= ~CHAN_CTX_CHSTATE_MASK;
635 tmp |= (MHI_CH_STATE_ENABLED << CHAN_CTX_CHSTATE_SHIFT);
636 chan_ctxt->chcfg = cpu_to_le32(tmp);
637
638 chan_ctxt->rbase = cpu_to_le64(tre_ring->iommu_base);
639 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
640 chan_ctxt->rlen = cpu_to_le64(tre_ring->len);
641 tre_ring->ctxt_wp = &chan_ctxt->wp;
642
643 tre_ring->rp = tre_ring->wp = tre_ring->base;
644 buf_ring->rp = buf_ring->wp = buf_ring->base;
645 mhi_chan->db_cfg.db_mode = 1;
646
647 /* Update to all cores */
648 smp_wmb();
649
650 return 0;
651 }
652
parse_ev_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)653 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
654 const struct mhi_controller_config *config)
655 {
656 struct mhi_event *mhi_event;
657 const struct mhi_event_config *event_cfg;
658 struct device *dev = mhi_cntrl->cntrl_dev;
659 int i, num;
660
661 num = config->num_events;
662 mhi_cntrl->total_ev_rings = num;
663 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event),
664 GFP_KERNEL);
665 if (!mhi_cntrl->mhi_event)
666 return -ENOMEM;
667
668 /* Populate event ring */
669 mhi_event = mhi_cntrl->mhi_event;
670 for (i = 0; i < num; i++) {
671 event_cfg = &config->event_cfg[i];
672
673 mhi_event->er_index = i;
674 mhi_event->ring.elements = event_cfg->num_elements;
675 mhi_event->intmod = event_cfg->irq_moderation_ms;
676 mhi_event->irq = event_cfg->irq;
677
678 if (event_cfg->channel != U32_MAX) {
679 /* This event ring has a dedicated channel */
680 mhi_event->chan = event_cfg->channel;
681 if (mhi_event->chan >= mhi_cntrl->max_chan) {
682 dev_err(dev,
683 "Event Ring channel not available\n");
684 goto error_ev_cfg;
685 }
686
687 mhi_event->mhi_chan =
688 &mhi_cntrl->mhi_chan[mhi_event->chan];
689 }
690
691 /* Priority is fixed to 1 for now */
692 mhi_event->priority = 1;
693
694 mhi_event->db_cfg.brstmode = event_cfg->mode;
695 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
696 goto error_ev_cfg;
697
698 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
699 mhi_event->db_cfg.process_db = mhi_db_brstmode;
700 else
701 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
702
703 mhi_event->data_type = event_cfg->data_type;
704
705 switch (mhi_event->data_type) {
706 case MHI_ER_DATA:
707 mhi_event->process_event = mhi_process_data_event_ring;
708 break;
709 case MHI_ER_CTRL:
710 mhi_event->process_event = mhi_process_ctrl_ev_ring;
711 break;
712 default:
713 dev_err(dev, "Event Ring type not supported\n");
714 goto error_ev_cfg;
715 }
716
717 mhi_event->hw_ring = event_cfg->hardware_event;
718 if (mhi_event->hw_ring)
719 mhi_cntrl->hw_ev_rings++;
720 else
721 mhi_cntrl->sw_ev_rings++;
722
723 mhi_event->cl_manage = event_cfg->client_managed;
724 mhi_event->offload_ev = event_cfg->offload_channel;
725 mhi_event++;
726 }
727
728 return 0;
729
730 error_ev_cfg:
731
732 kfree(mhi_cntrl->mhi_event);
733 return -EINVAL;
734 }
735
parse_ch_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)736 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,
737 const struct mhi_controller_config *config)
738 {
739 const struct mhi_channel_config *ch_cfg;
740 struct device *dev = mhi_cntrl->cntrl_dev;
741 int i;
742 u32 chan;
743
744 mhi_cntrl->max_chan = config->max_channels;
745
746 /*
747 * The allocation of MHI channels can exceed 32KB in some scenarios,
748 * so to avoid any memory possible allocation failures, vzalloc is
749 * used here
750 */
751 mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan *
752 sizeof(*mhi_cntrl->mhi_chan));
753 if (!mhi_cntrl->mhi_chan)
754 return -ENOMEM;
755
756 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);
757
758 /* Populate channel configurations */
759 for (i = 0; i < config->num_channels; i++) {
760 struct mhi_chan *mhi_chan;
761
762 ch_cfg = &config->ch_cfg[i];
763
764 chan = ch_cfg->num;
765 if (chan >= mhi_cntrl->max_chan) {
766 dev_err(dev, "Channel %d not available\n", chan);
767 goto error_chan_cfg;
768 }
769
770 mhi_chan = &mhi_cntrl->mhi_chan[chan];
771 mhi_chan->name = ch_cfg->name;
772 mhi_chan->chan = chan;
773
774 mhi_chan->tre_ring.elements = ch_cfg->num_elements;
775 if (!mhi_chan->tre_ring.elements)
776 goto error_chan_cfg;
777
778 /*
779 * For some channels, local ring length should be bigger than
780 * the transfer ring length due to internal logical channels
781 * in device. So host can queue much more buffers than transfer
782 * ring length. Example, RSC channels should have a larger local
783 * channel length than transfer ring length.
784 */
785 mhi_chan->buf_ring.elements = ch_cfg->local_elements;
786 if (!mhi_chan->buf_ring.elements)
787 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements;
788 mhi_chan->er_index = ch_cfg->event_ring;
789 mhi_chan->dir = ch_cfg->dir;
790
791 /*
792 * For most channels, chtype is identical to channel directions.
793 * So, if it is not defined then assign channel direction to
794 * chtype
795 */
796 mhi_chan->type = ch_cfg->type;
797 if (!mhi_chan->type)
798 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir;
799
800 mhi_chan->ee_mask = ch_cfg->ee_mask;
801 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg;
802 mhi_chan->lpm_notify = ch_cfg->lpm_notify;
803 mhi_chan->offload_ch = ch_cfg->offload_channel;
804 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch;
805 mhi_chan->pre_alloc = ch_cfg->auto_queue;
806 mhi_chan->wake_capable = ch_cfg->wake_capable;
807
808 /*
809 * If MHI host allocates buffers, then the channel direction
810 * should be DMA_FROM_DEVICE
811 */
812 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) {
813 dev_err(dev, "Invalid channel configuration\n");
814 goto error_chan_cfg;
815 }
816
817 /*
818 * Bi-directional and direction less channel must be an
819 * offload channel
820 */
821 if ((mhi_chan->dir == DMA_BIDIRECTIONAL ||
822 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) {
823 dev_err(dev, "Invalid channel configuration\n");
824 goto error_chan_cfg;
825 }
826
827 if (!mhi_chan->offload_ch) {
828 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell;
829 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) {
830 dev_err(dev, "Invalid Door bell mode\n");
831 goto error_chan_cfg;
832 }
833 }
834
835 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
836 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
837 else
838 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
839
840 mhi_chan->configured = true;
841
842 if (mhi_chan->lpm_notify)
843 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);
844 }
845
846 return 0;
847
848 error_chan_cfg:
849 vfree(mhi_cntrl->mhi_chan);
850
851 return -EINVAL;
852 }
853
parse_config(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)854 static int parse_config(struct mhi_controller *mhi_cntrl,
855 const struct mhi_controller_config *config)
856 {
857 int ret;
858
859 /* Parse MHI channel configuration */
860 ret = parse_ch_cfg(mhi_cntrl, config);
861 if (ret)
862 return ret;
863
864 /* Parse MHI event configuration */
865 ret = parse_ev_cfg(mhi_cntrl, config);
866 if (ret)
867 goto error_ev_cfg;
868
869 mhi_cntrl->timeout_ms = config->timeout_ms;
870 if (!mhi_cntrl->timeout_ms)
871 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
872
873 mhi_cntrl->bounce_buf = config->use_bounce_buf;
874 mhi_cntrl->buffer_len = config->buf_len;
875 if (!mhi_cntrl->buffer_len)
876 mhi_cntrl->buffer_len = MHI_MAX_MTU;
877
878 /* By default, host is allowed to ring DB in both M0 and M2 states */
879 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
880 if (config->m2_no_db)
881 mhi_cntrl->db_access &= ~MHI_PM_M2;
882
883 return 0;
884
885 error_ev_cfg:
886 vfree(mhi_cntrl->mhi_chan);
887
888 return ret;
889 }
890
mhi_register_controller(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)891 int mhi_register_controller(struct mhi_controller *mhi_cntrl,
892 const struct mhi_controller_config *config)
893 {
894 struct mhi_event *mhi_event;
895 struct mhi_chan *mhi_chan;
896 struct mhi_cmd *mhi_cmd;
897 struct mhi_device *mhi_dev;
898 u32 soc_info;
899 int ret, i;
900
901 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
902 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
903 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
904 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
905 !mhi_cntrl->irq || !mhi_cntrl->reg_len)
906 return -EINVAL;
907
908 ret = parse_config(mhi_cntrl, config);
909 if (ret)
910 return -EINVAL;
911
912 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS,
913 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);
914 if (!mhi_cntrl->mhi_cmd) {
915 ret = -ENOMEM;
916 goto err_free_event;
917 }
918
919 INIT_LIST_HEAD(&mhi_cntrl->transition_list);
920 mutex_init(&mhi_cntrl->pm_mutex);
921 rwlock_init(&mhi_cntrl->pm_lock);
922 spin_lock_init(&mhi_cntrl->transition_lock);
923 spin_lock_init(&mhi_cntrl->wlock);
924 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
925 init_waitqueue_head(&mhi_cntrl->state_event);
926
927 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);
928 if (!mhi_cntrl->hiprio_wq) {
929 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");
930 ret = -ENOMEM;
931 goto err_free_cmd;
932 }
933
934 mhi_cmd = mhi_cntrl->mhi_cmd;
935 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++)
936 spin_lock_init(&mhi_cmd->lock);
937
938 mhi_event = mhi_cntrl->mhi_event;
939 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
940 /* Skip for offload events */
941 if (mhi_event->offload_ev)
942 continue;
943
944 mhi_event->mhi_cntrl = mhi_cntrl;
945 spin_lock_init(&mhi_event->lock);
946 if (mhi_event->data_type == MHI_ER_CTRL)
947 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task,
948 (ulong)mhi_event);
949 else
950 tasklet_init(&mhi_event->task, mhi_ev_task,
951 (ulong)mhi_event);
952 }
953
954 mhi_chan = mhi_cntrl->mhi_chan;
955 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
956 mutex_init(&mhi_chan->mutex);
957 init_completion(&mhi_chan->completion);
958 rwlock_init(&mhi_chan->lock);
959
960 /* used in setting bei field of TRE */
961 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
962 mhi_chan->intmod = mhi_event->intmod;
963 }
964
965 if (mhi_cntrl->bounce_buf) {
966 mhi_cntrl->map_single = mhi_map_single_use_bb;
967 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;
968 } else {
969 mhi_cntrl->map_single = mhi_map_single_no_bb;
970 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
971 }
972
973 /* Read the MHI device info */
974 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,
975 SOC_HW_VERSION_OFFS, &soc_info);
976 if (ret)
977 goto err_destroy_wq;
978
979 mhi_cntrl->family_number = (soc_info & SOC_HW_VERSION_FAM_NUM_BMSK) >>
980 SOC_HW_VERSION_FAM_NUM_SHFT;
981 mhi_cntrl->device_number = (soc_info & SOC_HW_VERSION_DEV_NUM_BMSK) >>
982 SOC_HW_VERSION_DEV_NUM_SHFT;
983 mhi_cntrl->major_version = (soc_info & SOC_HW_VERSION_MAJOR_VER_BMSK) >>
984 SOC_HW_VERSION_MAJOR_VER_SHFT;
985 mhi_cntrl->minor_version = (soc_info & SOC_HW_VERSION_MINOR_VER_BMSK) >>
986 SOC_HW_VERSION_MINOR_VER_SHFT;
987
988 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL);
989 if (mhi_cntrl->index < 0) {
990 ret = mhi_cntrl->index;
991 goto err_destroy_wq;
992 }
993
994 /* Register controller with MHI bus */
995 mhi_dev = mhi_alloc_device(mhi_cntrl);
996 if (IS_ERR(mhi_dev)) {
997 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
998 ret = PTR_ERR(mhi_dev);
999 goto err_ida_free;
1000 }
1001
1002 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
1003 mhi_dev->mhi_cntrl = mhi_cntrl;
1004 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index);
1005 mhi_dev->name = dev_name(&mhi_dev->dev);
1006
1007 /* Init wakeup source */
1008 device_init_wakeup(&mhi_dev->dev, true);
1009
1010 ret = device_add(&mhi_dev->dev);
1011 if (ret)
1012 goto err_release_dev;
1013
1014 mhi_cntrl->mhi_dev = mhi_dev;
1015
1016 mhi_create_debugfs(mhi_cntrl);
1017
1018 return 0;
1019
1020 err_release_dev:
1021 put_device(&mhi_dev->dev);
1022 err_ida_free:
1023 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1024 err_destroy_wq:
1025 destroy_workqueue(mhi_cntrl->hiprio_wq);
1026 err_free_cmd:
1027 kfree(mhi_cntrl->mhi_cmd);
1028 err_free_event:
1029 kfree(mhi_cntrl->mhi_event);
1030 vfree(mhi_cntrl->mhi_chan);
1031
1032 return ret;
1033 }
1034 EXPORT_SYMBOL_GPL(mhi_register_controller);
1035
mhi_unregister_controller(struct mhi_controller * mhi_cntrl)1036 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
1037 {
1038 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;
1039 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
1040 unsigned int i;
1041
1042 mhi_destroy_debugfs(mhi_cntrl);
1043
1044 destroy_workqueue(mhi_cntrl->hiprio_wq);
1045 kfree(mhi_cntrl->mhi_cmd);
1046 kfree(mhi_cntrl->mhi_event);
1047
1048 /* Drop the references to MHI devices created for channels */
1049 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
1050 if (!mhi_chan->mhi_dev)
1051 continue;
1052
1053 put_device(&mhi_chan->mhi_dev->dev);
1054 }
1055 vfree(mhi_cntrl->mhi_chan);
1056
1057 device_del(&mhi_dev->dev);
1058 put_device(&mhi_dev->dev);
1059
1060 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1061 }
1062 EXPORT_SYMBOL_GPL(mhi_unregister_controller);
1063
mhi_alloc_controller(void)1064 struct mhi_controller *mhi_alloc_controller(void)
1065 {
1066 struct mhi_controller *mhi_cntrl;
1067
1068 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL);
1069
1070 return mhi_cntrl;
1071 }
1072 EXPORT_SYMBOL_GPL(mhi_alloc_controller);
1073
mhi_free_controller(struct mhi_controller * mhi_cntrl)1074 void mhi_free_controller(struct mhi_controller *mhi_cntrl)
1075 {
1076 kfree(mhi_cntrl);
1077 }
1078 EXPORT_SYMBOL_GPL(mhi_free_controller);
1079
mhi_prepare_for_power_up(struct mhi_controller * mhi_cntrl)1080 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
1081 {
1082 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1083 u32 bhi_off, bhie_off;
1084 int ret;
1085
1086 mutex_lock(&mhi_cntrl->pm_mutex);
1087
1088 ret = mhi_init_dev_ctxt(mhi_cntrl);
1089 if (ret)
1090 goto error_dev_ctxt;
1091
1092 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
1093 if (ret) {
1094 dev_err(dev, "Error getting BHI offset\n");
1095 goto error_reg_offset;
1096 }
1097
1098 if (bhi_off >= mhi_cntrl->reg_len) {
1099 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
1100 bhi_off, mhi_cntrl->reg_len);
1101 ret = -EINVAL;
1102 goto error_reg_offset;
1103 }
1104 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
1105
1106 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
1107 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
1108 &bhie_off);
1109 if (ret) {
1110 dev_err(dev, "Error getting BHIE offset\n");
1111 goto error_reg_offset;
1112 }
1113
1114 if (bhie_off >= mhi_cntrl->reg_len) {
1115 dev_err(dev,
1116 "BHIe offset: 0x%x is out of range: 0x%zx\n",
1117 bhie_off, mhi_cntrl->reg_len);
1118 ret = -EINVAL;
1119 goto error_reg_offset;
1120 }
1121 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
1122 }
1123
1124 if (mhi_cntrl->rddm_size) {
1125 /*
1126 * This controller supports RDDM, so we need to manually clear
1127 * BHIE RX registers since POR values are undefined.
1128 */
1129 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
1130 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
1131 4);
1132 /*
1133 * Allocate RDDM table for debugging purpose if specified
1134 */
1135 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
1136 mhi_cntrl->rddm_size);
1137 if (mhi_cntrl->rddm_image)
1138 mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
1139 }
1140
1141 mutex_unlock(&mhi_cntrl->pm_mutex);
1142
1143 return 0;
1144
1145 error_reg_offset:
1146 mhi_deinit_dev_ctxt(mhi_cntrl);
1147
1148 error_dev_ctxt:
1149 mutex_unlock(&mhi_cntrl->pm_mutex);
1150
1151 return ret;
1152 }
1153 EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up);
1154
mhi_unprepare_after_power_down(struct mhi_controller * mhi_cntrl)1155 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
1156 {
1157 if (mhi_cntrl->fbc_image) {
1158 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1159 mhi_cntrl->fbc_image = NULL;
1160 }
1161
1162 if (mhi_cntrl->rddm_image) {
1163 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1164 mhi_cntrl->rddm_image = NULL;
1165 }
1166
1167 mhi_cntrl->bhi = NULL;
1168 mhi_cntrl->bhie = NULL;
1169
1170 mhi_deinit_dev_ctxt(mhi_cntrl);
1171 }
1172 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
1173
mhi_release_device(struct device * dev)1174 static void mhi_release_device(struct device *dev)
1175 {
1176 struct mhi_device *mhi_dev = to_mhi_device(dev);
1177
1178 /*
1179 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI
1180 * devices for the channels will only get created if the mhi_dev
1181 * associated with it is NULL. This scenario will happen during the
1182 * controller suspend and resume.
1183 */
1184 if (mhi_dev->ul_chan)
1185 mhi_dev->ul_chan->mhi_dev = NULL;
1186
1187 if (mhi_dev->dl_chan)
1188 mhi_dev->dl_chan->mhi_dev = NULL;
1189
1190 kfree(mhi_dev);
1191 }
1192
mhi_alloc_device(struct mhi_controller * mhi_cntrl)1193 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)
1194 {
1195 struct mhi_device *mhi_dev;
1196 struct device *dev;
1197
1198 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL);
1199 if (!mhi_dev)
1200 return ERR_PTR(-ENOMEM);
1201
1202 dev = &mhi_dev->dev;
1203 device_initialize(dev);
1204 dev->bus = &mhi_bus_type;
1205 dev->release = mhi_release_device;
1206
1207 if (mhi_cntrl->mhi_dev) {
1208 /* for MHI client devices, parent is the MHI controller device */
1209 dev->parent = &mhi_cntrl->mhi_dev->dev;
1210 } else {
1211 /* for MHI controller device, parent is the bus device (e.g. pci device) */
1212 dev->parent = mhi_cntrl->cntrl_dev;
1213 }
1214
1215 mhi_dev->mhi_cntrl = mhi_cntrl;
1216 mhi_dev->dev_wake = 0;
1217
1218 return mhi_dev;
1219 }
1220
mhi_driver_probe(struct device * dev)1221 static int mhi_driver_probe(struct device *dev)
1222 {
1223 struct mhi_device *mhi_dev = to_mhi_device(dev);
1224 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1225 struct device_driver *drv = dev->driver;
1226 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1227 struct mhi_event *mhi_event;
1228 struct mhi_chan *ul_chan = mhi_dev->ul_chan;
1229 struct mhi_chan *dl_chan = mhi_dev->dl_chan;
1230 int ret;
1231
1232 /* Bring device out of LPM */
1233 ret = mhi_device_get_sync(mhi_dev);
1234 if (ret)
1235 return ret;
1236
1237 ret = -EINVAL;
1238
1239 if (ul_chan) {
1240 /*
1241 * If channel supports LPM notifications then status_cb should
1242 * be provided
1243 */
1244 if (ul_chan->lpm_notify && !mhi_drv->status_cb)
1245 goto exit_probe;
1246
1247 /* For non-offload channels then xfer_cb should be provided */
1248 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb)
1249 goto exit_probe;
1250
1251 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1252 }
1253
1254 ret = -EINVAL;
1255 if (dl_chan) {
1256 /*
1257 * If channel supports LPM notifications then status_cb should
1258 * be provided
1259 */
1260 if (dl_chan->lpm_notify && !mhi_drv->status_cb)
1261 goto exit_probe;
1262
1263 /* For non-offload channels then xfer_cb should be provided */
1264 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb)
1265 goto exit_probe;
1266
1267 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];
1268
1269 /*
1270 * If the channel event ring is managed by client, then
1271 * status_cb must be provided so that the framework can
1272 * notify pending data
1273 */
1274 if (mhi_event->cl_manage && !mhi_drv->status_cb)
1275 goto exit_probe;
1276
1277 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1278 }
1279
1280 /* Call the user provided probe function */
1281 ret = mhi_drv->probe(mhi_dev, mhi_dev->id);
1282 if (ret)
1283 goto exit_probe;
1284
1285 mhi_device_put(mhi_dev);
1286
1287 return ret;
1288
1289 exit_probe:
1290 mhi_unprepare_from_transfer(mhi_dev);
1291
1292 mhi_device_put(mhi_dev);
1293
1294 return ret;
1295 }
1296
mhi_driver_remove(struct device * dev)1297 static int mhi_driver_remove(struct device *dev)
1298 {
1299 struct mhi_device *mhi_dev = to_mhi_device(dev);
1300 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver);
1301 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1302 struct mhi_chan *mhi_chan;
1303 enum mhi_ch_state ch_state[] = {
1304 MHI_CH_STATE_DISABLED,
1305 MHI_CH_STATE_DISABLED
1306 };
1307 int dir;
1308
1309 /* Skip if it is a controller device */
1310 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1311 return 0;
1312
1313 /* Reset both channels */
1314 for (dir = 0; dir < 2; dir++) {
1315 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1316
1317 if (!mhi_chan)
1318 continue;
1319
1320 /* Wake all threads waiting for completion */
1321 write_lock_irq(&mhi_chan->lock);
1322 mhi_chan->ccs = MHI_EV_CC_INVALID;
1323 complete_all(&mhi_chan->completion);
1324 write_unlock_irq(&mhi_chan->lock);
1325
1326 /* Set the channel state to disabled */
1327 mutex_lock(&mhi_chan->mutex);
1328 write_lock_irq(&mhi_chan->lock);
1329 ch_state[dir] = mhi_chan->ch_state;
1330 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED;
1331 write_unlock_irq(&mhi_chan->lock);
1332
1333 /* Reset the non-offload channel */
1334 if (!mhi_chan->offload_ch)
1335 mhi_reset_chan(mhi_cntrl, mhi_chan);
1336
1337 mutex_unlock(&mhi_chan->mutex);
1338 }
1339
1340 mhi_drv->remove(mhi_dev);
1341
1342 /* De-init channel if it was enabled */
1343 for (dir = 0; dir < 2; dir++) {
1344 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1345
1346 if (!mhi_chan)
1347 continue;
1348
1349 mutex_lock(&mhi_chan->mutex);
1350
1351 if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
1352 ch_state[dir] == MHI_CH_STATE_STOP) &&
1353 !mhi_chan->offload_ch)
1354 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
1355
1356 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
1357
1358 mutex_unlock(&mhi_chan->mutex);
1359 }
1360
1361 while (mhi_dev->dev_wake)
1362 mhi_device_put(mhi_dev);
1363
1364 return 0;
1365 }
1366
__mhi_driver_register(struct mhi_driver * mhi_drv,struct module * owner)1367 int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner)
1368 {
1369 struct device_driver *driver = &mhi_drv->driver;
1370
1371 if (!mhi_drv->probe || !mhi_drv->remove)
1372 return -EINVAL;
1373
1374 driver->bus = &mhi_bus_type;
1375 driver->owner = owner;
1376 driver->probe = mhi_driver_probe;
1377 driver->remove = mhi_driver_remove;
1378
1379 return driver_register(driver);
1380 }
1381 EXPORT_SYMBOL_GPL(__mhi_driver_register);
1382
mhi_driver_unregister(struct mhi_driver * mhi_drv)1383 void mhi_driver_unregister(struct mhi_driver *mhi_drv)
1384 {
1385 driver_unregister(&mhi_drv->driver);
1386 }
1387 EXPORT_SYMBOL_GPL(mhi_driver_unregister);
1388
mhi_uevent(struct device * dev,struct kobj_uevent_env * env)1389 static int mhi_uevent(struct device *dev, struct kobj_uevent_env *env)
1390 {
1391 struct mhi_device *mhi_dev = to_mhi_device(dev);
1392
1393 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT,
1394 mhi_dev->name);
1395 }
1396
mhi_match(struct device * dev,struct device_driver * drv)1397 static int mhi_match(struct device *dev, struct device_driver *drv)
1398 {
1399 struct mhi_device *mhi_dev = to_mhi_device(dev);
1400 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1401 const struct mhi_device_id *id;
1402
1403 /*
1404 * If the device is a controller type then there is no client driver
1405 * associated with it
1406 */
1407 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1408 return 0;
1409
1410 for (id = mhi_drv->id_table; id->chan[0]; id++)
1411 if (!strcmp(mhi_dev->name, id->chan)) {
1412 mhi_dev->id = id;
1413 return 1;
1414 }
1415
1416 return 0;
1417 };
1418
1419 struct bus_type mhi_bus_type = {
1420 .name = "mhi",
1421 .dev_name = "mhi",
1422 .match = mhi_match,
1423 .uevent = mhi_uevent,
1424 .dev_groups = mhi_dev_groups,
1425 };
1426
mhi_init(void)1427 static int __init mhi_init(void)
1428 {
1429 mhi_debugfs_init();
1430 return bus_register(&mhi_bus_type);
1431 }
1432
mhi_exit(void)1433 static void __exit mhi_exit(void)
1434 {
1435 mhi_debugfs_exit();
1436 bus_unregister(&mhi_bus_type);
1437 }
1438
1439 postcore_initcall(mhi_init);
1440 module_exit(mhi_exit);
1441
1442 MODULE_LICENSE("GPL v2");
1443 MODULE_DESCRIPTION("MHI Host Interface");
1444