1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/err.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 P_BI_TCXO,
26 P_CORE_BI_PLL_TEST_SE,
27 P_GPLL0_OUT_EVEN,
28 P_GPLL0_OUT_MAIN,
29 P_GPLL1_OUT_MAIN,
30 P_GPLL4_OUT_MAIN,
31 P_GPLL6_OUT_MAIN,
32 P_GPLL7_OUT_MAIN,
33 P_SLEEP_CLK,
34 };
35
36 static struct clk_alpha_pll gpll0 = {
37 .offset = 0x0,
38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
39 .clkr = {
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
42 .hw.init = &(struct clk_init_data){
43 .name = "gpll0",
44 .parent_data = &(const struct clk_parent_data){
45 .fw_name = "bi_tcxo",
46 .name = "bi_tcxo",
47 },
48 .num_parents = 1,
49 .ops = &clk_alpha_pll_fixed_fabia_ops,
50 },
51 },
52 };
53
54 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
55 { 0x1, 2 },
56 { }
57 };
58
59 static struct clk_alpha_pll_postdiv gpll0_out_even = {
60 .offset = 0x0,
61 .post_div_shift = 8,
62 .post_div_table = post_div_table_gpll0_out_even,
63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
64 .width = 4,
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "gpll0_out_even",
68 .parent_hws = (const struct clk_hw*[]){
69 &gpll0.clkr.hw,
70 },
71 .num_parents = 1,
72 .ops = &clk_alpha_pll_postdiv_fabia_ops,
73 },
74 };
75
76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
77 .mult = 1,
78 .div = 2,
79 .hw.init = &(struct clk_init_data){
80 .name = "gcc_pll0_main_div_cdiv",
81 .parent_hws = (const struct clk_hw*[]){
82 &gpll0.clkr.hw,
83 },
84 .num_parents = 1,
85 .ops = &clk_fixed_factor_ops,
86 },
87 };
88
89 static struct clk_alpha_pll gpll1 = {
90 .offset = 0x01000,
91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
92 .clkr = {
93 .enable_reg = 0x52010,
94 .enable_mask = BIT(1),
95 .hw.init = &(struct clk_init_data){
96 .name = "gpll1",
97 .parent_data = &(const struct clk_parent_data){
98 .fw_name = "bi_tcxo",
99 .name = "bi_tcxo",
100 },
101 .num_parents = 1,
102 .ops = &clk_alpha_pll_fixed_fabia_ops,
103 },
104 },
105 };
106
107 static struct clk_alpha_pll gpll4 = {
108 .offset = 0x76000,
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
110 .clkr = {
111 .enable_reg = 0x52010,
112 .enable_mask = BIT(4),
113 .hw.init = &(struct clk_init_data){
114 .name = "gpll4",
115 .parent_data = &(const struct clk_parent_data){
116 .fw_name = "bi_tcxo",
117 .name = "bi_tcxo",
118 },
119 .num_parents = 1,
120 .ops = &clk_alpha_pll_fixed_fabia_ops,
121 },
122 },
123 };
124
125 static struct clk_alpha_pll gpll6 = {
126 .offset = 0x13000,
127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
128 .clkr = {
129 .enable_reg = 0x52010,
130 .enable_mask = BIT(6),
131 .hw.init = &(struct clk_init_data){
132 .name = "gpll6",
133 .parent_data = &(const struct clk_parent_data){
134 .fw_name = "bi_tcxo",
135 .name = "bi_tcxo",
136 },
137 .num_parents = 1,
138 .ops = &clk_alpha_pll_fixed_fabia_ops,
139 },
140 },
141 };
142
143 static struct clk_alpha_pll gpll7 = {
144 .offset = 0x27000,
145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
146 .clkr = {
147 .enable_reg = 0x52010,
148 .enable_mask = BIT(7),
149 .hw.init = &(struct clk_init_data){
150 .name = "gpll7",
151 .parent_data = &(const struct clk_parent_data){
152 .fw_name = "bi_tcxo",
153 .name = "bi_tcxo",
154 },
155 .num_parents = 1,
156 .ops = &clk_alpha_pll_fixed_fabia_ops,
157 },
158 },
159 };
160
161 static const struct parent_map gcc_parent_map_0[] = {
162 { P_BI_TCXO, 0 },
163 { P_GPLL0_OUT_MAIN, 1 },
164 { P_GPLL0_OUT_EVEN, 6 },
165 { P_CORE_BI_PLL_TEST_SE, 7 },
166 };
167
168 static const struct clk_parent_data gcc_parent_data_0[] = {
169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
170 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0_out_even.clkr.hw },
172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
173 };
174
175 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
177 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0_out_even.clkr.hw },
179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
180 };
181
182 static const struct parent_map gcc_parent_map_1[] = {
183 { P_BI_TCXO, 0 },
184 { P_GPLL0_OUT_MAIN, 1 },
185 { P_GPLL6_OUT_MAIN, 2 },
186 { P_GPLL0_OUT_EVEN, 6 },
187 { P_CORE_BI_PLL_TEST_SE, 7 },
188 };
189
190 static const struct clk_parent_data gcc_parent_data_1[] = {
191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
192 { .hw = &gpll0.clkr.hw },
193 { .hw = &gpll6.clkr.hw },
194 { .hw = &gpll0_out_even.clkr.hw },
195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
196 };
197
198 static const struct parent_map gcc_parent_map_2[] = {
199 { P_BI_TCXO, 0 },
200 { P_GPLL0_OUT_MAIN, 1 },
201 { P_GPLL1_OUT_MAIN, 4 },
202 { P_GPLL4_OUT_MAIN, 5 },
203 { P_GPLL0_OUT_EVEN, 6 },
204 { P_CORE_BI_PLL_TEST_SE, 7 },
205 };
206
207 static const struct clk_parent_data gcc_parent_data_2[] = {
208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
209 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll1.clkr.hw },
211 { .hw = &gpll4.clkr.hw },
212 { .hw = &gpll0_out_even.clkr.hw },
213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
214 };
215
216 static const struct parent_map gcc_parent_map_3[] = {
217 { P_BI_TCXO, 0 },
218 { P_GPLL0_OUT_MAIN, 1 },
219 { P_CORE_BI_PLL_TEST_SE, 7 },
220 };
221
222 static const struct clk_parent_data gcc_parent_data_3[] = {
223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
224 { .hw = &gpll0.clkr.hw },
225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
226 };
227
228 static const struct parent_map gcc_parent_map_4[] = {
229 { P_BI_TCXO, 0 },
230 { P_GPLL0_OUT_MAIN, 1 },
231 { P_SLEEP_CLK, 5 },
232 { P_GPLL0_OUT_EVEN, 6 },
233 { P_CORE_BI_PLL_TEST_SE, 7 },
234 };
235
236 static const struct clk_parent_data gcc_parent_data_4[] = {
237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
238 { .hw = &gpll0.clkr.hw },
239 { .fw_name = "sleep_clk", .name = "sleep_clk" },
240 { .hw = &gpll0_out_even.clkr.hw },
241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
242 };
243
244 static const struct parent_map gcc_parent_map_5[] = {
245 { P_BI_TCXO, 0 },
246 { P_GPLL0_OUT_MAIN, 1 },
247 { P_GPLL7_OUT_MAIN, 3 },
248 { P_GPLL0_OUT_EVEN, 6 },
249 { P_CORE_BI_PLL_TEST_SE, 7 },
250 };
251
252 static const struct clk_parent_data gcc_parent_data_5[] = {
253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
254 { .hw = &gpll0.clkr.hw },
255 { .hw = &gpll7.clkr.hw },
256 { .hw = &gpll0_out_even.clkr.hw },
257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
258 };
259
260 static const struct parent_map gcc_parent_map_6[] = {
261 { P_BI_TCXO, 0 },
262 { P_GPLL0_OUT_MAIN, 1 },
263 { P_SLEEP_CLK, 5 },
264 { P_CORE_BI_PLL_TEST_SE, 7 },
265 };
266
267 static const struct clk_parent_data gcc_parent_data_6[] = {
268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
269 { .hw = &gpll0.clkr.hw },
270 { .fw_name = "sleep_clk", .name = "sleep_clk" },
271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
272 };
273
274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
275 F(19200000, P_BI_TCXO, 1, 0, 0),
276 { }
277 };
278
279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
280 .cmd_rcgr = 0x48014,
281 .mnd_width = 0,
282 .hid_width = 5,
283 .parent_map = gcc_parent_map_0,
284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "gcc_cpuss_ahb_clk_src",
287 .parent_data = gcc_parent_data_0_ao,
288 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
289 .flags = CLK_SET_RATE_PARENT,
290 .ops = &clk_rcg2_ops,
291 },
292 };
293
294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
300 { }
301 };
302
303 static struct clk_rcg2 gcc_gp1_clk_src = {
304 .cmd_rcgr = 0x64004,
305 .mnd_width = 8,
306 .hid_width = 5,
307 .parent_map = gcc_parent_map_4,
308 .freq_tbl = ftbl_gcc_gp1_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "gcc_gp1_clk_src",
311 .parent_data = gcc_parent_data_4,
312 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
313 .ops = &clk_rcg2_ops,
314 },
315 };
316
317 static struct clk_rcg2 gcc_gp2_clk_src = {
318 .cmd_rcgr = 0x65004,
319 .mnd_width = 8,
320 .hid_width = 5,
321 .parent_map = gcc_parent_map_4,
322 .freq_tbl = ftbl_gcc_gp1_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "gcc_gp2_clk_src",
325 .parent_data = gcc_parent_data_4,
326 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
327 .ops = &clk_rcg2_ops,
328 },
329 };
330
331 static struct clk_rcg2 gcc_gp3_clk_src = {
332 .cmd_rcgr = 0x66004,
333 .mnd_width = 8,
334 .hid_width = 5,
335 .parent_map = gcc_parent_map_4,
336 .freq_tbl = ftbl_gcc_gp1_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "gcc_gp3_clk_src",
339 .parent_data = gcc_parent_data_4,
340 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
341 .ops = &clk_rcg2_ops,
342 },
343 };
344
345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
348 { }
349 };
350
351 static struct clk_rcg2 gcc_pdm2_clk_src = {
352 .cmd_rcgr = 0x33010,
353 .mnd_width = 0,
354 .hid_width = 5,
355 .parent_map = gcc_parent_map_0,
356 .freq_tbl = ftbl_gcc_pdm2_clk_src,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "gcc_pdm2_clk_src",
359 .parent_data = gcc_parent_data_0,
360 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
361 .ops = &clk_rcg2_ops,
362 },
363 };
364
365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
369 { }
370 };
371
372 static struct clk_rcg2 gcc_qspi_core_clk_src = {
373 .cmd_rcgr = 0x4b00c,
374 .mnd_width = 0,
375 .hid_width = 5,
376 .parent_map = gcc_parent_map_2,
377 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "gcc_qspi_core_clk_src",
380 .parent_data = gcc_parent_data_2,
381 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
382 .ops = &clk_rcg2_ops,
383 },
384 };
385
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
389 F(19200000, P_BI_TCXO, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
394 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
396 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
397 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
399 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
400 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
401 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
404 { }
405 };
406
407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
408 .name = "gcc_qupv3_wrap0_s0_clk_src",
409 .parent_data = gcc_parent_data_1,
410 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
411 .ops = &clk_rcg2_ops,
412 };
413
414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
415 .cmd_rcgr = 0x17034,
416 .mnd_width = 16,
417 .hid_width = 5,
418 .parent_map = gcc_parent_map_1,
419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
420 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
421 };
422
423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
424 .name = "gcc_qupv3_wrap0_s1_clk_src",
425 .parent_data = gcc_parent_data_1,
426 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
427 .ops = &clk_rcg2_ops,
428 };
429
430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
431 .cmd_rcgr = 0x17164,
432 .mnd_width = 16,
433 .hid_width = 5,
434 .parent_map = gcc_parent_map_1,
435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
436 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
437 };
438
439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
440 .name = "gcc_qupv3_wrap0_s2_clk_src",
441 .parent_data = gcc_parent_data_1,
442 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
443 .ops = &clk_rcg2_ops,
444 };
445
446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
447 .cmd_rcgr = 0x17294,
448 .mnd_width = 16,
449 .hid_width = 5,
450 .parent_map = gcc_parent_map_1,
451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
452 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
453 };
454
455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
456 .name = "gcc_qupv3_wrap0_s3_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .ops = &clk_rcg2_ops,
460 };
461
462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
463 .cmd_rcgr = 0x173c4,
464 .mnd_width = 16,
465 .hid_width = 5,
466 .parent_map = gcc_parent_map_1,
467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
468 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
469 };
470
471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
472 .name = "gcc_qupv3_wrap0_s4_clk_src",
473 .parent_data = gcc_parent_data_1,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
475 .ops = &clk_rcg2_ops,
476 };
477
478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
479 .cmd_rcgr = 0x174f4,
480 .mnd_width = 16,
481 .hid_width = 5,
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
484 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
485 };
486
487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
488 .name = "gcc_qupv3_wrap0_s5_clk_src",
489 .parent_data = gcc_parent_data_1,
490 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
491 .ops = &clk_rcg2_ops,
492 };
493
494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
495 .cmd_rcgr = 0x17624,
496 .mnd_width = 16,
497 .hid_width = 5,
498 .parent_map = gcc_parent_map_1,
499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
500 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
501 };
502
503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
504 .name = "gcc_qupv3_wrap1_s0_clk_src",
505 .parent_data = gcc_parent_data_1,
506 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
507 .ops = &clk_rcg2_ops,
508 };
509
510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
511 .cmd_rcgr = 0x18018,
512 .mnd_width = 16,
513 .hid_width = 5,
514 .parent_map = gcc_parent_map_1,
515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
516 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
517 };
518
519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
520 .name = "gcc_qupv3_wrap1_s1_clk_src",
521 .parent_data = gcc_parent_data_1,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
523 .ops = &clk_rcg2_ops,
524 };
525
526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
527 .cmd_rcgr = 0x18148,
528 .mnd_width = 16,
529 .hid_width = 5,
530 .parent_map = gcc_parent_map_1,
531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
532 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
533 };
534
535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
536 .name = "gcc_qupv3_wrap1_s2_clk_src",
537 .parent_data = gcc_parent_data_1,
538 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
539 .ops = &clk_rcg2_ops,
540 };
541
542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
543 .cmd_rcgr = 0x18278,
544 .mnd_width = 16,
545 .hid_width = 5,
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
548 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
549 };
550
551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
552 .name = "gcc_qupv3_wrap1_s3_clk_src",
553 .parent_data = gcc_parent_data_1,
554 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
555 .ops = &clk_rcg2_ops,
556 };
557
558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
559 .cmd_rcgr = 0x183a8,
560 .mnd_width = 16,
561 .hid_width = 5,
562 .parent_map = gcc_parent_map_1,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
565 };
566
567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
568 .name = "gcc_qupv3_wrap1_s4_clk_src",
569 .parent_data = gcc_parent_data_1,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
571 .ops = &clk_rcg2_ops,
572 };
573
574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
575 .cmd_rcgr = 0x184d8,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_1,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
581 };
582
583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
584 .name = "gcc_qupv3_wrap1_s5_clk_src",
585 .parent_data = gcc_parent_data_1,
586 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
587 .ops = &clk_rcg2_ops,
588 };
589
590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
591 .cmd_rcgr = 0x18608,
592 .mnd_width = 16,
593 .hid_width = 5,
594 .parent_map = gcc_parent_map_1,
595 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
596 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
597 };
598
599
600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
601 F(144000, P_BI_TCXO, 16, 3, 25),
602 F(400000, P_BI_TCXO, 12, 1, 4),
603 F(19200000, P_BI_TCXO, 1, 0, 0),
604 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
605 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
610 { }
611 };
612
613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
614 .cmd_rcgr = 0x12028,
615 .mnd_width = 8,
616 .hid_width = 5,
617 .parent_map = gcc_parent_map_1,
618 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "gcc_sdcc1_apps_clk_src",
621 .parent_data = gcc_parent_data_1,
622 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
623 .ops = &clk_rcg2_floor_ops,
624 },
625 };
626
627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
632 { }
633 };
634
635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
636 .cmd_rcgr = 0x12010,
637 .mnd_width = 0,
638 .hid_width = 5,
639 .parent_map = gcc_parent_map_0,
640 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "gcc_sdcc1_ice_core_clk_src",
643 .parent_data = gcc_parent_data_0,
644 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
645 .ops = &clk_rcg2_ops,
646 },
647 };
648
649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
650 F(400000, P_BI_TCXO, 12, 1, 4),
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
655 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
656 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
657 { }
658 };
659
660 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
661 .cmd_rcgr = 0x1400c,
662 .mnd_width = 8,
663 .hid_width = 5,
664 .parent_map = gcc_parent_map_5,
665 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "gcc_sdcc2_apps_clk_src",
668 .parent_data = gcc_parent_data_5,
669 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
670 .flags = CLK_OPS_PARENT_ENABLE,
671 .ops = &clk_rcg2_floor_ops,
672 },
673 };
674
675 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
676 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
677 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
678 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
679 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
680 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
681 { }
682 };
683
684 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
685 .cmd_rcgr = 0x77020,
686 .mnd_width = 8,
687 .hid_width = 5,
688 .parent_map = gcc_parent_map_0,
689 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "gcc_ufs_phy_axi_clk_src",
692 .parent_data = gcc_parent_data_0,
693 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
694 .ops = &clk_rcg2_ops,
695 },
696 };
697
698 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
699 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
700 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
701 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
702 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
703 { }
704 };
705
706 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
707 .cmd_rcgr = 0x77048,
708 .mnd_width = 0,
709 .hid_width = 5,
710 .parent_map = gcc_parent_map_0,
711 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "gcc_ufs_phy_ice_core_clk_src",
714 .parent_data = gcc_parent_data_0,
715 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
716 .ops = &clk_rcg2_ops,
717 },
718 };
719
720 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
721 F(9600000, P_BI_TCXO, 2, 0, 0),
722 F(19200000, P_BI_TCXO, 1, 0, 0),
723 { }
724 };
725
726 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
727 .cmd_rcgr = 0x77098,
728 .mnd_width = 0,
729 .hid_width = 5,
730 .parent_map = gcc_parent_map_3,
731 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
732 .clkr.hw.init = &(struct clk_init_data){
733 .name = "gcc_ufs_phy_phy_aux_clk_src",
734 .parent_data = gcc_parent_data_3,
735 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
736 .ops = &clk_rcg2_ops,
737 },
738 };
739
740 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
741 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
742 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
743 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
744 { }
745 };
746
747 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
748 .cmd_rcgr = 0x77060,
749 .mnd_width = 0,
750 .hid_width = 5,
751 .parent_map = gcc_parent_map_0,
752 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
753 .clkr.hw.init = &(struct clk_init_data){
754 .name = "gcc_ufs_phy_unipro_core_clk_src",
755 .parent_data = gcc_parent_data_0,
756 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
757 .ops = &clk_rcg2_ops,
758 },
759 };
760
761 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
762 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
763 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
764 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
765 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
766 { }
767 };
768
769 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
770 .cmd_rcgr = 0xf01c,
771 .mnd_width = 8,
772 .hid_width = 5,
773 .parent_map = gcc_parent_map_0,
774 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "gcc_usb30_prim_master_clk_src",
777 .parent_data = gcc_parent_data_0,
778 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
779 .ops = &clk_rcg2_ops,
780 },
781 };
782
783 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
784 F(19200000, P_BI_TCXO, 1, 0, 0),
785 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
786 { }
787 };
788
789 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
790 .cmd_rcgr = 0xf034,
791 .mnd_width = 0,
792 .hid_width = 5,
793 .parent_map = gcc_parent_map_0,
794 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "gcc_usb30_prim_mock_utmi_clk_src",
797 .parent_data = gcc_parent_data_0,
798 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
799 .ops = &clk_rcg2_ops,
800 },
801 };
802
803 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
804 F(19200000, P_BI_TCXO, 1, 0, 0),
805 { }
806 };
807
808 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
809 .cmd_rcgr = 0xf060,
810 .mnd_width = 0,
811 .hid_width = 5,
812 .parent_map = gcc_parent_map_6,
813 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "gcc_usb3_prim_phy_aux_clk_src",
816 .parent_data = gcc_parent_data_6,
817 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
818 .ops = &clk_rcg2_ops,
819 },
820 };
821
822 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
823 F(4800000, P_BI_TCXO, 4, 0, 0),
824 F(19200000, P_BI_TCXO, 1, 0, 0),
825 { }
826 };
827
828 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
829 .cmd_rcgr = 0x3d030,
830 .mnd_width = 0,
831 .hid_width = 5,
832 .parent_map = gcc_parent_map_3,
833 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "gcc_sec_ctrl_clk_src",
836 .parent_data = gcc_parent_data_3,
837 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
838 .ops = &clk_rcg2_ops,
839 },
840 };
841
842 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
843 .halt_reg = 0x82024,
844 .halt_check = BRANCH_HALT_DELAY,
845 .hwcg_reg = 0x82024,
846 .hwcg_bit = 1,
847 .clkr = {
848 .enable_reg = 0x82024,
849 .enable_mask = BIT(0),
850 .hw.init = &(struct clk_init_data){
851 .name = "gcc_aggre_ufs_phy_axi_clk",
852 .parent_hws = (const struct clk_hw*[]){
853 &gcc_ufs_phy_axi_clk_src.clkr.hw,
854 },
855 .num_parents = 1,
856 .flags = CLK_SET_RATE_PARENT,
857 .ops = &clk_branch2_ops,
858 },
859 },
860 };
861
862 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
863 .halt_reg = 0x8201c,
864 .halt_check = BRANCH_HALT,
865 .clkr = {
866 .enable_reg = 0x8201c,
867 .enable_mask = BIT(0),
868 .hw.init = &(struct clk_init_data){
869 .name = "gcc_aggre_usb3_prim_axi_clk",
870 .parent_hws = (const struct clk_hw*[]){
871 &gcc_usb30_prim_master_clk_src.clkr.hw,
872 },
873 .num_parents = 1,
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_branch2_ops,
876 },
877 },
878 };
879
880 static struct clk_branch gcc_boot_rom_ahb_clk = {
881 .halt_reg = 0x38004,
882 .halt_check = BRANCH_HALT_VOTED,
883 .hwcg_reg = 0x38004,
884 .hwcg_bit = 1,
885 .clkr = {
886 .enable_reg = 0x52000,
887 .enable_mask = BIT(10),
888 .hw.init = &(struct clk_init_data){
889 .name = "gcc_boot_rom_ahb_clk",
890 .ops = &clk_branch2_ops,
891 },
892 },
893 };
894
895 static struct clk_branch gcc_camera_hf_axi_clk = {
896 .halt_reg = 0xb020,
897 .halt_check = BRANCH_HALT,
898 .clkr = {
899 .enable_reg = 0xb020,
900 .enable_mask = BIT(0),
901 .hw.init = &(struct clk_init_data){
902 .name = "gcc_camera_hf_axi_clk",
903 .ops = &clk_branch2_ops,
904 },
905 },
906 };
907
908 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
909 .halt_reg = 0xb080,
910 .halt_check = BRANCH_HALT,
911 .hwcg_reg = 0xb080,
912 .hwcg_bit = 1,
913 .clkr = {
914 .enable_reg = 0xb080,
915 .enable_mask = BIT(0),
916 .hw.init = &(struct clk_init_data){
917 .name = "gcc_camera_throttle_hf_axi_clk",
918 .ops = &clk_branch2_ops,
919 },
920 },
921 };
922
923 static struct clk_branch gcc_ce1_ahb_clk = {
924 .halt_reg = 0x4100c,
925 .halt_check = BRANCH_HALT_VOTED,
926 .hwcg_reg = 0x4100c,
927 .hwcg_bit = 1,
928 .clkr = {
929 .enable_reg = 0x52000,
930 .enable_mask = BIT(3),
931 .hw.init = &(struct clk_init_data){
932 .name = "gcc_ce1_ahb_clk",
933 .ops = &clk_branch2_ops,
934 },
935 },
936 };
937
938 static struct clk_branch gcc_ce1_axi_clk = {
939 .halt_reg = 0x41008,
940 .halt_check = BRANCH_HALT_VOTED,
941 .clkr = {
942 .enable_reg = 0x52000,
943 .enable_mask = BIT(4),
944 .hw.init = &(struct clk_init_data){
945 .name = "gcc_ce1_axi_clk",
946 .ops = &clk_branch2_ops,
947 },
948 },
949 };
950
951 static struct clk_branch gcc_ce1_clk = {
952 .halt_reg = 0x41004,
953 .halt_check = BRANCH_HALT_VOTED,
954 .clkr = {
955 .enable_reg = 0x52000,
956 .enable_mask = BIT(5),
957 .hw.init = &(struct clk_init_data){
958 .name = "gcc_ce1_clk",
959 .ops = &clk_branch2_ops,
960 },
961 },
962 };
963
964 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
965 .halt_reg = 0x502c,
966 .halt_check = BRANCH_HALT,
967 .clkr = {
968 .enable_reg = 0x502c,
969 .enable_mask = BIT(0),
970 .hw.init = &(struct clk_init_data){
971 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
972 .parent_hws = (const struct clk_hw*[]){
973 &gcc_usb30_prim_master_clk_src.clkr.hw,
974 },
975 .num_parents = 1,
976 .flags = CLK_SET_RATE_PARENT,
977 .ops = &clk_branch2_ops,
978 },
979 },
980 };
981
982 /* For CPUSS functionality the AHB clock needs to be left enabled */
983 static struct clk_branch gcc_cpuss_ahb_clk = {
984 .halt_reg = 0x48000,
985 .halt_check = BRANCH_HALT_VOTED,
986 .clkr = {
987 .enable_reg = 0x52000,
988 .enable_mask = BIT(21),
989 .hw.init = &(struct clk_init_data){
990 .name = "gcc_cpuss_ahb_clk",
991 .parent_hws = (const struct clk_hw*[]){
992 &gcc_cpuss_ahb_clk_src.clkr.hw,
993 },
994 .num_parents = 1,
995 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
996 .ops = &clk_branch2_ops,
997 },
998 },
999 };
1000
1001 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1002 .halt_reg = 0x48008,
1003 .halt_check = BRANCH_HALT,
1004 .clkr = {
1005 .enable_reg = 0x48008,
1006 .enable_mask = BIT(0),
1007 .hw.init = &(struct clk_init_data){
1008 .name = "gcc_cpuss_rbcpr_clk",
1009 .ops = &clk_branch2_ops,
1010 },
1011 },
1012 };
1013
1014 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1015 .halt_reg = 0x4452c,
1016 .halt_check = BRANCH_VOTED,
1017 .clkr = {
1018 .enable_reg = 0x4452c,
1019 .enable_mask = BIT(0),
1020 .hw.init = &(struct clk_init_data){
1021 .name = "gcc_ddrss_gpu_axi_clk",
1022 .ops = &clk_branch2_ops,
1023 },
1024 },
1025 };
1026
1027 static struct clk_branch gcc_disp_gpll0_clk_src = {
1028 .halt_check = BRANCH_HALT_DELAY,
1029 .clkr = {
1030 .enable_reg = 0x52000,
1031 .enable_mask = BIT(18),
1032 .hw.init = &(struct clk_init_data){
1033 .name = "gcc_disp_gpll0_clk_src",
1034 .parent_hws = (const struct clk_hw*[]){
1035 &gpll0.clkr.hw,
1036 },
1037 .num_parents = 1,
1038 .ops = &clk_branch2_aon_ops,
1039 },
1040 },
1041 };
1042
1043 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1044 .halt_check = BRANCH_HALT_DELAY,
1045 .clkr = {
1046 .enable_reg = 0x52000,
1047 .enable_mask = BIT(19),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gcc_disp_gpll0_div_clk_src",
1050 .parent_hws = (const struct clk_hw*[]){
1051 &gcc_pll0_main_div_cdiv.hw,
1052 },
1053 .num_parents = 1,
1054 .ops = &clk_branch2_ops,
1055 },
1056 },
1057 };
1058
1059 static struct clk_branch gcc_disp_hf_axi_clk = {
1060 .halt_reg = 0xb024,
1061 .halt_check = BRANCH_HALT,
1062 .clkr = {
1063 .enable_reg = 0xb024,
1064 .enable_mask = BIT(0),
1065 .hw.init = &(struct clk_init_data){
1066 .name = "gcc_disp_hf_axi_clk",
1067 .ops = &clk_branch2_ops,
1068 },
1069 },
1070 };
1071
1072 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1073 .halt_reg = 0xb084,
1074 .halt_check = BRANCH_HALT,
1075 .hwcg_reg = 0xb084,
1076 .hwcg_bit = 1,
1077 .clkr = {
1078 .enable_reg = 0xb084,
1079 .enable_mask = BIT(0),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "gcc_disp_throttle_hf_axi_clk",
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085 };
1086
1087 static struct clk_branch gcc_gp1_clk = {
1088 .halt_reg = 0x64000,
1089 .halt_check = BRANCH_HALT,
1090 .clkr = {
1091 .enable_reg = 0x64000,
1092 .enable_mask = BIT(0),
1093 .hw.init = &(struct clk_init_data){
1094 .name = "gcc_gp1_clk",
1095 .parent_hws = (const struct clk_hw*[]){
1096 &gcc_gp1_clk_src.clkr.hw,
1097 },
1098 .num_parents = 1,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_branch2_ops,
1101 },
1102 },
1103 };
1104
1105 static struct clk_branch gcc_gp2_clk = {
1106 .halt_reg = 0x65000,
1107 .halt_check = BRANCH_HALT,
1108 .clkr = {
1109 .enable_reg = 0x65000,
1110 .enable_mask = BIT(0),
1111 .hw.init = &(struct clk_init_data){
1112 .name = "gcc_gp2_clk",
1113 .parent_hws = (const struct clk_hw*[]){
1114 &gcc_gp2_clk_src.clkr.hw,
1115 },
1116 .num_parents = 1,
1117 .flags = CLK_SET_RATE_PARENT,
1118 .ops = &clk_branch2_ops,
1119 },
1120 },
1121 };
1122
1123 static struct clk_branch gcc_gp3_clk = {
1124 .halt_reg = 0x66000,
1125 .halt_check = BRANCH_HALT,
1126 .clkr = {
1127 .enable_reg = 0x66000,
1128 .enable_mask = BIT(0),
1129 .hw.init = &(struct clk_init_data){
1130 .name = "gcc_gp3_clk",
1131 .parent_hws = (const struct clk_hw*[]){
1132 &gcc_gp3_clk_src.clkr.hw,
1133 },
1134 .num_parents = 1,
1135 .flags = CLK_SET_RATE_PARENT,
1136 .ops = &clk_branch2_ops,
1137 },
1138 },
1139 };
1140
1141 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1142 .halt_check = BRANCH_HALT_DELAY,
1143 .clkr = {
1144 .enable_reg = 0x52000,
1145 .enable_mask = BIT(15),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gcc_gpu_gpll0_clk_src",
1148 .parent_hws = (const struct clk_hw*[]){
1149 &gpll0.clkr.hw,
1150 },
1151 .num_parents = 1,
1152 .ops = &clk_branch2_ops,
1153 },
1154 },
1155 };
1156
1157 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1158 .halt_check = BRANCH_HALT_DELAY,
1159 .clkr = {
1160 .enable_reg = 0x52000,
1161 .enable_mask = BIT(16),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_gpu_gpll0_div_clk_src",
1164 .parent_hws = (const struct clk_hw*[]){
1165 &gcc_pll0_main_div_cdiv.hw,
1166 },
1167 .num_parents = 1,
1168 .ops = &clk_branch2_ops,
1169 },
1170 },
1171 };
1172
1173 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1174 .halt_reg = 0x7100c,
1175 .halt_check = BRANCH_VOTED,
1176 .clkr = {
1177 .enable_reg = 0x7100c,
1178 .enable_mask = BIT(0),
1179 .hw.init = &(struct clk_init_data){
1180 .name = "gcc_gpu_memnoc_gfx_clk",
1181 .ops = &clk_branch2_ops,
1182 },
1183 },
1184 };
1185
1186 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1187 .halt_reg = 0x71018,
1188 .halt_check = BRANCH_HALT,
1189 .clkr = {
1190 .enable_reg = 0x71018,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1194 .ops = &clk_branch2_ops,
1195 },
1196 },
1197 };
1198
1199 static struct clk_branch gcc_npu_axi_clk = {
1200 .halt_reg = 0x4d008,
1201 .halt_check = BRANCH_HALT,
1202 .clkr = {
1203 .enable_reg = 0x4d008,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "gcc_npu_axi_clk",
1207 .ops = &clk_branch2_ops,
1208 },
1209 },
1210 };
1211
1212 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1213 .halt_reg = 0x73008,
1214 .halt_check = BRANCH_HALT,
1215 .clkr = {
1216 .enable_reg = 0x73008,
1217 .enable_mask = BIT(0),
1218 .hw.init = &(struct clk_init_data){
1219 .name = "gcc_npu_bwmon_axi_clk",
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223 };
1224
1225 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1226 .halt_reg = 0x73018,
1227 .halt_check = BRANCH_HALT,
1228 .clkr = {
1229 .enable_reg = 0x73018,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236 };
1237
1238 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1239 .halt_reg = 0x7301c,
1240 .halt_check = BRANCH_HALT,
1241 .clkr = {
1242 .enable_reg = 0x7301c,
1243 .enable_mask = BIT(0),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1246 .ops = &clk_branch2_ops,
1247 },
1248 },
1249 };
1250
1251 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1252 .halt_reg = 0x4d004,
1253 .halt_check = BRANCH_HALT,
1254 .hwcg_reg = 0x4d004,
1255 .hwcg_bit = 1,
1256 .clkr = {
1257 .enable_reg = 0x4d004,
1258 .enable_mask = BIT(0),
1259 .hw.init = &(struct clk_init_data){
1260 .name = "gcc_npu_cfg_ahb_clk",
1261 .ops = &clk_branch2_ops,
1262 },
1263 },
1264 };
1265
1266 static struct clk_branch gcc_npu_dma_clk = {
1267 .halt_reg = 0x4d1a0,
1268 .halt_check = BRANCH_HALT,
1269 .hwcg_reg = 0x4d1a0,
1270 .hwcg_bit = 1,
1271 .clkr = {
1272 .enable_reg = 0x4d1a0,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "gcc_npu_dma_clk",
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279 };
1280
1281 static struct clk_branch gcc_npu_gpll0_clk_src = {
1282 .halt_check = BRANCH_HALT_DELAY,
1283 .clkr = {
1284 .enable_reg = 0x52000,
1285 .enable_mask = BIT(25),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "gcc_npu_gpll0_clk_src",
1288 .parent_hws = (const struct clk_hw*[]){
1289 &gpll0.clkr.hw,
1290 },
1291 .num_parents = 1,
1292 .ops = &clk_branch2_ops,
1293 },
1294 },
1295 };
1296
1297 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1298 .halt_check = BRANCH_HALT_DELAY,
1299 .clkr = {
1300 .enable_reg = 0x52000,
1301 .enable_mask = BIT(26),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_npu_gpll0_div_clk_src",
1304 .parent_hws = (const struct clk_hw*[]){
1305 &gcc_pll0_main_div_cdiv.hw,
1306 },
1307 .num_parents = 1,
1308 .flags = CLK_SET_RATE_PARENT,
1309 .ops = &clk_branch2_ops,
1310 },
1311 },
1312 };
1313
1314 static struct clk_branch gcc_pdm2_clk = {
1315 .halt_reg = 0x3300c,
1316 .halt_check = BRANCH_HALT,
1317 .clkr = {
1318 .enable_reg = 0x3300c,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "gcc_pdm2_clk",
1322 .parent_hws = (const struct clk_hw*[]){
1323 &gcc_pdm2_clk_src.clkr.hw,
1324 },
1325 .num_parents = 1,
1326 .flags = CLK_SET_RATE_PARENT,
1327 .ops = &clk_branch2_ops,
1328 },
1329 },
1330 };
1331
1332 static struct clk_branch gcc_pdm_ahb_clk = {
1333 .halt_reg = 0x33004,
1334 .halt_check = BRANCH_HALT,
1335 .hwcg_reg = 0x33004,
1336 .hwcg_bit = 1,
1337 .clkr = {
1338 .enable_reg = 0x33004,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "gcc_pdm_ahb_clk",
1342 .ops = &clk_branch2_ops,
1343 },
1344 },
1345 };
1346
1347 static struct clk_branch gcc_pdm_xo4_clk = {
1348 .halt_reg = 0x33008,
1349 .halt_check = BRANCH_HALT,
1350 .clkr = {
1351 .enable_reg = 0x33008,
1352 .enable_mask = BIT(0),
1353 .hw.init = &(struct clk_init_data){
1354 .name = "gcc_pdm_xo4_clk",
1355 .ops = &clk_branch2_ops,
1356 },
1357 },
1358 };
1359
1360 static struct clk_branch gcc_prng_ahb_clk = {
1361 .halt_reg = 0x34004,
1362 .halt_check = BRANCH_HALT_VOTED,
1363 .hwcg_reg = 0x34004,
1364 .hwcg_bit = 1,
1365 .clkr = {
1366 .enable_reg = 0x52000,
1367 .enable_mask = BIT(13),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gcc_prng_ahb_clk",
1370 .ops = &clk_branch2_ops,
1371 },
1372 },
1373 };
1374
1375 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1376 .halt_reg = 0x4b004,
1377 .halt_check = BRANCH_HALT,
1378 .hwcg_reg = 0x4b004,
1379 .hwcg_bit = 1,
1380 .clkr = {
1381 .enable_reg = 0x4b004,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1385 .ops = &clk_branch2_ops,
1386 },
1387 },
1388 };
1389
1390 static struct clk_branch gcc_qspi_core_clk = {
1391 .halt_reg = 0x4b008,
1392 .halt_check = BRANCH_HALT,
1393 .clkr = {
1394 .enable_reg = 0x4b008,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "gcc_qspi_core_clk",
1398 .parent_hws = (const struct clk_hw*[]){
1399 &gcc_qspi_core_clk_src.clkr.hw,
1400 },
1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1404 },
1405 },
1406 };
1407
1408 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1409 .halt_reg = 0x17014,
1410 .halt_check = BRANCH_HALT_VOTED,
1411 .clkr = {
1412 .enable_reg = 0x52008,
1413 .enable_mask = BIT(9),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "gcc_qupv3_wrap0_core_2x_clk",
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1422 .halt_reg = 0x1700c,
1423 .halt_check = BRANCH_HALT_VOTED,
1424 .clkr = {
1425 .enable_reg = 0x52008,
1426 .enable_mask = BIT(8),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_qupv3_wrap0_core_clk",
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432 };
1433
1434 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1435 .halt_reg = 0x17030,
1436 .halt_check = BRANCH_HALT_VOTED,
1437 .clkr = {
1438 .enable_reg = 0x52008,
1439 .enable_mask = BIT(10),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_qupv3_wrap0_s0_clk",
1442 .parent_hws = (const struct clk_hw*[]){
1443 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1444 },
1445 .num_parents = 1,
1446 .flags = CLK_SET_RATE_PARENT,
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1453 .halt_reg = 0x17160,
1454 .halt_check = BRANCH_HALT_VOTED,
1455 .clkr = {
1456 .enable_reg = 0x52008,
1457 .enable_mask = BIT(11),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gcc_qupv3_wrap0_s1_clk",
1460 .parent_hws = (const struct clk_hw*[]){
1461 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1462 },
1463 .num_parents = 1,
1464 .flags = CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1471 .halt_reg = 0x17290,
1472 .halt_check = BRANCH_HALT_VOTED,
1473 .clkr = {
1474 .enable_reg = 0x52008,
1475 .enable_mask = BIT(12),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "gcc_qupv3_wrap0_s2_clk",
1478 .parent_hws = (const struct clk_hw*[]){
1479 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1480 },
1481 .num_parents = 1,
1482 .flags = CLK_SET_RATE_PARENT,
1483 .ops = &clk_branch2_ops,
1484 },
1485 },
1486 };
1487
1488 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1489 .halt_reg = 0x173c0,
1490 .halt_check = BRANCH_HALT_VOTED,
1491 .clkr = {
1492 .enable_reg = 0x52008,
1493 .enable_mask = BIT(13),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "gcc_qupv3_wrap0_s3_clk",
1496 .parent_hws = (const struct clk_hw*[]){
1497 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1498 },
1499 .num_parents = 1,
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1502 },
1503 },
1504 };
1505
1506 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1507 .halt_reg = 0x174f0,
1508 .halt_check = BRANCH_HALT_VOTED,
1509 .clkr = {
1510 .enable_reg = 0x52008,
1511 .enable_mask = BIT(14),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "gcc_qupv3_wrap0_s4_clk",
1514 .parent_hws = (const struct clk_hw*[]){
1515 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1516 },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522 };
1523
1524 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1525 .halt_reg = 0x17620,
1526 .halt_check = BRANCH_HALT_VOTED,
1527 .clkr = {
1528 .enable_reg = 0x52008,
1529 .enable_mask = BIT(15),
1530 .hw.init = &(struct clk_init_data){
1531 .name = "gcc_qupv3_wrap0_s5_clk",
1532 .parent_hws = (const struct clk_hw*[]){
1533 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1534 },
1535 .num_parents = 1,
1536 .flags = CLK_SET_RATE_PARENT,
1537 .ops = &clk_branch2_ops,
1538 },
1539 },
1540 };
1541
1542 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1543 .halt_reg = 0x18004,
1544 .halt_check = BRANCH_HALT_VOTED,
1545 .clkr = {
1546 .enable_reg = 0x52008,
1547 .enable_mask = BIT(18),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "gcc_qupv3_wrap1_core_2x_clk",
1550 .ops = &clk_branch2_ops,
1551 },
1552 },
1553 };
1554
1555 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1556 .halt_reg = 0x18008,
1557 .halt_check = BRANCH_HALT_VOTED,
1558 .clkr = {
1559 .enable_reg = 0x52008,
1560 .enable_mask = BIT(19),
1561 .hw.init = &(struct clk_init_data){
1562 .name = "gcc_qupv3_wrap1_core_clk",
1563 .ops = &clk_branch2_ops,
1564 },
1565 },
1566 };
1567
1568 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1569 .halt_reg = 0x18014,
1570 .halt_check = BRANCH_HALT_VOTED,
1571 .clkr = {
1572 .enable_reg = 0x52008,
1573 .enable_mask = BIT(22),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_qupv3_wrap1_s0_clk",
1576 .parent_hws = (const struct clk_hw*[]){
1577 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1578 },
1579 .num_parents = 1,
1580 .flags = CLK_SET_RATE_PARENT,
1581 .ops = &clk_branch2_ops,
1582 },
1583 },
1584 };
1585
1586 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1587 .halt_reg = 0x18144,
1588 .halt_check = BRANCH_HALT_VOTED,
1589 .clkr = {
1590 .enable_reg = 0x52008,
1591 .enable_mask = BIT(23),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "gcc_qupv3_wrap1_s1_clk",
1594 .parent_hws = (const struct clk_hw*[]){
1595 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1596 },
1597 .num_parents = 1,
1598 .flags = CLK_SET_RATE_PARENT,
1599 .ops = &clk_branch2_ops,
1600 },
1601 },
1602 };
1603
1604 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1605 .halt_reg = 0x18274,
1606 .halt_check = BRANCH_HALT_VOTED,
1607 .clkr = {
1608 .enable_reg = 0x52008,
1609 .enable_mask = BIT(24),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_qupv3_wrap1_s2_clk",
1612 .parent_hws = (const struct clk_hw*[]){
1613 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1614 },
1615 .num_parents = 1,
1616 .flags = CLK_SET_RATE_PARENT,
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620 };
1621
1622 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1623 .halt_reg = 0x183a4,
1624 .halt_check = BRANCH_HALT_VOTED,
1625 .clkr = {
1626 .enable_reg = 0x52008,
1627 .enable_mask = BIT(25),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "gcc_qupv3_wrap1_s3_clk",
1630 .parent_hws = (const struct clk_hw*[]){
1631 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1632 },
1633 .num_parents = 1,
1634 .flags = CLK_SET_RATE_PARENT,
1635 .ops = &clk_branch2_ops,
1636 },
1637 },
1638 };
1639
1640 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1641 .halt_reg = 0x184d4,
1642 .halt_check = BRANCH_HALT_VOTED,
1643 .clkr = {
1644 .enable_reg = 0x52008,
1645 .enable_mask = BIT(26),
1646 .hw.init = &(struct clk_init_data){
1647 .name = "gcc_qupv3_wrap1_s4_clk",
1648 .parent_hws = (const struct clk_hw*[]){
1649 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1650 },
1651 .num_parents = 1,
1652 .flags = CLK_SET_RATE_PARENT,
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656 };
1657
1658 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1659 .halt_reg = 0x18604,
1660 .halt_check = BRANCH_HALT_VOTED,
1661 .clkr = {
1662 .enable_reg = 0x52008,
1663 .enable_mask = BIT(27),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_qupv3_wrap1_s5_clk",
1666 .parent_hws = (const struct clk_hw*[]){
1667 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1668 },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674 };
1675
1676 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1677 .halt_reg = 0x17004,
1678 .halt_check = BRANCH_HALT_VOTED,
1679 .clkr = {
1680 .enable_reg = 0x52008,
1681 .enable_mask = BIT(6),
1682 .hw.init = &(struct clk_init_data){
1683 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1684 .ops = &clk_branch2_ops,
1685 },
1686 },
1687 };
1688
1689 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1690 .halt_reg = 0x17008,
1691 .halt_check = BRANCH_HALT_VOTED,
1692 .hwcg_reg = 0x17008,
1693 .hwcg_bit = 1,
1694 .clkr = {
1695 .enable_reg = 0x52008,
1696 .enable_mask = BIT(7),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1699 .ops = &clk_branch2_ops,
1700 },
1701 },
1702 };
1703
1704 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1705 .halt_reg = 0x1800c,
1706 .halt_check = BRANCH_HALT_VOTED,
1707 .clkr = {
1708 .enable_reg = 0x52008,
1709 .enable_mask = BIT(20),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1712 .ops = &clk_branch2_ops,
1713 },
1714 },
1715 };
1716
1717 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1718 .halt_reg = 0x18010,
1719 .halt_check = BRANCH_HALT_VOTED,
1720 .hwcg_reg = 0x18010,
1721 .hwcg_bit = 1,
1722 .clkr = {
1723 .enable_reg = 0x52008,
1724 .enable_mask = BIT(21),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1727 .ops = &clk_branch2_ops,
1728 },
1729 },
1730 };
1731
1732 static struct clk_branch gcc_sdcc1_ahb_clk = {
1733 .halt_reg = 0x12008,
1734 .halt_check = BRANCH_HALT,
1735 .clkr = {
1736 .enable_reg = 0x12008,
1737 .enable_mask = BIT(0),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "gcc_sdcc1_ahb_clk",
1740 .ops = &clk_branch2_ops,
1741 },
1742 },
1743 };
1744
1745 static struct clk_branch gcc_sdcc1_apps_clk = {
1746 .halt_reg = 0x1200c,
1747 .halt_check = BRANCH_HALT,
1748 .clkr = {
1749 .enable_reg = 0x1200c,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "gcc_sdcc1_apps_clk",
1753 .parent_hws = (const struct clk_hw*[]){
1754 &gcc_sdcc1_apps_clk_src.clkr.hw,
1755 },
1756 .num_parents = 1,
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1759 },
1760 },
1761 };
1762
1763 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1764 .halt_reg = 0x12040,
1765 .halt_check = BRANCH_HALT,
1766 .clkr = {
1767 .enable_reg = 0x12040,
1768 .enable_mask = BIT(0),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "gcc_sdcc1_ice_core_clk",
1771 .parent_hws = (const struct clk_hw*[]){
1772 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1773 },
1774 .num_parents = 1,
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779 };
1780
1781 static struct clk_branch gcc_sdcc2_ahb_clk = {
1782 .halt_reg = 0x14008,
1783 .halt_check = BRANCH_HALT,
1784 .clkr = {
1785 .enable_reg = 0x14008,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_sdcc2_ahb_clk",
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792 };
1793
1794 static struct clk_branch gcc_sdcc2_apps_clk = {
1795 .halt_reg = 0x14004,
1796 .halt_check = BRANCH_HALT,
1797 .clkr = {
1798 .enable_reg = 0x14004,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_sdcc2_apps_clk",
1802 .parent_hws = (const struct clk_hw*[]){
1803 &gcc_sdcc2_apps_clk_src.clkr.hw,
1804 },
1805 .num_parents = 1,
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1808 },
1809 },
1810 };
1811
1812 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1813 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1814 .halt_reg = 0x4144,
1815 .halt_check = BRANCH_HALT_VOTED,
1816 .clkr = {
1817 .enable_reg = 0x52000,
1818 .enable_mask = BIT(0),
1819 .hw.init = &(struct clk_init_data){
1820 .name = "gcc_sys_noc_cpuss_ahb_clk",
1821 .parent_hws = (const struct clk_hw*[]){
1822 &gcc_cpuss_ahb_clk_src.clkr.hw,
1823 },
1824 .num_parents = 1,
1825 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1826 .ops = &clk_branch2_ops,
1827 },
1828 },
1829 };
1830
1831 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1832 .halt_reg = 0x8c000,
1833 .halt_check = BRANCH_HALT,
1834 .clkr = {
1835 .enable_reg = 0x8c000,
1836 .enable_mask = BIT(0),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "gcc_ufs_mem_clkref_clk",
1839 .ops = &clk_branch2_ops,
1840 },
1841 },
1842 };
1843
1844 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1845 .halt_reg = 0x77014,
1846 .halt_check = BRANCH_HALT,
1847 .hwcg_reg = 0x77014,
1848 .hwcg_bit = 1,
1849 .clkr = {
1850 .enable_reg = 0x77014,
1851 .enable_mask = BIT(0),
1852 .hw.init = &(struct clk_init_data){
1853 .name = "gcc_ufs_phy_ahb_clk",
1854 .ops = &clk_branch2_ops,
1855 },
1856 },
1857 };
1858
1859 static struct clk_branch gcc_ufs_phy_axi_clk = {
1860 .halt_reg = 0x77038,
1861 .halt_check = BRANCH_HALT,
1862 .hwcg_reg = 0x77038,
1863 .hwcg_bit = 1,
1864 .clkr = {
1865 .enable_reg = 0x77038,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "gcc_ufs_phy_axi_clk",
1869 .parent_hws = (const struct clk_hw*[]){
1870 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1871 },
1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877 };
1878
1879 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1880 .halt_reg = 0x77090,
1881 .halt_check = BRANCH_HALT,
1882 .hwcg_reg = 0x77090,
1883 .hwcg_bit = 1,
1884 .clkr = {
1885 .enable_reg = 0x77090,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_ufs_phy_ice_core_clk",
1889 .parent_hws = (const struct clk_hw*[]){
1890 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1891 },
1892 .num_parents = 1,
1893 .flags = CLK_SET_RATE_PARENT,
1894 .ops = &clk_branch2_ops,
1895 },
1896 },
1897 };
1898
1899 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1900 .halt_reg = 0x77094,
1901 .halt_check = BRANCH_HALT,
1902 .hwcg_reg = 0x77094,
1903 .hwcg_bit = 1,
1904 .clkr = {
1905 .enable_reg = 0x77094,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_ufs_phy_phy_aux_clk",
1909 .parent_hws = (const struct clk_hw*[]){
1910 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1911 },
1912 .num_parents = 1,
1913 .flags = CLK_SET_RATE_PARENT,
1914 .ops = &clk_branch2_ops,
1915 },
1916 },
1917 };
1918
1919 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1920 .halt_reg = 0x7701c,
1921 .halt_check = BRANCH_HALT_SKIP,
1922 .clkr = {
1923 .enable_reg = 0x7701c,
1924 .enable_mask = BIT(0),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "gcc_ufs_phy_rx_symbol_0_clk",
1927 .ops = &clk_branch2_ops,
1928 },
1929 },
1930 };
1931
1932 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1933 .halt_reg = 0x77018,
1934 .halt_check = BRANCH_HALT_SKIP,
1935 .clkr = {
1936 .enable_reg = 0x77018,
1937 .enable_mask = BIT(0),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_ufs_phy_tx_symbol_0_clk",
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943 };
1944
1945 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1946 .halt_reg = 0x7708c,
1947 .halt_check = BRANCH_HALT,
1948 .hwcg_reg = 0x7708c,
1949 .hwcg_bit = 1,
1950 .clkr = {
1951 .enable_reg = 0x7708c,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_ufs_phy_unipro_core_clk",
1955 .parent_hws = (const struct clk_hw*[]){
1956 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1957 },
1958 .num_parents = 1,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1961 },
1962 },
1963 };
1964
1965 static struct clk_branch gcc_usb30_prim_master_clk = {
1966 .halt_reg = 0xf010,
1967 .halt_check = BRANCH_HALT,
1968 .clkr = {
1969 .enable_reg = 0xf010,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_usb30_prim_master_clk",
1973 .parent_hws = (const struct clk_hw*[]){
1974 &gcc_usb30_prim_master_clk_src.clkr.hw,
1975 },
1976 .num_parents = 1,
1977 .flags = CLK_SET_RATE_PARENT,
1978 .ops = &clk_branch2_ops,
1979 },
1980 },
1981 };
1982
1983 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1984 .halt_reg = 0xf018,
1985 .halt_check = BRANCH_HALT,
1986 .clkr = {
1987 .enable_reg = 0xf018,
1988 .enable_mask = BIT(0),
1989 .hw.init = &(struct clk_init_data){
1990 .name = "gcc_usb30_prim_mock_utmi_clk",
1991 .parent_data = &(const struct clk_parent_data){
1992 .hw =
1993 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1994 },
1995 .num_parents = 1,
1996 .flags = CLK_SET_RATE_PARENT,
1997 .ops = &clk_branch2_ops,
1998 },
1999 },
2000 };
2001
2002 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2003 .halt_reg = 0xf014,
2004 .halt_check = BRANCH_HALT,
2005 .clkr = {
2006 .enable_reg = 0xf014,
2007 .enable_mask = BIT(0),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "gcc_usb30_prim_sleep_clk",
2010 .ops = &clk_branch2_ops,
2011 },
2012 },
2013 };
2014
2015 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2016 .halt_reg = 0x8c010,
2017 .halt_check = BRANCH_HALT,
2018 .clkr = {
2019 .enable_reg = 0x8c010,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "gcc_usb3_prim_clkref_clk",
2023 .ops = &clk_branch2_ops,
2024 },
2025 },
2026 };
2027
2028 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2029 .halt_reg = 0xf050,
2030 .halt_check = BRANCH_HALT,
2031 .clkr = {
2032 .enable_reg = 0xf050,
2033 .enable_mask = BIT(0),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "gcc_usb3_prim_phy_aux_clk",
2036 .parent_hws = (const struct clk_hw*[]){
2037 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2038 },
2039 .num_parents = 1,
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044 };
2045
2046 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2047 .halt_reg = 0xf054,
2048 .halt_check = BRANCH_HALT,
2049 .clkr = {
2050 .enable_reg = 0xf054,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gcc_usb3_prim_phy_com_aux_clk",
2054 .parent_hws = (const struct clk_hw*[]){
2055 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062 };
2063
2064 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2065 .halt_reg = 0xf058,
2066 .halt_check = BRANCH_HALT_SKIP,
2067 .clkr = {
2068 .enable_reg = 0xf058,
2069 .enable_mask = BIT(0),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "gcc_usb3_prim_phy_pipe_clk",
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075 };
2076
2077 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2078 .halt_reg = 0x6a004,
2079 .halt_check = BRANCH_HALT,
2080 .hwcg_reg = 0x6a004,
2081 .hwcg_bit = 1,
2082 .clkr = {
2083 .enable_reg = 0x6a004,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2087 .ops = &clk_branch2_ops,
2088 },
2089 },
2090 };
2091
2092 static struct clk_branch gcc_video_axi_clk = {
2093 .halt_reg = 0xb01c,
2094 .halt_check = BRANCH_HALT,
2095 .clkr = {
2096 .enable_reg = 0xb01c,
2097 .enable_mask = BIT(0),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "gcc_video_axi_clk",
2100 .ops = &clk_branch2_ops,
2101 },
2102 },
2103 };
2104
2105 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2106 .halt_check = BRANCH_HALT_DELAY,
2107 .clkr = {
2108 .enable_reg = 0x52000,
2109 .enable_mask = BIT(20),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "gcc_video_gpll0_div_clk_src",
2112 .parent_hws = (const struct clk_hw*[]){
2113 &gcc_pll0_main_div_cdiv.hw,
2114 },
2115 .num_parents = 1,
2116 .flags = CLK_SET_RATE_PARENT,
2117 .ops = &clk_branch2_ops,
2118 },
2119 },
2120 };
2121
2122 static struct clk_branch gcc_video_throttle_axi_clk = {
2123 .halt_reg = 0xb07c,
2124 .halt_check = BRANCH_HALT,
2125 .hwcg_reg = 0xb07c,
2126 .hwcg_bit = 1,
2127 .clkr = {
2128 .enable_reg = 0xb07c,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gcc_video_throttle_axi_clk",
2132 .ops = &clk_branch2_ops,
2133 },
2134 },
2135 };
2136
2137 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2138 .halt_reg = 0x8a000,
2139 .halt_check = BRANCH_HALT,
2140 .clkr = {
2141 .enable_reg = 0x8a000,
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gcc_mss_cfg_ahb_clk",
2145 .ops = &clk_branch2_ops,
2146 },
2147 },
2148 };
2149
2150 static struct clk_branch gcc_mss_mfab_axis_clk = {
2151 .halt_reg = 0x8a004,
2152 .halt_check = BRANCH_HALT_VOTED,
2153 .clkr = {
2154 .enable_reg = 0x8a004,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "gcc_mss_mfab_axis_clk",
2158 .ops = &clk_branch2_ops,
2159 },
2160 },
2161 };
2162
2163 static struct clk_branch gcc_mss_nav_axi_clk = {
2164 .halt_reg = 0x8a00c,
2165 .halt_check = BRANCH_HALT_VOTED,
2166 .clkr = {
2167 .enable_reg = 0x8a00c,
2168 .enable_mask = BIT(0),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "gcc_mss_nav_axi_clk",
2171 .ops = &clk_branch2_ops,
2172 },
2173 },
2174 };
2175
2176 static struct clk_branch gcc_mss_snoc_axi_clk = {
2177 .halt_reg = 0x8a150,
2178 .halt_check = BRANCH_HALT,
2179 .clkr = {
2180 .enable_reg = 0x8a150,
2181 .enable_mask = BIT(0),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "gcc_mss_snoc_axi_clk",
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187 };
2188
2189 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2190 .halt_reg = 0x8a154,
2191 .halt_check = BRANCH_HALT,
2192 .clkr = {
2193 .enable_reg = 0x8a154,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_mss_q6_memnoc_axi_clk",
2197 .ops = &clk_branch2_ops,
2198 },
2199 },
2200 };
2201
2202 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2203 .halt_reg = 0x47018,
2204 .halt_check = BRANCH_HALT_DELAY,
2205 .clkr = {
2206 .enable_reg = 0x47018,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_lpass_cfg_noc_sway_clk",
2210 .ops = &clk_branch2_ops,
2211 },
2212 },
2213 };
2214
2215 static struct gdsc ufs_phy_gdsc = {
2216 .gdscr = 0x77004,
2217 .pd = {
2218 .name = "ufs_phy_gdsc",
2219 },
2220 .pwrsts = PWRSTS_OFF_ON,
2221 };
2222
2223 static struct gdsc usb30_prim_gdsc = {
2224 .gdscr = 0x0f004,
2225 .pd = {
2226 .name = "usb30_prim_gdsc",
2227 },
2228 .pwrsts = PWRSTS_OFF_ON,
2229 };
2230
2231 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2232 .gdscr = 0x7d040,
2233 .pd = {
2234 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2235 },
2236 .pwrsts = PWRSTS_OFF_ON,
2237 .flags = VOTABLE,
2238 };
2239
2240 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2241 .gdscr = 0x7d044,
2242 .pd = {
2243 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2244 },
2245 .pwrsts = PWRSTS_OFF_ON,
2246 .flags = VOTABLE,
2247 };
2248
2249 static struct gdsc *gcc_sc7180_gdscs[] = {
2250 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2251 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2252 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2253 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2254 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2255 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2256 };
2257
2258
2259 static struct clk_hw *gcc_sc7180_hws[] = {
2260 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2261 };
2262
2263 static struct clk_regmap *gcc_sc7180_clocks[] = {
2264 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2265 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2266 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2267 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2268 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2269 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2270 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2271 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2272 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2273 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2274 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2275 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2276 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2277 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2278 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2279 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2280 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2281 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2282 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2283 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2284 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2285 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2286 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2287 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2288 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2289 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2290 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2291 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2292 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2293 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2294 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2295 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2296 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2297 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2298 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2299 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2300 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2301 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2302 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2303 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2304 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2305 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2306 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2307 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2308 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2309 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2310 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2311 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2312 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2313 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2314 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2315 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2316 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2317 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2318 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2319 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2320 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2321 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2322 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2323 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2324 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2325 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2326 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2327 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2328 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2329 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2330 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2331 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2332 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2333 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2334 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2335 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2336 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2337 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2338 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2339 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2340 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2341 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2342 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2343 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2344 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2345 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2346 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2347 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2348 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2349 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2350 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2351 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2352 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2353 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2354 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2355 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2356 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2357 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2358 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2359 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2360 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2361 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2362 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2363 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2364 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2365 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2366 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2367 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2368 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2369 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2370 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2371 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2372 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2373 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2374 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2375 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2376 [GPLL0] = &gpll0.clkr,
2377 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2378 [GPLL6] = &gpll6.clkr,
2379 [GPLL7] = &gpll7.clkr,
2380 [GPLL4] = &gpll4.clkr,
2381 [GPLL1] = &gpll1.clkr,
2382 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2383 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2384 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2385 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2386 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2387 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2388 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2389 };
2390
2391 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2392 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2393 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2394 [GCC_UFS_PHY_BCR] = { 0x77000 },
2395 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2396 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2397 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2398 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2399 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2400 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2401 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2402 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2403 };
2404
2405 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2406 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2407 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2408 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2409 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2410 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2411 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2412 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2413 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2414 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2415 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2416 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2417 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2418 };
2419
2420 static const struct regmap_config gcc_sc7180_regmap_config = {
2421 .reg_bits = 32,
2422 .reg_stride = 4,
2423 .val_bits = 32,
2424 .max_register = 0x18208c,
2425 .fast_io = true,
2426 };
2427
2428 static const struct qcom_cc_desc gcc_sc7180_desc = {
2429 .config = &gcc_sc7180_regmap_config,
2430 .clk_hws = gcc_sc7180_hws,
2431 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2432 .clks = gcc_sc7180_clocks,
2433 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2434 .resets = gcc_sc7180_resets,
2435 .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2436 .gdscs = gcc_sc7180_gdscs,
2437 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2438 };
2439
2440 static const struct of_device_id gcc_sc7180_match_table[] = {
2441 { .compatible = "qcom,gcc-sc7180" },
2442 { }
2443 };
2444 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2445
gcc_sc7180_probe(struct platform_device * pdev)2446 static int gcc_sc7180_probe(struct platform_device *pdev)
2447 {
2448 struct regmap *regmap;
2449 int ret;
2450
2451 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2452 if (IS_ERR(regmap))
2453 return PTR_ERR(regmap);
2454
2455 /*
2456 * Disable the GPLL0 active input to MM blocks, NPU
2457 * and GPU via MISC registers.
2458 */
2459 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2460 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2461 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2462
2463 /*
2464 * Keep the clocks always-ON
2465 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
2466 * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
2467 */
2468 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2469 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2470 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
2471 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2472 regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
2473 regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
2474 regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
2475 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2476
2477 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2478 ARRAY_SIZE(gcc_dfs_clocks));
2479 if (ret)
2480 return ret;
2481
2482 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2483 }
2484
2485 static struct platform_driver gcc_sc7180_driver = {
2486 .probe = gcc_sc7180_probe,
2487 .driver = {
2488 .name = "gcc-sc7180",
2489 .of_match_table = gcc_sc7180_match_table,
2490 },
2491 };
2492
gcc_sc7180_init(void)2493 static int __init gcc_sc7180_init(void)
2494 {
2495 return platform_driver_register(&gcc_sc7180_driver);
2496 }
2497 core_initcall(gcc_sc7180_init);
2498
gcc_sc7180_exit(void)2499 static void __exit gcc_sc7180_exit(void)
2500 {
2501 platform_driver_unregister(&gcc_sc7180_driver);
2502 }
2503 module_exit(gcc_sc7180_exit);
2504
2505 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2506 MODULE_LICENSE("GPL v2");
2507