1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/aer.h>
6 #include <linux/bitops.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
9 #include <linux/io.h>
10 #include <linux/iommu.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/seq_file.h>
16 #include <linux/topology.h>
17 #include <linux/uacce.h>
18
19 #include "sec.h"
20
21 #define SEC_VF_NUM 63
22 #define SEC_QUEUE_NUM_V1 4096
23 #define SEC_PF_PCI_DEVICE_ID 0xa255
24 #define SEC_VF_PCI_DEVICE_ID 0xa256
25
26 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
27 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
28 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
29
30 #define SEC_SQE_SIZE 128
31 #define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH)
32 #define SEC_PF_DEF_Q_NUM 256
33 #define SEC_PF_DEF_Q_BASE 0
34 #define SEC_CTX_Q_NUM_DEF 2
35 #define SEC_CTX_Q_NUM_MAX 32
36
37 #define SEC_CTRL_CNT_CLR_CE 0x301120
38 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
39 #define SEC_CORE_INT_SOURCE 0x301010
40 #define SEC_CORE_INT_MASK 0x301000
41 #define SEC_CORE_INT_STATUS 0x301008
42 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
43 #define SEC_ECC_NUM 16
44 #define SEC_ECC_MASH 0xFF
45 #define SEC_CORE_INT_DISABLE 0x0
46 #define SEC_CORE_INT_ENABLE 0x7c1ff
47 #define SEC_CORE_INT_CLEAR 0x7c1ff
48 #define SEC_SAA_ENABLE 0x17f
49
50 #define SEC_RAS_CE_REG 0x301050
51 #define SEC_RAS_FE_REG 0x301054
52 #define SEC_RAS_NFE_REG 0x301058
53 #define SEC_RAS_CE_ENB_MSK 0x88
54 #define SEC_RAS_FE_ENB_MSK 0x0
55 #define SEC_RAS_NFE_ENB_MSK 0x7c177
56 #define SEC_OOO_SHUTDOWN_SEL 0x301014
57 #define SEC_RAS_DISABLE 0x0
58 #define SEC_MEM_START_INIT_REG 0x301100
59 #define SEC_MEM_INIT_DONE_REG 0x301104
60
61 /* clock gating */
62 #define SEC_CONTROL_REG 0x301200
63 #define SEC_DYNAMIC_GATE_REG 0x30121c
64 #define SEC_CORE_AUTO_GATE 0x30212c
65 #define SEC_DYNAMIC_GATE_EN 0x7bff
66 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
67 #define SEC_CLK_GATE_ENABLE BIT(3)
68 #define SEC_CLK_GATE_DISABLE (~BIT(3))
69
70 #define SEC_TRNG_EN_SHIFT 8
71 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
72 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
73
74 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
75 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
76 #define SEC_SAA_EN_REG 0x301270
77 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
78 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
79 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
80
81 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
82 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
83 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
84 #define SEC_USER1_ENABLE_DATA_SSV BIT(16)
85 #define SEC_USER1_WB_CONTEXT_SSV BIT(8)
86 #define SEC_USER1_WB_DATA_SSV BIT(0)
87 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \
88 SEC_USER1_ENABLE_DATA_SSV | \
89 SEC_USER1_WB_CONTEXT_SSV | \
90 SEC_USER1_WB_DATA_SSV)
91 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
92 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
93 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
94
95 #define SEC_PREFETCH_CFG 0x301130
96 #define SEC_SVA_TRANS 0x301EC4
97 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
98 #define SEC_PREFETCH_DISABLE BIT(1)
99 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11))
100
101 #define SEC_DELAY_10_US 10
102 #define SEC_POLL_TIMEOUT_US 1000
103 #define SEC_DBGFS_VAL_MAX_LEN 20
104 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
105
106 #define SEC_SQE_MASK_OFFSET 64
107 #define SEC_SQE_MASK_LEN 48
108 #define SEC_SHAPER_TYPE_RATE 128
109
110 struct sec_hw_error {
111 u32 int_msk;
112 const char *msg;
113 };
114
115 struct sec_dfx_item {
116 const char *name;
117 u32 offset;
118 };
119
120 static const char sec_name[] = "hisi_sec2";
121 static struct dentry *sec_debugfs_root;
122
123 static struct hisi_qm_list sec_devices = {
124 .register_to_crypto = sec_register_to_crypto,
125 .unregister_from_crypto = sec_unregister_from_crypto,
126 };
127
128 static const struct sec_hw_error sec_hw_errors[] = {
129 {
130 .int_msk = BIT(0),
131 .msg = "sec_axi_rresp_err_rint"
132 },
133 {
134 .int_msk = BIT(1),
135 .msg = "sec_axi_bresp_err_rint"
136 },
137 {
138 .int_msk = BIT(2),
139 .msg = "sec_ecc_2bit_err_rint"
140 },
141 {
142 .int_msk = BIT(3),
143 .msg = "sec_ecc_1bit_err_rint"
144 },
145 {
146 .int_msk = BIT(4),
147 .msg = "sec_req_trng_timeout_rint"
148 },
149 {
150 .int_msk = BIT(5),
151 .msg = "sec_fsm_hbeat_rint"
152 },
153 {
154 .int_msk = BIT(6),
155 .msg = "sec_channel_req_rng_timeout_rint"
156 },
157 {
158 .int_msk = BIT(7),
159 .msg = "sec_bd_err_rint"
160 },
161 {
162 .int_msk = BIT(8),
163 .msg = "sec_chain_buff_err_rint"
164 },
165 {
166 .int_msk = BIT(14),
167 .msg = "sec_no_secure_access"
168 },
169 {
170 .int_msk = BIT(15),
171 .msg = "sec_wrapping_key_auth_err"
172 },
173 {
174 .int_msk = BIT(16),
175 .msg = "sec_km_key_crc_fail"
176 },
177 {
178 .int_msk = BIT(17),
179 .msg = "sec_axi_poison_err"
180 },
181 {
182 .int_msk = BIT(18),
183 .msg = "sec_sva_err"
184 },
185 {}
186 };
187
188 static const char * const sec_dbg_file_name[] = {
189 [SEC_CLEAR_ENABLE] = "clear_enable",
190 };
191
192 static struct sec_dfx_item sec_dfx_labels[] = {
193 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
194 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)},
195 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
196 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)},
197 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)},
198 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)},
199 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
200 };
201
202 static const struct debugfs_reg32 sec_dfx_regs[] = {
203 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
204 {"SEC_SAA_EN ", 0x301270},
205 {"SEC_BD_LATENCY_MIN ", 0x301600},
206 {"SEC_BD_LATENCY_MAX ", 0x301608},
207 {"SEC_BD_LATENCY_AVG ", 0x30160C},
208 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
209 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
210 {"SEC_BD_NUM_IN_SEC ", 0x301680},
211 {"SEC_ECC_1BIT_CNT ", 0x301C00},
212 {"SEC_ECC_1BIT_INFO ", 0x301C04},
213 {"SEC_ECC_2BIT_CNT ", 0x301C10},
214 {"SEC_ECC_2BIT_INFO ", 0x301C14},
215 {"SEC_BD_SAA0 ", 0x301C20},
216 {"SEC_BD_SAA1 ", 0x301C24},
217 {"SEC_BD_SAA2 ", 0x301C28},
218 {"SEC_BD_SAA3 ", 0x301C2C},
219 {"SEC_BD_SAA4 ", 0x301C30},
220 {"SEC_BD_SAA5 ", 0x301C34},
221 {"SEC_BD_SAA6 ", 0x301C38},
222 {"SEC_BD_SAA7 ", 0x301C3C},
223 {"SEC_BD_SAA8 ", 0x301C40},
224 };
225
sec_pf_q_num_set(const char * val,const struct kernel_param * kp)226 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
227 {
228 return q_num_set(val, kp, SEC_PF_PCI_DEVICE_ID);
229 }
230
231 static const struct kernel_param_ops sec_pf_q_num_ops = {
232 .set = sec_pf_q_num_set,
233 .get = param_get_int,
234 };
235
236 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
237 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
238 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
239
sec_ctx_q_num_set(const char * val,const struct kernel_param * kp)240 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
241 {
242 u32 ctx_q_num;
243 int ret;
244
245 if (!val)
246 return -EINVAL;
247
248 ret = kstrtou32(val, 10, &ctx_q_num);
249 if (ret)
250 return -EINVAL;
251
252 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
253 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
254 return -EINVAL;
255 }
256
257 return param_set_int(val, kp);
258 }
259
260 static const struct kernel_param_ops sec_ctx_q_num_ops = {
261 .set = sec_ctx_q_num_set,
262 .get = param_get_int,
263 };
264 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
265 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
266 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
267
268 static const struct kernel_param_ops vfs_num_ops = {
269 .set = vfs_num_set,
270 .get = param_get_int,
271 };
272
273 static u32 vfs_num;
274 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
275 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
276
sec_destroy_qps(struct hisi_qp ** qps,int qp_num)277 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
278 {
279 hisi_qm_free_qps(qps, qp_num);
280 kfree(qps);
281 }
282
sec_create_qps(void)283 struct hisi_qp **sec_create_qps(void)
284 {
285 int node = cpu_to_node(smp_processor_id());
286 u32 ctx_num = ctx_q_num;
287 struct hisi_qp **qps;
288 int ret;
289
290 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL);
291 if (!qps)
292 return NULL;
293
294 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps);
295 if (!ret)
296 return qps;
297
298 kfree(qps);
299 return NULL;
300 }
301
302 static const struct kernel_param_ops sec_uacce_mode_ops = {
303 .set = uacce_mode_set,
304 .get = param_get_int,
305 };
306
307 /*
308 * uacce_mode = 0 means sec only register to crypto,
309 * uacce_mode = 1 means sec both register to crypto and uacce.
310 */
311 static u32 uacce_mode = UACCE_MODE_NOUACCE;
312 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
313 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
314
315 static const struct pci_device_id sec_dev_ids[] = {
316 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PF_PCI_DEVICE_ID) },
317 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_VF_PCI_DEVICE_ID) },
318 { 0, }
319 };
320 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
321
sec_set_endian(struct hisi_qm * qm)322 static void sec_set_endian(struct hisi_qm *qm)
323 {
324 u32 reg;
325
326 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
327 reg &= ~(BIT(1) | BIT(0));
328 if (!IS_ENABLED(CONFIG_64BIT))
329 reg |= BIT(1);
330
331
332 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
333 reg |= BIT(0);
334
335 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
336 }
337
sec_open_sva_prefetch(struct hisi_qm * qm)338 static void sec_open_sva_prefetch(struct hisi_qm *qm)
339 {
340 u32 val;
341 int ret;
342
343 if (qm->ver < QM_HW_V3)
344 return;
345
346 /* Enable prefetch */
347 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
348 val &= SEC_PREFETCH_ENABLE;
349 writel(val, qm->io_base + SEC_PREFETCH_CFG);
350
351 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
352 val, !(val & SEC_PREFETCH_DISABLE),
353 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
354 if (ret)
355 pci_err(qm->pdev, "failed to open sva prefetch\n");
356 }
357
sec_close_sva_prefetch(struct hisi_qm * qm)358 static void sec_close_sva_prefetch(struct hisi_qm *qm)
359 {
360 u32 val;
361 int ret;
362
363 if (qm->ver < QM_HW_V3)
364 return;
365
366 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
367 val |= SEC_PREFETCH_DISABLE;
368 writel(val, qm->io_base + SEC_PREFETCH_CFG);
369
370 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
371 val, !(val & SEC_SVA_DISABLE_READY),
372 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
373 if (ret)
374 pci_err(qm->pdev, "failed to close sva prefetch\n");
375 }
376
sec_enable_clock_gate(struct hisi_qm * qm)377 static void sec_enable_clock_gate(struct hisi_qm *qm)
378 {
379 u32 val;
380
381 if (qm->ver < QM_HW_V3)
382 return;
383
384 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
385 val |= SEC_CLK_GATE_ENABLE;
386 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
387
388 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);
389 val |= SEC_DYNAMIC_GATE_EN;
390 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
391
392 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
393 val |= SEC_CORE_AUTO_GATE_EN;
394 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
395 }
396
sec_disable_clock_gate(struct hisi_qm * qm)397 static void sec_disable_clock_gate(struct hisi_qm *qm)
398 {
399 u32 val;
400
401 /* Kunpeng920 needs to close clock gating */
402 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
403 val &= SEC_CLK_GATE_DISABLE;
404 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
405 }
406
sec_engine_init(struct hisi_qm * qm)407 static int sec_engine_init(struct hisi_qm *qm)
408 {
409 int ret;
410 u32 reg;
411
412 /* disable clock gate control before mem init */
413 sec_disable_clock_gate(qm);
414
415 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
416
417 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
418 reg, reg & 0x1, SEC_DELAY_10_US,
419 SEC_POLL_TIMEOUT_US);
420 if (ret) {
421 pci_err(qm->pdev, "fail to init sec mem\n");
422 return ret;
423 }
424
425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
426 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
427 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
428
429 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
430 reg |= SEC_USER0_SMMU_NORMAL;
431 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
432
433 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
434 reg &= SEC_USER1_SMMU_MASK;
435 if (qm->use_sva && qm->ver == QM_HW_V2)
436 reg |= SEC_USER1_SMMU_SVA;
437 else
438 reg |= SEC_USER1_SMMU_NORMAL;
439 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
440
441 writel(SEC_SINGLE_PORT_MAX_TRANS,
442 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
443
444 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
445
446 /* HW V2 enable sm4 extra mode, as ctr/ecb */
447 if (qm->ver < QM_HW_V3)
448 writel_relaxed(SEC_BD_ERR_CHK_EN0,
449 qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
450
451 /* Enable sm4 xts mode multiple iv */
452 writel_relaxed(SEC_BD_ERR_CHK_EN1,
453 qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
454 writel_relaxed(SEC_BD_ERR_CHK_EN3,
455 qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
456
457 /* config endian */
458 sec_set_endian(qm);
459
460 sec_enable_clock_gate(qm);
461
462 return 0;
463 }
464
sec_set_user_domain_and_cache(struct hisi_qm * qm)465 static int sec_set_user_domain_and_cache(struct hisi_qm *qm)
466 {
467 /* qm user domain */
468 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
469 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
470 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
471 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
472 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
473
474 /* qm cache */
475 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
476 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
477
478 /* disable FLR triggered by BME(bus master enable) */
479 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
480 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
481
482 /* enable sqc,cqc writeback */
483 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
484 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
485 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
486
487 return sec_engine_init(qm);
488 }
489
490 /* sec_debug_regs_clear() - clear the sec debug regs */
sec_debug_regs_clear(struct hisi_qm * qm)491 static void sec_debug_regs_clear(struct hisi_qm *qm)
492 {
493 int i;
494
495 /* clear sec dfx regs */
496 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
497 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
498 readl(qm->io_base + sec_dfx_regs[i].offset);
499
500 /* clear rdclr_en */
501 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
502
503 hisi_qm_debug_regs_clear(qm);
504 }
505
sec_master_ooo_ctrl(struct hisi_qm * qm,bool enable)506 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
507 {
508 u32 val1, val2;
509
510 val1 = readl(qm->io_base + SEC_CONTROL_REG);
511 if (enable) {
512 val1 |= SEC_AXI_SHUTDOWN_ENABLE;
513 val2 = SEC_RAS_NFE_ENB_MSK;
514 } else {
515 val1 &= SEC_AXI_SHUTDOWN_DISABLE;
516 val2 = 0x0;
517 }
518
519 if (qm->ver > QM_HW_V2)
520 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
521
522 writel(val1, qm->io_base + SEC_CONTROL_REG);
523 }
524
sec_hw_error_enable(struct hisi_qm * qm)525 static void sec_hw_error_enable(struct hisi_qm *qm)
526 {
527 if (qm->ver == QM_HW_V1) {
528 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
529 pci_info(qm->pdev, "V1 not support hw error handle\n");
530 return;
531 }
532
533 /* clear SEC hw error source if having */
534 writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE);
535
536 /* enable RAS int */
537 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG);
538 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
539 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG);
540
541 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
542 sec_master_ooo_ctrl(qm, true);
543
544 /* enable SEC hw error interrupts */
545 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
546 }
547
sec_hw_error_disable(struct hisi_qm * qm)548 static void sec_hw_error_disable(struct hisi_qm *qm)
549 {
550 /* disable SEC hw error interrupts */
551 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
552
553 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
554 sec_master_ooo_ctrl(qm, false);
555
556 /* disable RAS int */
557 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
558 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
559 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
560 }
561
sec_clear_enable_read(struct hisi_qm * qm)562 static u32 sec_clear_enable_read(struct hisi_qm *qm)
563 {
564 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
565 SEC_CTRL_CNT_CLR_CE_BIT;
566 }
567
sec_clear_enable_write(struct hisi_qm * qm,u32 val)568 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
569 {
570 u32 tmp;
571
572 if (val != 1 && val)
573 return -EINVAL;
574
575 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
576 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
577 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
578
579 return 0;
580 }
581
sec_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)582 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
583 size_t count, loff_t *pos)
584 {
585 struct sec_debug_file *file = filp->private_data;
586 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
587 struct hisi_qm *qm = file->qm;
588 u32 val;
589 int ret;
590
591 ret = hisi_qm_get_dfx_access(qm);
592 if (ret)
593 return ret;
594
595 spin_lock_irq(&file->lock);
596
597 switch (file->index) {
598 case SEC_CLEAR_ENABLE:
599 val = sec_clear_enable_read(qm);
600 break;
601 default:
602 goto err_input;
603 }
604
605 spin_unlock_irq(&file->lock);
606
607 hisi_qm_put_dfx_access(qm);
608 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
609 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
610
611 err_input:
612 spin_unlock_irq(&file->lock);
613 hisi_qm_put_dfx_access(qm);
614 return -EINVAL;
615 }
616
sec_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)617 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
618 size_t count, loff_t *pos)
619 {
620 struct sec_debug_file *file = filp->private_data;
621 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
622 struct hisi_qm *qm = file->qm;
623 unsigned long val;
624 int len, ret;
625
626 if (*pos != 0)
627 return 0;
628
629 if (count >= SEC_DBGFS_VAL_MAX_LEN)
630 return -ENOSPC;
631
632 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
633 pos, buf, count);
634 if (len < 0)
635 return len;
636
637 tbuf[len] = '\0';
638 if (kstrtoul(tbuf, 0, &val))
639 return -EFAULT;
640
641 ret = hisi_qm_get_dfx_access(qm);
642 if (ret)
643 return ret;
644
645 spin_lock_irq(&file->lock);
646
647 switch (file->index) {
648 case SEC_CLEAR_ENABLE:
649 ret = sec_clear_enable_write(qm, val);
650 if (ret)
651 goto err_input;
652 break;
653 default:
654 ret = -EINVAL;
655 goto err_input;
656 }
657
658 ret = count;
659
660 err_input:
661 spin_unlock_irq(&file->lock);
662 hisi_qm_put_dfx_access(qm);
663 return ret;
664 }
665
666 static const struct file_operations sec_dbg_fops = {
667 .owner = THIS_MODULE,
668 .open = simple_open,
669 .read = sec_debug_read,
670 .write = sec_debug_write,
671 };
672
sec_debugfs_atomic64_get(void * data,u64 * val)673 static int sec_debugfs_atomic64_get(void *data, u64 *val)
674 {
675 *val = atomic64_read((atomic64_t *)data);
676
677 return 0;
678 }
679
sec_debugfs_atomic64_set(void * data,u64 val)680 static int sec_debugfs_atomic64_set(void *data, u64 val)
681 {
682 if (val)
683 return -EINVAL;
684
685 atomic64_set((atomic64_t *)data, 0);
686
687 return 0;
688 }
689
690 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
691 sec_debugfs_atomic64_set, "%lld\n");
692
sec_regs_show(struct seq_file * s,void * unused)693 static int sec_regs_show(struct seq_file *s, void *unused)
694 {
695 hisi_qm_regs_dump(s, s->private);
696
697 return 0;
698 }
699
700 DEFINE_SHOW_ATTRIBUTE(sec_regs);
701
sec_core_debug_init(struct hisi_qm * qm)702 static int sec_core_debug_init(struct hisi_qm *qm)
703 {
704 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
705 struct device *dev = &qm->pdev->dev;
706 struct sec_dfx *dfx = &sec->debug.dfx;
707 struct debugfs_regset32 *regset;
708 struct dentry *tmp_d;
709 int i;
710
711 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);
712
713 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
714 if (!regset)
715 return -ENOMEM;
716
717 regset->regs = sec_dfx_regs;
718 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
719 regset->base = qm->io_base;
720 regset->dev = dev;
721
722 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID)
723 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops);
724
725 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) {
726 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
727 sec_dfx_labels[i].offset);
728 debugfs_create_file(sec_dfx_labels[i].name, 0644,
729 tmp_d, data, &sec_atomic64_ops);
730 }
731
732 return 0;
733 }
734
sec_debug_init(struct hisi_qm * qm)735 static int sec_debug_init(struct hisi_qm *qm)
736 {
737 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
738 int i;
739
740 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) {
741 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) {
742 spin_lock_init(&sec->debug.files[i].lock);
743 sec->debug.files[i].index = i;
744 sec->debug.files[i].qm = qm;
745
746 debugfs_create_file(sec_dbg_file_name[i], 0600,
747 qm->debug.debug_root,
748 sec->debug.files + i,
749 &sec_dbg_fops);
750 }
751 }
752
753 return sec_core_debug_init(qm);
754 }
755
sec_debugfs_init(struct hisi_qm * qm)756 static int sec_debugfs_init(struct hisi_qm *qm)
757 {
758 struct device *dev = &qm->pdev->dev;
759 int ret;
760
761 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
762 sec_debugfs_root);
763 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;
764 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;
765 hisi_qm_debug_init(qm);
766
767 ret = sec_debug_init(qm);
768 if (ret)
769 goto failed_to_create;
770
771 return 0;
772
773 failed_to_create:
774 debugfs_remove_recursive(sec_debugfs_root);
775 return ret;
776 }
777
sec_debugfs_exit(struct hisi_qm * qm)778 static void sec_debugfs_exit(struct hisi_qm *qm)
779 {
780 debugfs_remove_recursive(qm->debug.debug_root);
781 }
782
sec_log_hw_error(struct hisi_qm * qm,u32 err_sts)783 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
784 {
785 const struct sec_hw_error *errs = sec_hw_errors;
786 struct device *dev = &qm->pdev->dev;
787 u32 err_val;
788
789 while (errs->msg) {
790 if (errs->int_msk & err_sts) {
791 dev_err(dev, "%s [error status=0x%x] found\n",
792 errs->msg, errs->int_msk);
793
794 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
795 err_val = readl(qm->io_base +
796 SEC_CORE_SRAM_ECC_ERR_INFO);
797 dev_err(dev, "multi ecc sram num=0x%x\n",
798 ((err_val) >> SEC_ECC_NUM) &
799 SEC_ECC_MASH);
800 }
801 }
802 errs++;
803 }
804 }
805
sec_get_hw_err_status(struct hisi_qm * qm)806 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
807 {
808 return readl(qm->io_base + SEC_CORE_INT_STATUS);
809 }
810
sec_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)811 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
812 {
813 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
814 }
815
sec_open_axi_master_ooo(struct hisi_qm * qm)816 static void sec_open_axi_master_ooo(struct hisi_qm *qm)
817 {
818 u32 val;
819
820 val = readl(qm->io_base + SEC_CONTROL_REG);
821 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
822 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
823 }
824
sec_err_info_init(struct hisi_qm * qm)825 static void sec_err_info_init(struct hisi_qm *qm)
826 {
827 struct hisi_qm_err_info *err_info = &qm->err_info;
828
829 err_info->ce = QM_BASE_CE;
830 err_info->fe = 0;
831 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
832 err_info->dev_ce_mask = SEC_RAS_CE_ENB_MSK;
833 err_info->msi_wr_port = BIT(0);
834 err_info->acpi_rst = "SRST";
835 err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
836 QM_ACC_WB_NOT_READY_TIMEOUT;
837 }
838
839 static const struct hisi_qm_err_ini sec_err_ini = {
840 .hw_init = sec_set_user_domain_and_cache,
841 .hw_err_enable = sec_hw_error_enable,
842 .hw_err_disable = sec_hw_error_disable,
843 .get_dev_hw_err_status = sec_get_hw_err_status,
844 .clear_dev_hw_err_status = sec_clear_hw_err_status,
845 .log_dev_hw_err = sec_log_hw_error,
846 .open_axi_master_ooo = sec_open_axi_master_ooo,
847 .open_sva_prefetch = sec_open_sva_prefetch,
848 .close_sva_prefetch = sec_close_sva_prefetch,
849 .err_info_init = sec_err_info_init,
850 };
851
sec_pf_probe_init(struct sec_dev * sec)852 static int sec_pf_probe_init(struct sec_dev *sec)
853 {
854 struct hisi_qm *qm = &sec->qm;
855 int ret;
856
857 qm->err_ini = &sec_err_ini;
858 qm->err_ini->err_info_init(qm);
859
860 ret = sec_set_user_domain_and_cache(qm);
861 if (ret)
862 return ret;
863
864 sec_open_sva_prefetch(qm);
865 hisi_qm_dev_err_init(qm);
866 sec_debug_regs_clear(qm);
867
868 return 0;
869 }
870
sec_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)871 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
872 {
873 int ret;
874
875 qm->pdev = pdev;
876 qm->ver = pdev->revision;
877 qm->algs = "cipher\ndigest\naead";
878 qm->mode = uacce_mode;
879 qm->sqe_size = SEC_SQE_SIZE;
880 qm->dev_name = sec_name;
881
882 qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ?
883 QM_HW_PF : QM_HW_VF;
884 if (qm->fun_type == QM_HW_PF) {
885 qm->qp_base = SEC_PF_DEF_Q_BASE;
886 qm->qp_num = pf_q_num;
887 qm->debug.curr_qm_qp_num = pf_q_num;
888 qm->qm_list = &sec_devices;
889 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
890 /*
891 * have no way to get qm configure in VM in v1 hardware,
892 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
893 * to trigger only one VF in v1 hardware.
894 * v2 hardware has no such problem.
895 */
896 qm->qp_base = SEC_PF_DEF_Q_NUM;
897 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
898 }
899
900 /*
901 * WQ_HIGHPRI: SEC request must be low delayed,
902 * so need a high priority workqueue.
903 * WQ_UNBOUND: SEC task is likely with long
904 * running CPU intensive workloads.
905 */
906 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
907 WQ_UNBOUND, num_online_cpus(),
908 pci_name(qm->pdev));
909 if (!qm->wq) {
910 pci_err(qm->pdev, "fail to alloc workqueue\n");
911 return -ENOMEM;
912 }
913
914 ret = hisi_qm_init(qm);
915 if (ret)
916 destroy_workqueue(qm->wq);
917
918 return ret;
919 }
920
sec_qm_uninit(struct hisi_qm * qm)921 static void sec_qm_uninit(struct hisi_qm *qm)
922 {
923 hisi_qm_uninit(qm);
924 }
925
sec_probe_init(struct sec_dev * sec)926 static int sec_probe_init(struct sec_dev *sec)
927 {
928 u32 type_rate = SEC_SHAPER_TYPE_RATE;
929 struct hisi_qm *qm = &sec->qm;
930 int ret;
931
932 if (qm->fun_type == QM_HW_PF) {
933 ret = sec_pf_probe_init(sec);
934 if (ret)
935 return ret;
936 /* enable shaper type 0 */
937 if (qm->ver >= QM_HW_V3) {
938 type_rate |= QM_SHAPER_ENABLE;
939 qm->type_rate = type_rate;
940 }
941 }
942
943 return 0;
944 }
945
sec_probe_uninit(struct hisi_qm * qm)946 static void sec_probe_uninit(struct hisi_qm *qm)
947 {
948 hisi_qm_dev_err_uninit(qm);
949
950 destroy_workqueue(qm->wq);
951 }
952
sec_iommu_used_check(struct sec_dev * sec)953 static void sec_iommu_used_check(struct sec_dev *sec)
954 {
955 struct iommu_domain *domain;
956 struct device *dev = &sec->qm.pdev->dev;
957
958 domain = iommu_get_domain_for_dev(dev);
959
960 /* Check if iommu is used */
961 sec->iommu_used = false;
962 if (domain) {
963 if (domain->type & __IOMMU_DOMAIN_PAGING)
964 sec->iommu_used = true;
965 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
966 domain->type);
967 }
968 }
969
sec_probe(struct pci_dev * pdev,const struct pci_device_id * id)970 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
971 {
972 struct sec_dev *sec;
973 struct hisi_qm *qm;
974 int ret;
975
976 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
977 if (!sec)
978 return -ENOMEM;
979
980 qm = &sec->qm;
981 ret = sec_qm_init(qm, pdev);
982 if (ret) {
983 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
984 return ret;
985 }
986
987 sec->ctx_q_num = ctx_q_num;
988 sec_iommu_used_check(sec);
989
990 ret = sec_probe_init(sec);
991 if (ret) {
992 pci_err(pdev, "Failed to probe!\n");
993 goto err_qm_uninit;
994 }
995
996 ret = hisi_qm_start(qm);
997 if (ret) {
998 pci_err(pdev, "Failed to start sec qm!\n");
999 goto err_probe_uninit;
1000 }
1001
1002 ret = sec_debugfs_init(qm);
1003 if (ret)
1004 pci_warn(pdev, "Failed to init debugfs!\n");
1005
1006 if (qm->qp_num >= ctx_q_num) {
1007 ret = hisi_qm_alg_register(qm, &sec_devices);
1008 if (ret < 0) {
1009 pr_err("Failed to register driver to crypto.\n");
1010 goto err_qm_stop;
1011 }
1012 } else {
1013 pci_warn(qm->pdev,
1014 "Failed to use kernel mode, qp not enough!\n");
1015 }
1016
1017 if (qm->uacce) {
1018 ret = uacce_register(qm->uacce);
1019 if (ret) {
1020 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1021 goto err_alg_unregister;
1022 }
1023 }
1024
1025 if (qm->fun_type == QM_HW_PF && vfs_num) {
1026 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1027 if (ret < 0)
1028 goto err_alg_unregister;
1029 }
1030
1031 hisi_qm_pm_init(qm);
1032
1033 return 0;
1034
1035 err_alg_unregister:
1036 if (qm->qp_num >= ctx_q_num)
1037 hisi_qm_alg_unregister(qm, &sec_devices);
1038 err_qm_stop:
1039 sec_debugfs_exit(qm);
1040 hisi_qm_stop(qm, QM_NORMAL);
1041 err_probe_uninit:
1042 sec_probe_uninit(qm);
1043 err_qm_uninit:
1044 sec_qm_uninit(qm);
1045 return ret;
1046 }
1047
sec_remove(struct pci_dev * pdev)1048 static void sec_remove(struct pci_dev *pdev)
1049 {
1050 struct hisi_qm *qm = pci_get_drvdata(pdev);
1051
1052 hisi_qm_pm_uninit(qm);
1053 hisi_qm_wait_task_finish(qm, &sec_devices);
1054 if (qm->qp_num >= ctx_q_num)
1055 hisi_qm_alg_unregister(qm, &sec_devices);
1056
1057 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1058 hisi_qm_sriov_disable(pdev, true);
1059
1060 sec_debugfs_exit(qm);
1061
1062 (void)hisi_qm_stop(qm, QM_NORMAL);
1063
1064 if (qm->fun_type == QM_HW_PF)
1065 sec_debug_regs_clear(qm);
1066
1067 sec_probe_uninit(qm);
1068
1069 sec_qm_uninit(qm);
1070 }
1071
1072 static const struct dev_pm_ops sec_pm_ops = {
1073 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1074 };
1075
1076 static const struct pci_error_handlers sec_err_handler = {
1077 .error_detected = hisi_qm_dev_err_detected,
1078 .slot_reset = hisi_qm_dev_slot_reset,
1079 .reset_prepare = hisi_qm_reset_prepare,
1080 .reset_done = hisi_qm_reset_done,
1081 };
1082
1083 static struct pci_driver sec_pci_driver = {
1084 .name = "hisi_sec2",
1085 .id_table = sec_dev_ids,
1086 .probe = sec_probe,
1087 .remove = sec_remove,
1088 .err_handler = &sec_err_handler,
1089 .sriov_configure = hisi_qm_sriov_configure,
1090 .shutdown = hisi_qm_dev_shutdown,
1091 .driver.pm = &sec_pm_ops,
1092 };
1093
sec_register_debugfs(void)1094 static void sec_register_debugfs(void)
1095 {
1096 if (!debugfs_initialized())
1097 return;
1098
1099 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1100 }
1101
sec_unregister_debugfs(void)1102 static void sec_unregister_debugfs(void)
1103 {
1104 debugfs_remove_recursive(sec_debugfs_root);
1105 }
1106
sec_init(void)1107 static int __init sec_init(void)
1108 {
1109 int ret;
1110
1111 hisi_qm_init_list(&sec_devices);
1112 sec_register_debugfs();
1113
1114 ret = pci_register_driver(&sec_pci_driver);
1115 if (ret < 0) {
1116 sec_unregister_debugfs();
1117 pr_err("Failed to register pci driver.\n");
1118 return ret;
1119 }
1120
1121 return 0;
1122 }
1123
sec_exit(void)1124 static void __exit sec_exit(void)
1125 {
1126 pci_unregister_driver(&sec_pci_driver);
1127 sec_unregister_debugfs();
1128 }
1129
1130 module_init(sec_init);
1131 module_exit(sec_exit);
1132
1133 MODULE_LICENSE("GPL v2");
1134 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1135 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1136 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>");
1137 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1138 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
1139