1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2020 Intel Corporation */ 3 #ifndef ADF_GEN2_HW_DATA_H_ 4 #define ADF_GEN2_HW_DATA_H_ 5 6 #include "adf_accel_devices.h" 7 8 /* Transport access */ 9 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 10 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 11 #define ADF_RING_CSR_RING_CONFIG 0x000 12 #define ADF_RING_CSR_RING_LBASE 0x040 13 #define ADF_RING_CSR_RING_UBASE 0x080 14 #define ADF_RING_CSR_RING_HEAD 0x0C0 15 #define ADF_RING_CSR_RING_TAIL 0x100 16 #define ADF_RING_CSR_E_STAT 0x14C 17 #define ADF_RING_CSR_INT_FLAG 0x170 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 20 #define ADF_RING_CSR_INT_COL_EN 0x17C 21 #define ADF_RING_CSR_INT_COL_CTL 0x180 22 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 23 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 24 #define ADF_RING_BUNDLE_SIZE 0x1000 25 26 #define BUILD_RING_BASE_ADDR(addr, size) \ 27 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 29 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 30 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 33 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 34 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 36 ADF_RING_CSR_E_STAT) 37 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 38 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 39 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value) 40 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 41 do { \ 42 u32 l_base = 0, u_base = 0; \ 43 l_base = (u32)((value) & 0xFFFFFFFF); \ 44 u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \ 45 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 46 ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \ 47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 48 ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \ 49 } while (0) 50 51 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 52 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 53 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value) 54 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 55 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 56 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value) 57 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 58 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 59 ADF_RING_CSR_INT_FLAG, value) 60 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 61 do { \ 62 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 63 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \ 64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 65 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \ 66 } while (0) 67 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 68 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 69 ADF_RING_CSR_INT_COL_EN, value) 70 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 71 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 72 ADF_RING_CSR_INT_COL_CTL, \ 73 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 74 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 75 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 76 ADF_RING_CSR_INT_FLAG_AND_COL, value) 77 78 /* AE to function map */ 79 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190) 80 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310) 81 #define AE2FUNCTION_MAP_REG_SIZE 4 82 #define AE2FUNCTION_MAP_VALID BIT(7) 83 84 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \ 85 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 86 AE2FUNCTION_MAP_REG_SIZE * (index)) 87 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ 88 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 89 AE2FUNCTION_MAP_REG_SIZE * (index), value) 90 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \ 91 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 92 AE2FUNCTION_MAP_REG_SIZE * (index)) 93 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ 94 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 95 AE2FUNCTION_MAP_REG_SIZE * (index), value) 96 97 /* Admin Interface Offsets */ 98 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 99 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 100 #define ADF_MAILBOX_BASE_OFFSET 0x20970 101 102 /* Arbiter configuration */ 103 #define ADF_ARB_OFFSET 0x30000 104 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180 105 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 106 #define ADF_ARB_REG_SLOT 0x1000 107 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C 108 109 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \ 110 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ 111 (ADF_ARB_REG_SLOT * (index)), value) 112 113 /* Power gating */ 114 #define ADF_POWERGATE_DC BIT(23) 115 #define ADF_POWERGATE_PKE BIT(24) 116 117 /* WDT timers 118 * 119 * Timeout is in cycles. Clock speed may vary across products but this 120 * value should be a few milli-seconds. 121 */ 122 #define ADF_SSM_WDT_DEFAULT_VALUE 0x200000 123 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x2000000 124 #define ADF_SSMWDT_OFFSET 0x54 125 #define ADF_SSMWDTPKE_OFFSET 0x58 126 #define ADF_SSMWDT(i) (ADF_SSMWDT_OFFSET + ((i) * 0x4000)) 127 #define ADF_SSMWDTPKE(i) (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000)) 128 129 void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable, 130 int num_a_regs, int num_b_regs); 131 void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops); 132 void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info); 133 void adf_gen2_get_arb_info(struct arb_info *arb_info); 134 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev); 135 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 136 137 #endif 138